Need Pegasos I/II device tree

Hi, Can somebody post the device tree of a Pegasos I (prefered) or a Pegasos II (or any other similar machine) here, please. Thanks! regards, Gerhard -- GMX FreeMail: 1 GB Postfach, 5 E-Mail-Adressen, 10 Free SMS. Alle Infos und kostenlose Anmeldung: http://www.gmx.net/de/go/freemail _

Re: [PATCH v7 3/3] [POWERPC] MPC832x_RDB: update dts to use SPI1in QE, register mmc_spi stub

On Tue, Sep 04, 2007 at 01:17:51AM +0200, Segher Boessenkool wrote: >> I expect very few things from the bootloader: setup memory controller, > > Setup CPUs, clocks and voltages, system busses, system controllers, > memory controllers, memory itself, Yup-yup, these little things. ;-) But clocks an

"atomic" 64-bit math on 32-bit ppc's?

Hi guys, Since this is a generic PPC coding question I figured I'd send it here. We're looking to make the small effort to get ZFS-FUSE working on PPC and there is a need (as is implemented on Solaris) for some 'atomic' math operations to ease multithreading in ZFS. The Solaris PPC code drop inc

Re: Need Pegasos I/II device tree

https://bugzilla.novell.com/attachment.cgi?id=98271 Have fun. -- Matt Sealey <[EMAIL PROTECTED]> Genesi, Manager, Developer Relations Gerhard Pircher wrote: > Hi, > > Can somebody post the device tree of a Pegasos I (prefered) or a Pegasos II > (or any other similar machine) here, please. > >

Re: [RFC] AmigaOne device tree source v2

Original-Nachricht > Datum: Tue, 4 Sep 2007 00:32:57 +0200 > Von: Segher Boessenkool <[EMAIL PROTECTED]> > An: "Gerhard Pircher" <[EMAIL PROTECTED]> > CC: linuxppc-dev@ozlabs.org, David Gibson <[EMAIL PROTECTED]> > Betreff: Re: [RFC] AmigaOne device tree source v2 > PCI memory s

[patch 1/2] PS3: Clear SPU Class 0 interrupts in handler

From: Masato Noguchi <[EMAIL PROTECTED]> Fix a bug that causes the PS3 to hang on the SPU Class 0 interrupt. The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt is delivered as a pulse. The current spu interrupt handler assumes this behavior and does not clear the interrupt

[patch 2/2] Cell: Wrap master run control bit

From: Masato Noguchi <[EMAIL PROTECTED]> Add platform specific SPU run control routines. The current spufs_run_spu() implementation uses the SPU master run control bit (MFC_SR1[S]) to control SPE execution, but the PS3 hypervisor does not support the use of this feature. This change adds run co

Re: "atomic" 64-bit math on 32-bit ppc's?

On Tue, Sep 04, 2007 at 12:09:22PM +0100, Matt Sealey wrote: > Hi guys, > > Since this is a generic PPC coding question I figured I'd send it here. > We're > looking to make the small effort to get ZFS-FUSE working on PPC and there is > a need (as is implemented on Solaris) for some 'atomic' math

Re: [RFC] AmigaOne device tree source v2

Original-Nachricht > Datum: Tue, 4 Sep 2007 00:52:02 +0200 > Von: Segher Boessenkool <[EMAIL PROTECTED]> > An: "Gerhard Pircher" <[EMAIL PROTECTED]> > CC: linuxppc-dev@ozlabs.org, David Gibson <[EMAIL PROTECTED]> > Betreff: Re: [RFC] AmigaOne device tree source v2 > >>> Yeah, PC

Re: "atomic" 64-bit math on 32-bit ppc's?

Gabriel Paubert wrote: > On Tue, Sep 04, 2007 at 12:09:22PM +0100, Matt Sealey wrote: >> Hi guys, >> >> The Solaris PPC code drop included most of these functions for 32-bit ops on >> 32-bit PPC architectures but the 64-bit operations are not present. What I >> a not clear on is the operation of l

Re: [patch 5/6] Walnut board support

On Sun, 02 Sep 2007 08:59:06 -0500 Josh Boyer <[EMAIL PROTECTED]> wrote: > On Mon, 2007-09-03 at 11:11 +1000, David Gibson wrote: > > On Fri, Aug 31, 2007 at 03:04:54PM -0500, Josh Boyer wrote: > > > Board support for the PPC405 Walnut evaluation board > > > > > > Signed-off-by: Josh Boyer <[EMAI

Re: [patch 3/6] Walnut DTS

On Sun, 02 Sep 2007 08:59:44 -0500 Josh Boyer <[EMAIL PROTECTED]> wrote: > On Mon, 2007-09-03 at 11:08 +1000, David Gibson wrote: > > On Fri, Aug 31, 2007 at 03:04:52PM -0500, Josh Boyer wrote: > > > Device tree source file for the PPC405 Walnut evaluation board. > > > > > > Signed-off-by: Josh B

Re: Regarding immap_86xx.h

On Sep 4, 2007, at 1:38 AM, sivaji wrote: > > Hi, > I am using 2.6.23-rc3 kernel. In this kernel immap_86xx.h > file was > loacted in the path: include/asm-powerpc/immap_86xx.h. > > This file contains only PCI and Global utility Regsiters > Declarations. LocalBus Controller,

Newbie on embedded linux on PPC: error: cannot find boot.o

hi folks, my name is thomas trying to make embedded linux run on a powerpc, but we've got special boards here, although we use a xilinx virtex4 fpga... as you said in the nabble-thread (see subject), i set up edk9.1 software platform settings und ran libgen to get the xparameters* files. i cop

Re: ppc Floating Point support status

On Wednesday 22 August 2007 15:52:09 Kumar Gala wrote: > On Aug 22, 2007, at 1:37 PM, Ben Buchli wrote: > > Hello everybody, > > I was wondering what the status was on supporting floating-point > > instructions > > for the mpc8548. I found the suggested patch: > > http://patchwork.ozlabs.org/linux

Re: Newbie on embedded linux on PPC: error: cannot find boot.o

On 9/4/07, Thomas Gerlach <[EMAIL PROTECTED]> wrote: > hi folks, > > > my name is thomas trying to make embedded linux run on a powerpc, but we've > got special boards here, although we use a xilinx virtex4 fpga... > > as you said in the nabble-thread (see subject), i set up edk9.1 software > pla

Re: "atomic" 64-bit math on 32-bit ppc's?

On Tue, Sep 04, 2007 at 01:31:07PM +0100, Matt Sealey wrote: > > Gabriel Paubert wrote: > >On Tue, Sep 04, 2007 at 12:09:22PM +0100, Matt Sealey wrote: > >>Hi guys, > >> > >>The Solaris PPC code drop included most of these functions for 32-bit ops > >>on > >>32-bit PPC architectures but the 64-bi

Re: Regarding immap_86xx.h

Kumar Gala wrote: > Its most likely been removed since these structures have been > distributed to the places they are used. Not only that, but I submitted a patch to remove the PCI structure, so all that's left is the GUTS structure. The GUTS structure is different from other devices since i

Re: "atomic" 64-bit math on 32-bit ppc's?

Gabriel Paubert wrote: > I don't know at all the ZFS code, not any filesystem code for the > matter. But how many spinlocks would you have to take and release > per actual disk operation? I have no idea, but considering the space supported by the filesystem it's probably a hell of a lot. It seem

Re: [PATCH v7 3/3] [POWERPC] MPC832x_RDB: update dts to use SPI1in QE, register mmc_spi stub

On Tue, Sep 04, 2007 at 02:47:50PM +0400, Anton Vorontsov wrote: > > _and system GPIOs_ :-) > > Yup, firmware should set up gpios, to make initial kernel boot. No, it should set all pins and similar setup-once type initialization that is board-specific rather than device-specific -- there's no re

Re: "atomic" 64-bit math on 32-bit ppc's?

On Tue, Sep 04, 2007 at 01:39:37PM +0200, Gabriel Paubert wrote: > That's wrong if lock is assigned to r0, you should use > a "b" constraint to avoid this. Same for atomic_dec below. GCC should really have removed r0 from the "r" class (it isn't truly a general-purpose register), and had a differe

Re: [PATCH 3/9] cpm2: Add SCCs to cpm2_clk_setup(), and cpm2_smc_clk_setup().

On Thu, 30 Aug 2007 15:15:00 -0500 Scott Wood wrote: > On Thu, Aug 30, 2007 at 02:25:48AM +0400, Vitaly Bordug wrote: > > I would have it in the same patch, that adds clocking stuff to 8xx. > > I was trying to keep the 8xx and 82xx patchsets reasonably separate. > > > And maybe in the same, segr

Re: [PATCH v7 3/3] [POWERPC] MPC832x_RDB: update dts to use SPI1in QE, register mmc_spi stub

On Tue, 4 Sep 2007 13:20:28 -0500 Scott Wood wrote: > > > _and system GPIOs_ :-) > > > > Yup, firmware should set up gpios, to make initial kernel boot. > > No, it should set all pins and similar setup-once type initialization > that is board-specific rather than device-specific -- there's n

Re: [PATCH 4/9] cpm2: Add cpm2_set_pin().

On Tue, 28 Aug 2007 15:19:24 -0500 Scott Wood wrote: > This provides a generic way for board code to set up CPM pins, rather > than directly poking magic values into registers. > Please provide more info either here or somewhere in Documentation/, or inside the code at least. We're adding new ut

Re: [patch 2/2] Cell: Wrap master run control bit

On Tuesday 04 September 2007, Geoff Levand wrote: > > From: Masato Noguchi <[EMAIL PROTECTED]> > > Add platform specific SPU run control routines. > > The current spufs_run_spu() implementation uses the SPU master > run control bit (MFC_SR1[S]) to control SPE execution, but the > PS3 hypervisor

Re: [patch 2/2] Cell: Wrap master run control bit

On Wednesday 05 September 2007, Arnd Bergmann wrote: > On Tuesday 04 September 2007, Geoff Levand wrote: > > > > From: Masato Noguchi <[EMAIL PROTECTED]> > > > > Add platform specific SPU run control routines. > > > > The current spufs_run_spu() implementation uses the SPU master > > run control

Re: [patch 1/2] PS3: Clear SPU Class 0 interrupts in handler

On Tuesday 04 September 2007, Geoff Levand wrote: > From: Masato Noguchi <[EMAIL PROTECTED]> > > Fix a bug that causes the PS3 to hang on the SPU Class 0 interrupt. > > The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt > is delivered as a pulse.  The current spu interrupt ha

[POWERPC] flags as passed to spin_*_irqsave() should be unsigned long.

Signed-off-by: Tony Breeds <[EMAIL PROTECTED]> --- Found trying to build a -rt kernel, which has a BUILD_BUG_ON(), in this caswe. drivers/net/pasemi_mac.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Index: working/drivers/net/pasemi_mac.c ===

Re: [POWERPC] flags as passed to spin_*_irqsave() should be unsigned long.

On Wed, Sep 05, 2007 at 10:23:14AM +1000, Tony Breeds wrote: > Signed-off-by: Tony Breeds <[EMAIL PROTECTED]> > > --- > Found trying to build a -rt kernel, which has a BUILD_BUG_ON(), in this > caswe. Thanks, applied. I'll batch it up with the next set of updates to jgarzik. -Olof

Re: "atomic" 64-bit math on 32-bit ppc's?

On Tue, Sep 04, 2007 at 01:31:07PM +0100, Matt Sealey wrote: > > Gabriel Paubert wrote: > > On Tue, Sep 04, 2007 at 12:09:22PM +0100, Matt Sealey wrote: > >> Hi guys, > >> > >> The Solaris PPC code drop included most of these functions for 32-bit ops > >> on > >> 32-bit PPC architectures but the

Re: [patch 5/6] Walnut board support

On Tue, Sep 04, 2007 at 07:37:41AM -0500, Josh Boyer wrote: > On Sun, 02 Sep 2007 08:59:06 -0500 > Josh Boyer <[EMAIL PROTECTED]> wrote: > > > On Mon, 2007-09-03 at 11:11 +1000, David Gibson wrote: > > > On Fri, Aug 31, 2007 at 03:04:54PM -0500, Josh Boyer wrote: > > > > Board support for the PPC4

Re: [patch 2/6] cuimage for Bamboo board

On Mon, Sep 03, 2007 at 08:42:11AM -0500, Josh Boyer wrote: > On Mon, 2007-09-03 at 11:01 +1000, David Gibson wrote: > > On Fri, Aug 31, 2007 at 03:04:51PM -0500, Josh Boyer wrote: > > > Add a cuboot wrapper for the Bamboo board. This also removes some > > > obsoleted > > > linker declarations th

Re: [patch 3/6] Walnut DTS

On Tue, Sep 04, 2007 at 07:42:03AM -0500, Josh Boyer wrote: > On Sun, 02 Sep 2007 08:59:44 -0500 > Josh Boyer <[EMAIL PROTECTED]> wrote: [snip] > > > > + POB0: opb { > > > > + compatible = "ibm,opb"; > > > > > > Need an opb-405gp here, too. > > > > Yep. > > Fi

Re: [RFC] AmigaOne device tree source v2

On Tue, Sep 04, 2007 at 01:49:45PM +0200, Gerhard Pircher wrote: > > Original-Nachricht > > Datum: Tue, 4 Sep 2007 00:32:57 +0200 > > Von: Segher Boessenkool <[EMAIL PROTECTED]> > > An: "Gerhard Pircher" <[EMAIL PROTECTED]> > > CC: linuxppc-dev@ozlabs.org, David Gibson <[EMAIL PR

Re: Document and implement an improved flash device binding

On Mon, Sep 03, 2007 at 12:23:34PM +0200, Segher Boessenkool wrote: > >+ j) CFI or JEDEC memory-mapped NOR flash > > > > Flash chips (Memory Technology Devices) are often used for solid > >state > > file systems on embedded devices. > > Well, almost everything has a NOR flash on it, not

Please pull from 'for-2.6.24' branch

Paul, Please pull from 'for-2.6.24' branch of

Re: [patch 5/6] Walnut board support

On Fri, Aug 31, 2007 at 03:04:54PM -0500, Josh Boyer wrote: > Board support for the PPC405 Walnut evaluation board > > Signed-off-by: Josh Boyer <[EMAIL PROTECTED]> Acked-by: David Gibson <[EMAIL PROTECTED]> -- David Gibson| I'll have my music baroque, and my code david AT g

[POWERPC] pasemi: add pasemi_pci_getcfgaddr()

commit aa37284d64c33d4755072d4bb4b5b1304d415d97 Author: Olof Johansson <[EMAIL PROTECTED]> Date: Sat Sep 1 15:43:52 2007 -0500 [POWERPC] pasemi: add pasemi_pci_getcfgaddr() Add pasemi_pci_getcfgaddr(), to get the remapped address of a specific config register for a PCI device.

[POWERPC] pasemi: Add workaround for erratum 5945

commit 3f7a4e905341e46e7b442a9326c3b31229e25209 Author: Olof Johansson <[EMAIL PROTECTED]> Date: Mon Sep 3 00:11:49 2007 -0500 [POWERPC] pasemi: Add workaround for erratum 5945 Erratum 5945 causes some of the registers on the PCIe root ports to not read correctly. Do a small da

[POWERPC] pasemi: Export more SPRs to sysfs when CONFIG_DEBUG_KERNEL=y

commit e34d30c44975ed7db1542f6548f2716185c87baf Author: Olof Johansson <[EMAIL PROTECTED]> Date: Sat Sep 1 14:45:07 2007 -0500 [POWERPC] pasemi: Export more SPRs to sysfs when CONFIG_DEBUG_KERNEL=y Export some of the implementation-specific registers via sysfs. Useful when debug

[POWERPC] pasemi: Print more information at machine check

commit c456a6cdfe86cb0e2e2187f5e76768f9215e0693 Author: Olof Johansson <[EMAIL PROTECTED]> Date: Tue Sep 4 21:49:51 2007 -0500 [POWERPC] pasemi: Print more information at machine check Add printout of some SoC error status registers, and dump the SLB contents for those machine c

[POWERPC] pasemi: Move pasemi_idle_init() to late_initcall()

commit 6a30bd1e2160e921a8fb051b472dfaf068f4f386 Author: Olof Johansson <[EMAIL PROTECTED]> Date: Tue Sep 4 21:53:30 2007 -0500 [POWERPC] pasemi: Move pasemi_idle_init() to late_initcall() Move pasemi_idle_init() to be a late_initcall instead of being called from setup_arch(). Th

Re: [patch 3/6] Walnut DTS

On Wed, 2007-09-05 at 12:36 +1000, David Gibson wrote: > On Tue, Sep 04, 2007 at 07:42:03AM -0500, Josh Boyer wrote: > > On Sun, 02 Sep 2007 08:59:44 -0500 > > Josh Boyer <[EMAIL PROTECTED]> wrote: > [snip] > > > > > + POB0: opb { > > > > > + compatible = "ibm,opb";

Re: [patch 2/6] cuimage for Bamboo board

On Wed, 2007-09-05 at 11:10 +1000, David Gibson wrote: > On Mon, Sep 03, 2007 at 08:42:11AM -0500, Josh Boyer wrote: > > On Mon, 2007-09-03 at 11:01 +1000, David Gibson wrote: > > > On Fri, Aug 31, 2007 at 03:04:51PM -0500, Josh Boyer wrote: > > > > Add a cuboot wrapper for the Bamboo board. This

[PATCH] powerpc: Remove unused platform_machine_check()

Remove leftover cruft from ARCH=ppc. There are no users of platform_machine_check() in ARCH=powerpc, and none should be added (they should use ppc_md.machine_check_handler instead). Signed-off-by: Olof Johansson <[EMAIL PROTECTED]> diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/

[PATCH] powerpc: Don't use generic machine check parsing everywhere

If a platform provide it's own machine check handler, assume that code will handle the reason parsing and reporting the error. The current default fall-though only makes sense on a few 32-bit platforms that lack individual handlers. Signed-off-by: Olof Johansson <[EMAIL PROTECTED]> diff --git

[PATCH] powerpc: Move lowlevel runlatch calls under cpu feature control

There's no need to call the runlatch on functions on processors that don't implement them (CPU_FTR_CTRL). Signed-off-by: Olof Johansson <[EMAIL PROTECTED]> diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 33c4e8c..cec5908 100644 --- a/arch/powerpc/kernel/head_6

[PATCH] powerpc: Remove warning in arch/powerpc/kernel/sysfs.c

arch/powerpc/kernel/sysfs.c: In function 'cpu_add_sysdev_attr_group': arch/powerpc/kernel/sysfs.c:388: warning: ignoring return value of 'sysfs_create_group', declared with attribute warn_unused_result Signed-off-by: Olof Johansson <[EMAIL PROTECTED]> diff --git a/arch/powerpc/kernel/

[PATCH] powerpc: Add workaround for MPICs with broken register reads

Some versions of PWRficient 1682M have an interrupt controller in which the first register in each pair for interrupt sources doesn't always read with the right polarity/sense values. To work around this, keep a software copy of the register instead. Since it's not modified from the mpic itsel

Keep On Debugging You

I wrote this last year in frustration with an out-of-order execution bug I was trying to fix. Keep On Debugging You Sung to the tune of REO Speedwagon's "Keep on Loving' You" You should've seen by the opcodes in the queue, baby There was something missin' You should known by the registers, too

Re: [patch 2/6] cuimage for Bamboo board

On Tue, Sep 04, 2007 at 07:40:19PM -0500, Josh Boyer wrote: > On Wed, 2007-09-05 at 11:10 +1000, David Gibson wrote: > > On Mon, Sep 03, 2007 at 08:42:11AM -0500, Josh Boyer wrote: > > > On Mon, 2007-09-03 at 11:01 +1000, David Gibson wrote: > > > > On Fri, Aug 31, 2007 at 03:04:51PM -0500, Josh Bo