On Mon, 2008-03-17 at 17:13 +0100, Laurent Pinchart wrote:
> The PIC I am working with is linked to a falling-edge external irq on the
> CPM2. When the first PIC interrupt was generated the kernel called the PIC
> chained irq handler endlessly.
>
> After some investigation it turned out the ex
On Thursday 13 March 2008 14:56, Laurent Pinchart wrote:
> Hi Michael,
>
> On Wednesday 12 March 2008 01:51, Michael Ellerman wrote:
> > On Tue, 2008-03-11 at 11:58 +0100, Laurent Pinchart wrote:
> > > Hi everybody,
> > >
> > > is there any documentation describing interrupt handling for the
> > >
Hi Michael,
On Wednesday 12 March 2008 01:51, Michael Ellerman wrote:
> On Tue, 2008-03-11 at 11:58 +0100, Laurent Pinchart wrote:
> > Hi everybody,
> >
> > is there any documentation describing interrupt handling for the powerpc
> > architecture ? I'm writing a driver for a cascaded interrupt con
On Tue, 2008-03-11 at 11:58 +0100, Laurent Pinchart wrote:
> Hi everybody,
>
> is there any documentation describing interrupt handling for the powerpc
> architecture ? I'm writing a driver for a cascaded interrupt controller and
> the only source of information I found was the code.
I don't th
Hi everybody,
is there any documentation describing interrupt handling for the powerpc
architecture ? I'm writing a driver for a cascaded interrupt controller and
the only source of information I found was the code.
I'm particularly interested in information about irq hosts (allocation and
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