On Mon, Mar 06, 2017 at 04:46:46PM +1100, Michael Ellerman wrote:
> Hmm, which p9 mambo is this? I get:
>
> test: cache_shape
> tags: git_version:v4.10-10927-g0a55d1671c33
> L1I cache size: 0x8000 32768B 32K
> L1I line size:0x80 128-way associative
> L1D cache siz
Paul Clarke writes:
> P9 (with bad device-tree):
> --
> # ./cache_shape
> test: cache_shape
> tags: git_version:v4.10-0-gc470abd-dirty
> L1I cache size: 0 0B 0K
> L1I line size:0x80 fully associative
> L1D cache size: 0 0B 0K
>
On Fri, 2017-03-03 at 07:51 -0600, Paul Clarke wrote:
> > On P9 it all comes from the device tree so if that's wrong the AUX
> > vectors will definitely be wrong.
>
> mambo-p9 is still falling victim to the device-tree, but "working":
> --
> getauxval(AT_L1I_CACHEGEOMETRY) = 0x0080
> A
On 03/02/2017 10:01 PM, Michael Ellerman wrote:
Paul Clarke writes:
On 03/02/2017 12:33 AM, Michael Ellerman wrote:
Paul Clarke writes:
On 02/02/2017 12:22 AM, Benjamin Herrenschmidt wrote:
This adds AUX vectors for the L1I,D, L2 and L3 cache levels
providing for each cache level the size o
Paul Clarke writes:
> On 03/02/2017 12:33 AM, Michael Ellerman wrote:
>> Paul Clarke writes:
>>> On 02/02/2017 12:22 AM, Benjamin Herrenschmidt wrote:
This adds AUX vectors for the L1I,D, L2 and L3 cache levels
providing for each cache level the size of the cache in bytes
and the
On 03/02/2017 12:33 AM, Michael Ellerman wrote:
Paul Clarke writes:
On 02/02/2017 12:22 AM, Benjamin Herrenschmidt wrote:
This adds AUX vectors for the L1I,D, L2 and L3 cache levels
providing for each cache level the size of the cache in bytes
and the geometry (line size and number of ways).
Paul Clarke writes:
> On 02/02/2017 12:22 AM, Benjamin Herrenschmidt wrote:
>> This adds AUX vectors for the L1I,D, L2 and L3 cache levels
>> providing for each cache level the size of the cache in bytes
>> and the geometry (line size and number of ways).
>>
>> We chose to not use the existing al
On 02/02/2017 12:22 AM, Benjamin Herrenschmidt wrote:
This adds AUX vectors for the L1I,D, L2 and L3 cache levels
providing for each cache level the size of the cache in bytes
and the geometry (line size and number of ways).
We chose to not use the existing alpha/sh definition which
packs all th
This adds AUX vectors for the L1I,D, L2 and L3 cache levels
providing for each cache level the size of the cache in bytes
and the geometry (line size and number of ways).
We chose to not use the existing alpha/sh definition which
packs all the information in a single entry per cache level as
it is
