On 06/17/2013 09:49:19 PM, Lian Minghuan-b31939 wrote:
On 06/18/2013 08:42 AM, Scott Wood wrote:
On 06/17/2013 07:28:07 PM, Scott Wood wrote:
On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
+compatible = "fsl,mpic-msi";
+reg = <0x41600 0x200 0x44140 4>;
Why 0x200?
[Minghuan]
On 06/18/2013 08:42 AM, Scott Wood wrote:
On 06/17/2013 07:28:07 PM, Scott Wood wrote:
On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
+compatible = "fsl,mpic-msi";
+reg = <0x41600 0x200 0x44140 4>;
Why 0x200?
[Minghuan] The offsets of the MSIA registers are from 0x41600 to
0
On 06/17/2013 07:28:07 PM, Scott Wood wrote:
On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
+compatible = "fsl,mpic-msi";
+reg = <0x41600 0x200 0x44140 4>;
Why 0x200?
[Minghuan] The offsets of the MSIA registers are from 0x41600 to
0x417ff, and the size is 0x200.
offset 0x4
On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
Hi Soctt,
please see my comments.
On 06/15/2013 06:06 AM, Scott Wood wrote:
On 06/14/2013 02:15:57 AM, Minghuan Lian wrote:
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI regist
Hi Soctt,
please see my comments.
On 06/15/2013 06:06 AM, Scott Wood wrote:
On 06/14/2013 02:15:57 AM, Minghuan Lian wrote:
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses diffe
On 06/14/2013 02:15:57 AM, Minghuan Lian wrote:
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecuti
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecutive. It is hard to use
'msi-available-ranges' to de
