On Wed, Jan 29, 2025 at 06:20:31PM +1000, Nicholas Piggin wrote:
> Perfectly reasonable to not add broadcast tlbie in microwatt.
If you call "the easy way out" reasonable, then sure. This pretty
trivial hardware addition causes so many software headaches whenn
missing, it isn't funny. "Friends d
On Wed, Jan 29, 2025 at 06:18:54PM +1100, Paul Mackerras wrote:
> Interesting. I looked in my copy of v2.07 (PowerISA_V2.07_PUBLIC.pdf)
> and it mentions rfscv in a couple of places, but has no description of
> scv or rfscv. I'll change it to v3.0.
Huh, rfscv is 3.0 and later according to later
On Wed, Jan 29, 2025 at 04:36:14PM +1000, Nicholas Piggin wrote:
> On Wed Jan 29, 2025 at 8:52 AM AEST, Paul Mackerras wrote:
> > Microwatt now implements ISA v3.1 (SFFS compliancy subset), including
> > prefixed instructions, scv/rfscv, and the FSCR, HFSCR, TAR, and CTRL
> > registers. The privil
On Wed, Jan 29, 2025 at 09:52:09AM +1100, Paul Mackerras wrote:
> - isa = <3000>;
> + isa = <3010>;
Does this mean 3.1, or 3.01? If the former, can this also encode 3.1C?
Should uwatt say to support that?
> little-endian {
> -
On Wed Jan 29, 2025 at 5:18 PM AEST, Paul Mackerras wrote:
> On Wed, Jan 29, 2025 at 04:36:14PM +1000, Nicholas Piggin wrote:
>> On Wed Jan 29, 2025 at 8:52 AM AEST, Paul Mackerras wrote:
>> > Microwatt now implements ISA v3.1 (SFFS compliancy subset), including
>> > prefixed instructions, scv/rfsc
On Wed, Jan 29, 2025 at 04:36:14PM +1000, Nicholas Piggin wrote:
> On Wed Jan 29, 2025 at 8:52 AM AEST, Paul Mackerras wrote:
> > Microwatt now implements ISA v3.1 (SFFS compliancy subset), including
> > prefixed instructions, scv/rfscv, and the FSCR, HFSCR, TAR, and CTRL
> > registers. The privil
On Wed Jan 29, 2025 at 8:52 AM AEST, Paul Mackerras wrote:
> Microwatt now implements ISA v3.1 (SFFS compliancy subset), including
> prefixed instructions, scv/rfscv, and the FSCR, HFSCR, TAR, and CTRL
> registers. The privileged mode of operation is now hypervisor mode
> and there is no privilege
Microwatt now implements ISA v3.1 (SFFS compliancy subset), including
prefixed instructions, scv/rfscv, and the FSCR, HFSCR, TAR, and CTRL
registers. The privileged mode of operation is now hypervisor mode
and there is no privileged non-hypervisor mode; the MSR[HV] bit is
forced to 1.
Besides upd
