On Wed, 4 Mar 2009 20:48:45 +0300
Anton Vorontsov wrote:
> But I see the point of confusion... Instead of teaching
> "SDHCI core" to work with 32 bits hosts, we'd better handle this
> in the eSDHC part, in the accessors.
>
> This is relatively trivial and should not cause much overhead
> (at lea
On Sat, Feb 21, 2009 at 04:58:33PM +0100, Pierre Ossman wrote:
> On Fri, 13 Feb 2009 17:47:22 +0300
> Anton Vorontsov wrote:
>
> > SDHCI driver must take special care when working with "triggering"
> > registers on hosts with strict 32 bit addressing.
> >
> > In FSL eSDHC hosts all registers are
On Fri, 13 Feb 2009 17:47:22 +0300
Anton Vorontsov wrote:
> SDHCI driver must take special care when working with "triggering"
> registers on hosts with strict 32 bit addressing.
>
> In FSL eSDHC hosts all registers are 32 bit width, writing to the
> first half of any register will cause [undefi
SDHCI driver must take special care when working with "triggering"
registers on hosts with strict 32 bit addressing.
In FSL eSDHC hosts all registers are 32 bit width, writing to the
first half of any register will cause [undefined?] write the second
half of the register. That is, 16 bit write to
SDHCI driver must take special care when working with "triggering"
registers on hosts with strict 32 bit addressing.
In FSL eSDHC hosts all registers are 32 bit width, writing to the
first half of any register will cause [undefined?] write the second
half of the register. That is, 16 bit write to
