Hi all,
we've had a long standing problems where drivers try to hook into the
DMA_OPS mechanisms to override them for something that is not DMA, or
to introduce additional dispatching.
Now that we are not using DMA_OPS support for dma-iommu and can build
kernels without DMA_OPS support on many co
DMA ops are a helper for architectures and not for drivers to override
the DMA implementation. Unfortunately driver authors keep ignoring
this. Make this more clear by renaming the symbol to ARCH_DMA_OPS,
have the three drivers overriding it depend on that. They should
probably also be marked br
On 8/23/24 9:19 PM, Segher Boessenkool wrote:
Hi!
On Fri, Aug 23, 2024 at 03:54:59PM +0200, Christoph Hellwig wrote:
On Fri, Aug 23, 2024 at 08:06:00AM -0500, Segher Boessenkool wrote:
What does "uncached memory" even mean here? Literally it would be
I=1 memory (uncachEABLE memory), but more
Hi!
On Fri, Aug 23, 2024 at 03:54:59PM +0200, Christoph Hellwig wrote:
> On Fri, Aug 23, 2024 at 08:06:00AM -0500, Segher Boessenkool wrote:
> > What does "uncached memory" even mean here? Literally it would be
> > I=1 memory (uncachEABLE memory), but more likely you want M=0 memory
> > here ("no
On Fri, Aug 23, 2024 at 06:08:36PM +0100, Will Deacon wrote:
> On Fri, Aug 23, 2024 at 05:41:06PM +0100, Catalin Marinas wrote:
> > On Fri, Aug 23, 2024 at 03:45:32PM +0100, Will Deacon wrote:
> > > On Thu, Aug 22, 2024 at 04:10:49PM +0100, Joey Gouly wrote:
> > > > +static void permission_overlay_
Hi Geert,
On Fri, 2024-08-23 at 15:13 +0200, Geert Uytterhoeven wrote:
> IMHO CRASH_DUMP should just default to n, like most kernel options, as
> it enables non-trivial extra functionality: the kernel source tree has
> more than 100 locations that check if CONFIG_CRASH_DUMP is enabled.
I guess we
On Fri, Aug 23, 2024 at 05:41:06PM +0100, Catalin Marinas wrote:
> On Fri, Aug 23, 2024 at 03:45:32PM +0100, Will Deacon wrote:
> > On Thu, Aug 22, 2024 at 04:10:49PM +0100, Joey Gouly wrote:
> > > +static void permission_overlay_switch(struct task_struct *next)
> > > +{
> > > + if (!system_support
Le 23/08/2024 à 08:24, Kunwu Chan a écrit :
[Vous ne recevez pas souvent de courriers de kunwu.c...@linux.dev. Découvrez
pourquoi ceci est important à https://aka.ms/LearnAboutSenderIdentification ]
From: Kunwu Chan
Since commit d492cc2573a0 ("driver core: device.h: make struct
bus_type a
On Fri, Aug 23, 2024 at 03:45:32PM +0100, Will Deacon wrote:
> On Thu, Aug 22, 2024 at 04:10:49PM +0100, Joey Gouly wrote:
> > +static void permission_overlay_switch(struct task_struct *next)
> > +{
> > + if (!system_supports_poe())
> > + return;
> > +
> > + current->thread.por_el0 =
Le 22/08/2024 à 17:25, cuigaosheng a écrit :
[Vous ne recevez pas souvent de courriers de cuigaoshe...@huawei.com.
Découvrez pourquoi ceci est important à
https://aka.ms/LearnAboutSenderIdentification ]
On 2024/8/22 22:16, LEROY Christophe wrote:
Le 22/08/2024 à 15:06, Gaosheng Cui a écri
VFIO_EEH_PE_INJECT_ERR ioctl is currently failing on pseries
due to missing implementation of err_inject eeh_ops for pseries.
This patch implements pseries_eeh_err_inject in eeh_ops/pseries
eeh_ops. Implements support for injecting MMIO load/store error
for testing from user space.
The check on PC
On Thu, Aug 22, 2024 at 04:10:49PM +0100, Joey Gouly wrote:
> POR_EL0 is a register that can be modified by userspace directly,
> so it must be context switched.
>
> Signed-off-by: Joey Gouly
> Cc: Catalin Marinas
> Cc: Will Deacon
> Reviewed-by: Catalin Marinas
> ---
> arch/arm64/include/asm
On Fri, 23 Aug 2024 14:48:11 +0100,
Will Deacon wrote:
>
> On Thu, Aug 22, 2024 at 04:10:51PM +0100, Joey Gouly wrote:
> > To allow using newer instructions that current assemblers don't know about,
> > replace the `at` instruction with the underlying SYS instruction.
> >
> > Signed-off-by: Joey
On Fri, Aug 23, 2024 at 08:06:00AM -0500, Segher Boessenkool wrote:
> What does "uncached memory" even mean here? Literally it would be
> I=1 memory (uncachEABLE memory), but more likely you want M=0 memory
> here ("non-memory memory", "not well-behaved memory", MMIO often).
Regular kernel memory
On Thu, Aug 22, 2024 at 04:10:51PM +0100, Joey Gouly wrote:
> To allow using newer instructions that current assemblers don't know about,
> replace the `at` instruction with the underlying SYS instruction.
>
> Signed-off-by: Joey Gouly
> Cc: Marc Zyngier
> Cc: Oliver Upton
> Cc: Catalin Marinas
On Thu, Aug 22, 2024 at 04:10:47PM +0100, Joey Gouly wrote:
> Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2.
>
> Signed-off-by: Joey Gouly
> Cc: Catalin Marinas
> Cc: Will Deacon
> Acked-by: Catalin Marinas
> Reviewed-by: Anshuman Khandual
> ---
> arch/arm64/include/asm/el2
arc nsimosci_hs_defconfig gcc-13.2.0
arc nsimosci_hs_smp_defconfig gcc-13.2.0
arc randconfig-001-20240823 gcc-13.2.0
arc randconfig-002-20240823 gcc-13.2.0
arcvdk_hs38_smp_defconfig gcc-13.2.0
arm
Hi!
On Thu, Aug 22, 2024 at 06:39:33AM +, LEROY Christophe wrote:
> Le 22/08/2024 à 07:32, Christoph Hellwig a écrit :
> > On Thu, Aug 22, 2024 at 05:25:10AM +, LEROY Christophe wrote:
> >>> and this results in a call to dma_direct_allocation(), which has one
> >>> innocent looking memset(
gcc-13.2.0
arc nsimosci_hs_defconfig gcc-13.2.0
arc nsimosci_hs_smp_defconfig gcc-13.2.0
arc randconfig-001-20240823 gcc-13.2.0
arc randconfig-002-20240823 gcc-13.2.0
arcvdk_hs38_smp_defconfig gcc
Fixes boot failures on 6.9 on PPC_BOOK3S_32 machines using
Open Firmware. On these machines, the kernel refuses to boot
from non-zero PHYSICAL_START, which occurs when CRASH_DUMP is on.
Since most PPC_BOOK3S_32 machines boot via Open Firmware, it should
default to off for them. Users booting via s
On 2024-08-23 07:58, Dave Vasilevsky wrote:
> On 2024-08-23 03:16, John Paul Adrian Glaubitz wrote:
>> It should be disabled on m68k and sh by default as well.
>
> Sure, I can change that. What's the reasoning, so I can explain in my commit
> message?
Oh I don't think m68k even has ARCH_SUPPORTS
On 2024-08-23 03:16, John Paul Adrian Glaubitz wrote:
> It should be disabled on m68k and sh by default as well.
Sure, I can change that. What's the reasoning, so I can explain in my commit
message?
-Dave
On a CPU/Memory hotplug event, the kexec lock is taken to update the
kdump image. At the same time, this lock is also required to report
the support for crash hotplug to user-space via the
/sys/devices/system/[cpu|memory]/crash_hotplug sysfs interface, to
avoid kdump reload.
The kexec lock is need
The maple platform was added in 2004 [1], to support the "Maple" 970FX
evaluation board.
It was later used for IBM JS20/JS21 machines, as well as the Bimini
machine, aka "Yellow Dog Powerstation".
Sadly all those machines have passed into memory, and there's been no
evidence for years that anyone
These two drivers are only buildable for the powerpc "maple" platform,
which has now been removed. Remove the drivers.
Signed-off-by: Michael Ellerman
---
drivers/edac/Kconfig| 18 --
drivers/edac/Makefile | 2 -
drivers/edac/amd8111_edac.c | 596
This driver is no longer buildable since the PPC_MAPLE platform was
removed. Remove the driver.
Note that the comment in the driver says it supports "SMU & 970FX
based G5 Macs", but that's not true, that comment was copied from
pmac64-cpufreq.c, which still exists and continues to support those
ma
Le 08/08/2024 à 09:11, Herve Codina a écrit :
The Freescale QMC controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff
Le 08/08/2024 à 09:11, Herve Codina a écrit :
The QUICC Engine (QE) QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Handle this optional 'soft-qmc' firmware.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 67 +++
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instea
Le 08/08/2024 à 09:11, Herve Codina a écrit :
The PUSHSCHED command is missing in the QE header file.
This command is supported on MPC8321 and is used to modify the start
address for the task running on a given peripheral. It is needed for the
QMC in order to perform the re-initialization pro
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Introduce devm_cpm_muram_alloc() and devm_cpm_muram_alloc_fixed(), the
resource-managed version of cpm_muram_alloc and cpm_muram_alloc_fixed().
These resource-managed versions simplify the user avoiding the need to
call cpm_muram_free(). Indeed, t
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles the CPM1 version of QMC.
In order to prepare the support for the QUICC Engine (QE) version of
QMC, introduce qmc_version to identify versions. This will enable the
code to make the distinction between several QMC implementatio
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles CPM1 version of QMC. Even if GSMRL is specific to
the CPM1 version, the exact same purpose and format register (GUMRL) is
present in the QUICC Engine (QE) version of QMC. Compared to the QE
version, the values defined for the m
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles the CPM1 version of QMC, RPACK does not need to
be initialized. This is not the case in the QUICC Engine (QE) version.
In preparation of the support for QE, initialize the RPACK register
when the receiver is initialized and ea
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles CPM1 version of QMC and qmc_chan_command() is
clearly CPM1 specific.
In order to prepare the support for the QUICC Engine (QE) version,
rename qmc_chan_command() to reflect that point.
Signed-off-by: Herve Codina
Reviewed-
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles the CPM1 version of QMC and initialize the QMC used
SCC. The QUICC Engine (QE) version uses an UCC (Unified Communication
Controllers) instead of the SCC (Serial Communication Controllers) used
in the CPM1 version. These contro
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles the CPM1 version of QMC. Resources initialisations
(i.e. retrieving base addresses and offsets of different parts) will
be slightly different in the QUICC Engine (QE) version. Indeed, in QE
version, some resources need to be al
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles CPM1 version of QMC. In the QUICC Engine (QE)
version, some operations done at probe() need to be done in a different
order.
In order to prepare the support for the QE version, changed the sequence
of operation done at probe()
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles CPM1 version of QMC. Some hardcoded values are used
several times to initialize the QMC state machine. In the QUICC Engine
(QE) version of QMC, these values are different.
In order to prepare the support for the QE version of
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instea
Le 08/08/2024 à 09:11, Herve Codina a écrit :
checkpatch.pl raises the following issue
CHECK: spinlock_t definition without comment
Add the missing comments.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 inserti
Le 08/08/2024 à 09:11, Herve Codina a écrit :
checkpatch.pl raises the following issue
CHECK: 'transmiter' may be misspelled - perhaps 'transmitter'?
Indeed, fix it.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2
Le 08/08/2024 à 09:11, Herve Codina a écrit :
checkpatch.pl raises the following issue in several places
CHECK: Unnecessary parenthesis around ...
Remove them.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c | 8
1 file changed, 4 i
Le 08/08/2024 à 09:11, Herve Codina a écrit :
QMC_TSA_MASK is a bitfield. The value defined is a specific value of
this bitfield and correspond to the use of 8bit resolution for the
routing entry.
Be accurate and rename the defined constant to reflect this point.
Signed-off-by: Herve Codina
Le 08/08/2024 à 09:11, Herve Codina a écrit :
TSA consumers in CPM1 implementation don't need to know about the serial
device number used by the TSA component. In QUICC Engine implementation,
this information is needed.
Improve the TSA API with tsa_serial_get_num() in order to provide this
in
Le 08/08/2024 à 09:11, Herve Codina a écrit :
The Freescale TSA controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
di
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
The QE TSA is similar to the CPM1 TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles CPM1 version of TSA.
In order to prepare the support for the QUICC Engine (QE) version of
TSA, introduce tsa_version to identify versions. This will enable the
code to make the distinction between several TSA implementations.
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles the CPM1 version of TSA. Connecting and
disconnecting the SCC to/from the TSA consists in handling SICR register
which is CPM1 specific. The connection and disconnection operation in
the QUICC Engine (QE) version are slightly d
dma_alloc_from_pool is the allocator used when the caller can't
sleep, and as that is reusing memory it really has to call memset
or a memset-like function on the already uncached memory
unfortunately. The dma engine operation that is doing this allocation
is documented as not being able to sleep,
Le 08/08/2024 à 09:11, Herve Codina a écrit :
checkpatch.pl raises the following issues
CHECK: Please don't use multiple blank lines
CHECK: Alignment should match open parenthesis
Fix them.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/soc/fsl/qe/qmc.c
Le 08/08/2024 à 09:11, Herve Codina a écrit :
checkpatch.pl signals the following improvement for qmc.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles the CPM1 version of TSA. Setting up TSA consists in
handling SIMODE and SIGMR registers. These registers are CPM1 specific.
Setting up the QUICC Engine (QE) version of TSA is slightly different.
In order to prepare the suppor
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Current code handles the CPM1 version of TSA. Compared against QUICC
Engine (QE) version of TSA, CPM1 SIRAM entries are slightly different.
In order to prepare the support for the QE version, clearly identify
these entries and functions handling t
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Loops handling the tdm array use hardcoded size and the initialization
part uses hardcoded indexes to initialize the array.
Use ARRAY_SIZE() to avoid the hardcoded size and initialize the array
using a loop.
Signed-off-by: Herve Codina
Reviewe
Le 08/08/2024 à 09:11, Herve Codina a écrit :
SISTR, SICMR and SIRP registers offset definitions are not used.
In order to avoid unneeded code, remove them.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/soc/fsl/qe/tsa.c | 9 -
1 file changed, 9 delet
Le 08/08/2024 à 09:11, Herve Codina a écrit :
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (
Le 08/08/2024 à 09:10, Herve Codina a écrit :
checkpatch.pl raises the following issue
CHECK: spinlock_t definition without comment
Add the missing comment.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/soc/fsl/qe/tsa.c | 2 +-
1 file changed, 1 insertion
Le 08/08/2024 à 09:10, Herve Codina a écrit :
checkpatch.pl raises the following issues
CHECK: Please don't use multiple blank lines
CHECK: spaces preferred around that '/' (ctx:VxV)
CHECK: spaces preferred around that '+' (ctx:VxV)
CHECK: spaces preferred around that '-' (ctx:VxV)
Le 08/08/2024 à 09:10, Herve Codina a écrit :
checkpatch.pl signals the following improvement for tsa.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina
Reviewed-by: Christophe Leroy
---
drivers/s
Le 08/08/2024 à 09:10, Herve Codina a écrit :
The tsa_write8() parameter is an u32 value. This is not consistent with
the function itself. Indeed, tsa_write8() writes an 8bits value.
Be consistent and use an u8 parameter value.
Fixes: 1d4ba0b81c1c ("soc: fsl: cpm1: Add support for TSA")
Cc:
Le 08/08/2024 à 09:10, Herve Codina a écrit :
The TRNSYNC feature is enabled whatever the number of time-slots used.
The feature is needed only when more than one time-slot is used.
Improve the driver enabling TRNSYNC only when it is needed.
Signed-off-by: Herve Codina
Reviewed-by: Christ
Le 08/08/2024 à 09:10, Herve Codina a écrit :
The TRNSYNC feature is available (and enabled) only in transparent mode.
Since commit 7cc9bda9c163 ("soc: fsl: cpm1: qmc: Handle timeslot entries
at channel start() and stop()") TRNSYNC register is updated in
transparent and hdlc mode. In hdlc mod
On Thu, 2024-08-22 at 20:41 -0400, Dave Vasilevsky wrote:
> From d6e5fe3a45f46f1aa01914648c443291d956de9e Mon Sep 17 00:00:00 2001
> From: Dave Vasilevsky
> Date: Thu, 22 Aug 2024 20:13:46 -0400
> Subject: [PATCH] powerpc: Default to CRASH_DUMP=n when Open Firmware boot is
> likely
> MIME-Version
The non-standard "fast endian switch" syscall was added in 2008[1],
but was never widely used. It was disabled by default in 2017[2], and
there's no evidence it's ever been used since.
Remove it entirely.
A normal endian switch syscall was added in 2015[3].
[1]: 745a14cc264b ("[POWERPC] Add fast
65 matches
Mail list logo
