Add bindings documentation for TMU (Thermal Monitoring Unit) on QorIQ
platform.
Signed-off-by: Jia Hongtao
Reviewed-by: Scott Wood
---
.../devicetree/bindings/thermal/qoriq-thermal.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bi
Register the qoriq cpufreq driver as a cooling device, based on the
thermal device tree framework. When temperature crosses the passive trip
point cpufreq is used to throttle CPUs.
Signed-off-by: Jia Hongtao
Reviewed-by: Scott Wood
---
This patch depends on following patches from Scott Wood:
htt
This patchset add thermal management support to QorIQ platform including:
- T1040/T1042.
- T1023/T1024.
- LS1021A.
The thermal driver is updated to V4 based on Linux v4.4-rc2.
CPU Cooling device registration is done by another patch which will send
to both thermal and cpufreq maintainers.
The pa
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao
Reviewed-by: Scott Wood
---
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/ar
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao
Reviewed-by: Scott Wood
--
Also add nodes and properties for thermal management support. Meanwhile
preprocessor support is needed using thermal of framework.
Signed-off-by: Jia Hongtao
Reviewed-by: Scott Wood
---
arch/powerpc/boot/dts/fsl/t1040d4rdb.dts| 2 +-
arch/powerpc/boot/dts/fsl/t1040qds.dts | 2 +-
arc
On 24-11-15, 14:55, Jia Hongtao wrote:
> + /* Register CPU cooling device for QorIQ platform */
> + for_each_node_with_property(cpu_np, "#cooling-cells") {
> + of_property_read_u32(cpu_np, "reg", &cpu_id);
> + cpufreq_get_policy(&cpu_policy, cpu_id);
That's not the
ASRC need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to ASRC registers
Signed-off-by: Shengjiu Wang
---
SPDIF need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to SPDIF registers.
Signed-off-by: Shengjiu Wang
--
ESAI need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to ESAI registers.
Signed-off-by: Shengjiu Wang
---
add spba clock for fsl audio IP
Changes in V3
- update the comments for clock description.
Shengjiu Wang (3):
ASoC: fsl_esai: spba clock is needed by esai device
ASoC: fsl_spdif: spba clk is needed by spdif device
ASoC: fsl_asrc: spba clock is needed by asrc device
Documentation/devicetre
Also add nodes and properties for thermal management support. Meanwhile
preprocessor support is needed using thermal of framework.
Signed-off-by: Jia Hongtao
Reviewed-by: Scott Wood
---
arch/powerpc/boot/dts/fsl/t1023rdb.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 86 +++
On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote:
> Hi All,
>
> This patch series attempt to update book3s 64 linux page table format to
> make it more flexible. Our current pte format is very restrictive and we
> overload multiple pte bits. This is due to the non-availability of free bits
> in pte_
This adds two tests for memory page migration. One for normal page
migration which works for both 4K or 64K base page size kernel and
the other one is for 16MB huge page migration which will work both
4K or 64K base page sized 16MB huge pages as and when we support
huge page migration.
Signed-off-
On BMC machines, console output is controlled by the OPAL firmware and is
only flushed when its pollers are called. When the kernel is in a panic
state, it no longer calls these pollers and thus console output does not
completely flush, causing some output from the panic to be lost.
This patch ad
Benjamin Herrenschmidt writes:
> On Mon, 2015-11-23 at 15:52 +0530, Aneesh Kumar K.V wrote:
>> This patch series attempt to update book3s 64 linux page table format to
>> make it more flexible. Our current pte format is very restrictive and we
>> overload multiple pte bits. This is due to the non
Make the newly added TM tests skip if we don't have TM available, either
because we're running on old hardware, or the kernel doesn't have TM
support enabled.
Signed-off-by: Michael Ellerman
---
tools/testing/selftests/powerpc/tm/Makefile | 8 +---
tools/testing/selftests/powerpc
Move have_htm_nosc() into a new tm.h, and add a new helper, have_htm()
which we'll use in the next patch.
Signed-off-by: Michael Ellerman
---
tools/testing/selftests/powerpc/tm/tm-syscall.c | 12 +
tools/testing/selftests/powerpc/tm/tm.h | 34 +
2 files ch
We already do this twice and want to add another so add a helper.
Signed-off-by: Michael Ellerman
---
tools/testing/selftests/powerpc/pmu/ebb/ebb.c | 3 +--
tools/testing/selftests/powerpc/tm/tm-syscall.c | 3 +--
tools/testing/selftests/powerpc/utils.h | 6 ++
3 files changed, 8 i
This doesn't really belong in harness.c, it's a helper function. So move
it into utils.c.
Signed-off-by: Michael Ellerman
---
tools/testing/selftests/powerpc/harness.c| 43 --
tools/testing/selftests/powerpc/pmu/Makefile | 2 +
tools/testing/selftests/powerpc/pmu/ebb
On Mon, 2015-11-23 at 23:27 +0800, Ming Lei wrote:
> On Mon, Nov 23, 2015 at 11:20 PM, Laurent Dufour
> wrote:
> > >
> > > Reverting above commit on top if 4.4-rc1 seems to fix the problem for me.
> >
> > That's what I mentioned earlier ;)
> >
> > Now Ming send an additional patch with seems to
On 11/24/2015 10:06 AM, Gavin Shan wrote:
On Wed, Nov 18, 2015 at 01:23:05PM +1100, Alexey Kardashevskiy wrote:
On 11/05/2015 12:12 AM, Gavin Shan wrote:
This adds a reference count of PE, representing the number of PCI
devices associated with the PE. The reference count is increased
or decreas
On Wed, Nov 18, 2015 at 03:24:35PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>The pdn (struct pci_dn) instances are allocated from memblock or
>>bootmem when creating PCI controller (hoses) in setup_arch(). PCI
>>hotplug, which will be supported by proceeding pa
On Mon, 2015-11-23 at 15:52 +0530, Aneesh Kumar K.V wrote:
> This patch series attempt to update book3s 64 linux page table format to
> make it more flexible. Our current pte format is very restrictive and we
> overload multiple pte bits. This is due to the non-availability of free bits
> in pte_t.
On Wed, Nov 18, 2015 at 02:14:59PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>This renames traverse_pci_devices() to pci_traverse_device_nodes().
>
>Why? pci_traverse_device_nodes() is not moved to some more generic header
>where is would be required to have a s
On Mon, 2015-11-23 at 11:53 +0530, Anshuman Khandual wrote:
> On 11/19/2015 11:34 AM, Rashmica Gupta wrote:
> > Most architectures use NR_syscalls as the #define for the number of
> > syscalls.
> >
> > We use __NR_syscalls, and then define NR_syscalls as __NR_syscalls.
> >
> > __NR_syscalls is
On Wed, Nov 18, 2015 at 06:33:08PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>This adds standalone driver to support PCI hotplug for PowerPC PowerNV
>>platform that runs on top of skiboot firmware. The firmware identifies
>>hotpluggable slots and marked their de
On Wed, Nov 18, 2015 at 02:59:32PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>This renames pcibios_find_pci_bus() to pci_find_bus_by_node() to
>>avoid conflicts with those PCI subsystem weak function names, which
>>have prefix "pcibios". No logical changes intro
On Wed, Nov 18, 2015 at 01:43:06PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>This renames pcibios_{add,remove}_pci_devices() to avoid conflicts
>>with names of the weak functions in PCI subsystem, which have the
>>prefix "pcibios". No logical changes introduced
On Wed, Nov 18, 2015 at 01:23:05PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>This adds a reference count of PE, representing the number of PCI
>>devices associated with the PE. The reference count is increased
>>or decreased when PCI devices join or leave the P
On Thu, Nov 19, 2015 at 11:10:42AM +1100, Alexey Kardashevskiy wrote:
>On 11/17/2015 12:04 PM, Gavin Shan wrote:
>>On Mon, Nov 16, 2015 at 07:01:59PM +1100, Alexey Kardashevskiy wrote:
>>>On 11/05/2015 12:12 AM, Gavin Shan wrote:
As we track M32 segment consumption, this introduces an array to
> The main thing you could do, and anyone could do (!), is just review some
> patches. Even if you don't know the area of code that well, you can usually do
> a basic review.
>
> eg. Just the basic stuff:
> - Is the subject correctly formatted and makes sense.
> - Is the change log well written a
On Mon, 23 Nov 2015 10:46:20 +0800
Ming Lei wrote:
> Hi Mark,
>
> On Mon, Nov 23, 2015 at 9:50 AM, Mark Salter wrote:
> > On Mon, 2015-11-23 at 08:36 +0800, Ming Lei wrote:
> >> On Mon, Nov 23, 2015 at 7:20 AM, Mark Salter wrote:
> >> > On Sun, 2015-11-22 at 00:56 +0800, Ming Lei wrote:
> >> >
On 23/11/2015:02:57:19 PM, Laurent Dufour wrote:
> On 23/11/2015 00:20, Mark Salter wrote:
> > On Sun, 2015-11-22 at 00:56 +0800, Ming Lei wrote:
> >> On Sat, 21 Nov 2015 12:30:14 +0100
> >> Laurent Dufour wrote:
> >>
> >>> On 20/11/2015 13:10, Michael Ellerman wrote:
> On Thu, 2015-11-19 at
As preparation for eliminating the indirect access to the various
global cpu_*_bits bitmaps via the pointer variables cpu_*_mask, rename
the cpu_online_mask member of struct fadump_crash_info_header to
simply online_mask, thus allowing cpu_online_mask to become a macro.
Acked-by: Michael Ellerman
Andrew, can I get you to take these through -mm? Noone else seems to
want to pick them up. They're rebased on top of 4.4-rc2 (and applied
cleanly), but otherwise identical to what I've sent previously.
=
v2: fix build failure on ppc, add acks.
The four cpumasks cpu_{possible,online,present,a
On 23/11/2015 16:27, Ming Lei wrote:
> On Mon, Nov 23, 2015 at 11:20 PM, Laurent Dufour
> wrote:
>>>
>>> Reverting above commit on top if 4.4-rc1 seems to fix the problem for me.
>>
>> That's what I mentioned earlier ;)
>>
>> Now Ming send an additional patch with seems to fix the bug introduced
>
On Mon, Nov 23, 2015 at 11:20 PM, Laurent Dufour
wrote:
>>
>> Reverting above commit on top if 4.4-rc1 seems to fix the problem for me.
>
> That's what I mentioned earlier ;)
>
> Now Ming send an additional patch with seems to fix the bug introduced
> through the commit bdced438acd8. When testing
On 23/11/2015 16:13, Pratyush Anand wrote:
> On 23/11/2015:02:57:19 PM, Laurent Dufour wrote:
>> On 23/11/2015 00:20, Mark Salter wrote:
>>> On Sun, 2015-11-22 at 00:56 +0800, Ming Lei wrote:
On Sat, 21 Nov 2015 12:30:14 +0100
Laurent Dufour wrote:
> On 20/11/2015 13:10, Michael
Add 'P' command with optional task_struct address to dump all/one task's
information: task pointer, kernel stack pointer, PID, PPID, state
(interpreted), CPU where (last) running, and command.
Introduce XMON_PROTECT macro to standardize memory-access-fault
protection (setjm
Add 'P' command with optional task_struct address to dump all/one task's
information: task pointer, kernel stack pointer, PID, PPID, state
(interpreted), CPU where (last) running, and command.
Introduce XMON_PROTECT macro to standardize memory-access-fault
protection (setjmp). Initially used only
On 23/11/2015 00:20, Mark Salter wrote:
> On Sun, 2015-11-22 at 00:56 +0800, Ming Lei wrote:
>> On Sat, 21 Nov 2015 12:30:14 +0100
>> Laurent Dufour wrote:
>>
>>> On 20/11/2015 13:10, Michael Ellerman wrote:
On Thu, 2015-11-19 at 00:23 -0800, Christoph Hellwig wrote:
> It's pretty mu
Andy Shevchenko writes:
> On Sun, 2015-11-22 at 13:03 +, Måns Rullgård wrote:
>> Andy Shevchenko writes:
>>
>> > The SATA implementation based on two actually different devices,
>> > i.e. SATA and
>> > DMA controllers.
>> >
>> > For Synopsys DesignWare DMA we have already a generic
>> > im
On 11/20/2015 09:45 AM, Michael Neuling wrote:
> Test the kernels signal generation code to ensure it can handle an
> invalid stack pointer when transactional.
>
> Signed-off-by: Michael Neuling
Tested-by: Anshuman Khandual
___
Linuxppc-dev mailing l
On 11/20/2015 09:45 AM, Michael Neuling wrote:
> Test the kernel's signal return code to ensure that it doesn't crash
> when both the transactional and suspend MSR bits are set in the signal
> context.
>
> Signed-off-by: Michael Neuling
Tested-by: Anshuman Khandual
If we have _PAGE_COMBO set, we override the _PAGE_F_GIX_SHIFT
and _PAGE_F_SECOND. Together we have 4 bits, each of them
used to indicate whether any of the 4 4k subpage in that group
is valid. ie,
[ group 1 bit ] [ group 2 bit ] . [ group 4 ]
[ subpage 1 - 4] [ subpage 5- 8] . [ subpa
Now that we don't track 4k subpage slot details, get rid of real_pte
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h| 15 +++
arch/powerpc/include/asm/book3s/64/pgtable.h | 33 ++--
arch/powerpc/include/asm/nohash/64/pgtable-6
Now that we don't really use real_pte_t drop them from iterator argument
list. The follow up patch will remove real_pte_t completely
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 5 +++--
arch/powerpc/include/asm/book3s/64/pgtable.h | 7 +++
arch/powe
Now that we don't track 4k subpage information we can use 2K PTE
fragments.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h
b/arch/powerpc/in
We search the hash table to find the slot information. This slows down
the lookup, but we do that only for 4k subpage config
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 33 ++
arch/powerpc/include/asm/book3s/64/pgtable.h | 11 +-
arch/
This will bulk read 4 hash pte slot entries and should reduce the loop
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/plpar_wrappers.h | 17 ++
arch/powerpc/platforms/pseries/lpar.c | 54 +++
2 files changed, 44 insertions(+), 27 deletions(-)
Remove the related functions and #defines
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/64/pgtable.h | 33
1 file changed, 33 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h
b/arch/powerpc/include/asm/nohash/64/pgtable.h
They don't need to track 4k subpage slot details and hence don't need
second half of pgtable_t.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/64/pgtable-64k.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/64/pgtabl
Use the #define instead of open-coding the same
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
arch/powerpc/include/asm/book3s/64/pgtable.h | 2 +-
arch/powerpc/include/asm/nohash/64/pgtable.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
pte and pmd table size are dependent on config items. Don't
hard code the same. This make sure we use the right value
when masking pmd entries and also while checking pmd_bad
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h| 30 ++--
arch/
Hi,
This patch series update 4k subpage tracking in pte page, thereby reducing
the ptefragment size. This results in us allocating less number of
pgtable_t for an application. One of the side effect is that we now make
and hcall to find out whether a 4k subpage is present in the hash page table or
For a pte entry we will have _PAGE_PTE set. Our pte page
address have a minimum alignment requirement of HUGEPD_SHIFT_MASK + 1.
We use the lower 7 bits to indicate hugepd. ie.
For pmd and pgd we can find:
1) _PAGE_PTE set pte -> indicate PTE
2) bits [2..6] non zero -> indicate hugepd.
They also
We support THP only with book3s_64 and 64K page size. Move
THP details to hash64-64k.h to clarify the same.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 126 +
arch/powerpc/include/asm/book3s/64/hash.h | 223 +--
W.r.t hugetlb, we support two format for pmd. With book3s_64 and
64K linux page size, we can have pte at the pmd level. Hence we
don't need to support hugepd there. For everything else hugepd
is supported and pmd_huge is (0).
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc
Only difference here is, we apply the WIMG mapping early, so rflags
passed to updatepp will also be changed.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash64_4k.c | 5 -
arch/powerpc/mm/hash64_64k.c | 10 --
arch/powerpc/mm/hash_utils
Instead of open coding it in multiple code paths, export the helper
and add more documentation. Also make sure we don't make assumption
regarding pte bit position
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 1 +
arch/powerpc/mm/hash64_4k
We should not expect pte bit position in asm code. Simply
by moving part of that to C
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/exceptions-64s.S | 16 +++-
arch/powerpc/mm/hash_utils_64.c | 29 +
2 files changed, 32
This is similar to 64K insert. May be we want to consolidate
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/Makefile| 6 +-
arch/powerpc/mm/hash64_4k.c | 139 +
arch/powerpc/mm/hash_low_64.S | 331
Convert from asm to C
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 3 +-
arch/powerpc/include/asm/book3s/64/hash.h | 1 +
arch/powerpc/mm/hash64_64k.c | 134 +++-
arch/powerpc/mm/hash_low_64.S
No real change, only style changes
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h
b/arch/powerpc/includ
This free up 11 bits in pte_t. In the later patch we also change
the pte_t format so that we can start supporting migration pte
at pmd level.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 10 +
arch/powerpc/include/asm/book3s/64
Currently we use 4 bits for each slot and pack all the 16 slot
information related to a 64K linux page in a 64bit value. To do this
we use 16 bits of pte_t. Move the hash slot valid bit out of pte_t
and place them in the second half of pte page. We also use 8 bit
per each slot.
Acked-by: Scott Woo
We will use this in the later patch to compute the right hash index
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
arch/powerpc/include/asm/book3s/64/pgtable.h | 4 ++--
arch/powerpc/include/asm/nohash/64/pgtable.h | 4 ++--
arch
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/Makefile| 3 +
arch/powerpc/mm/hash64_64k.c| 202 +
arch/powerpc/mm/hash_low_64.S | 380
arch/powerpc/mm/hash_utils_64.c | 4 +-
4 files changed
We will use the increased size to store more information of 4K pte
when using 64K page size. The idea is to free up bits in pte_t.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgalloc-64.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
d
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/32/pte-40x.h | 6 +++---
arch/powerpc/include/asm/nohash/32/pte-44x.h | 6 +++---
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 6 +++---
arch/powerpc/include/asm/nohash/32/pte-fsl-booke.h
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 16
arch/powerpc/include/asm/{ => nohash/32}/pte-40x.h | 0
arch/powerpc/include/asm/{ => nohash/32}/pte-44x.h | 0
arch/powerpc/include/asm/{ => noh
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/{pgtable-ppc32.h => nohash/32/pgtable.h} | 0
arch/powerpc/include/asm/{pgtable-ppc64.h => nohash/64/pgtable.h} | 2 +-
arch/powerpc/include/asm/nohash/pgtable.h | 8
3 files change
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
.../include/asm/{pgtable-ppc64-4k.h => nohash/64/pgtable-4k.h} | 0
.../asm/{pgtable-ppc64-64k.h => nohash/64/pgtable-64k.h} | 0
arch/powerpc/include/asm/nohash/64/pgtable.h | 10 +-
3 files changed, 5 in
Move the booke related headers below booke/32 or booke/64
We are splitting this change into multiple patch to make the rebasing
easier. The following patches can be folded into this if needed.
They are kept separate for easier review.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
ar
This enables us to keep hash64 related bits together, and makes it easy
to follow.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 450 ++-
arch/powerpc/include/asm/book3s/64/pgtable.h | 447 +---
functions which operate on pte bits are moved to hash*.h and other
generic functions are moved to pgtable.h
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 183
arch/powerpc/include/asm/book3s/64/hash.h| 151 ++
We convert them static inline function here as we did with pte_val in
the previous patch
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 6 -
arch/powerpc/include/asm/book3s/64/hash-4k.h | 6 -
arch/powerpc/include/asm/book3s/64/
We also convert few #define to static inline in this patch for better
type checking
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/pgtable.h | 118 +-
arch/powerpc/include/asm/page.h | 10 ++-
arch/powerpc/include/
We copy only needed PTE bits define from pte-common.h to respective
hash related header. This should greatly simply later patches in which
we are going to change the pte format for hash config
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h
We are going to drop pte_common.h in the later patch. The idea is to
enable hash code not require to define all PTE bits. Having PTE bits
defined in pte_common.h made the code unnecessarily complex.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/pgtable
We also move __ASSEMBLY__ towards the end of header. This avoid
having #ifndef __ASSEMBLY___ all over the header
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 93 +++-
arch/powerpc/include/asm/book3s/64/pgtable.h
This further make a copy of pte defines to book3s/64/hash*.h. This
remove the dependency on ppc64-4k.h and ppc64-64k.h
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 87 ++-
arch/powerpc/include/asm/book3s/64/hash
Keep it seperate to make rebasing easier
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 4 ++--
arch/powerpc/include/asm/book3s/64/pgtable.h | 6 +++---
arch/powerpc/include/asm/pgtable-ppc32.h | 2 --
arch/powerpc/include/asm/pgtable
In this patch we do:
cp pgtable-ppc32.h book3s/32/pgtable.h
cp pgtable-ppc64.h book3s/64/pgtable.h
This enable us to do further changes to hash specific config.
We will change the page table format for 64bit hash in later patches.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/p
Splitting this so that rename can track changes to file. Before merging
we will fold this
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/hash.h | 6 +++---
.../include/asm/{pte-hash64-4k.h => book3s/64/hash-4k.h} | 1 -
.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/{pte-hash32.h => book3s/32/hash.h} | 0
arch/powerpc/include/asm/{pte-hash64.h => book3s/64/hash.h} | 0
arch/powerpc/include/asm/pgtable-ppc32.h| 2 +-
arch/powerpc/include/asm/pgtable-ppc64.h
Hi All,
This patch series attempt to update book3s 64 linux page table format to
make it more flexible. Our current pte format is very restrictive and we
overload multiple pte bits. This is due to the non-availability of free bits
in pte_t. We use pte_t to track the validity of 4K subpages. This p
On Mon, 2015-11-23 at 13:54 +0530, Anshuman Khandual wrote:
> On 11/21/2015 11:38 AM, Rashmica Gupta wrote:
> > It is common practice with powerpc to use 'rN' to refer to register 'N'.
> > However
> > when using the pt_regs_offset table we have to use 'gprN'.
> >
> > So add aliases such that bo
On Mon, 2015-11-23 at 12:28 +0300, Denis Kirjanov wrote:
> On 11/23/15, Michael Ellerman wrote:
> > On Thu, 2015-11-19 at 12:15 +0300, Denis Kirjanov wrote:
> > > On 11/19/15, Rashmica Gupta wrote:
> > > > Most architectures use NR_syscalls as the #define for the number of
> > > > syscalls.
> > >
On Mon, 2015-11-23 at 12:45 +0300, Denis Kirjanov wrote:
> On 11/23/15, Michael Ellerman wrote:
> > Hi Denis,
> >
> > On Fri, 2015-11-20 at 17:48 +0300, Denis Kirjanov wrote:
> > > Hi guys,
> > >
> > > As we all know we have a great tool to track the patch queue - patchwork.
> > > The sad thing
On Sun, 2015-11-22 at 13:03 +, Måns Rullgård wrote:
> Andy Shevchenko writes:
>
> > The SATA implementation based on two actually different devices,
> > i.e. SATA and
> > DMA controllers.
> >
> > For Synopsys DesignWare DMA we have already a generic
> > implementation of the
> > driver. Thus
On 11/23/15, Michael Ellerman wrote:
> Hi Denis,
>
> On Fri, 2015-11-20 at 17:48 +0300, Denis Kirjanov wrote:
>> Hi guys,
>>
>> As we all know we have a great tool to track the patch queue - patchwork.
>> The sad thing is that it's maintained not good as it could be. The
>> netdev patchwork is a g
On 11/23/15, Michael Ellerman wrote:
> On Fri, 2015-11-20 at 15:22 +0300, Denis Kirjanov wrote:
>> On 11/3/15, Denis Kirjanov wrote:
>> > On 11/3/15, Michael Ellerman wrote:
>> > > On Thu, 2015-10-29 at 22:10 +0300, Denis Kirjanov wrote:
>> > > > ./drmgr -c cpu -a -r gives the following warning:
On 11/23/15, Michael Ellerman wrote:
> On Thu, 2015-11-19 at 12:15 +0300, Denis Kirjanov wrote:
>
>> On 11/19/15, Rashmica Gupta wrote:
>
>> > Most architectures use NR_syscalls as the #define for the number of
>> > syscalls.
>> >
>> > We use __NR_syscalls, and then define NR_syscalls as __NR_sys
On 11/20/2015 09:11 PM, Jacek Anaszewski wrote:
> Since brightness setting can sleep for this driver, implement
> brightness_set_blocking op, instead of brightness_set.
> It makes this driver compatible with LED triggers.
Hello Jacek,
Thanks for the patch. Looks good.. I will test this patch lat
On 11/21/2015 11:38 AM, Rashmica Gupta wrote:
> It is common practice with powerpc to use 'rN' to refer to register 'N'.
> However
> when using the pt_regs_offset table we have to use 'gprN'.
>
> So add aliases such that both 'rN' and 'gprN' can be used.
>
> For example, we can currently do:
> $
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