> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 17, 2013 2:49 AM
> To: Kushwaha Prabhakar-B32579
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org; Aggrwal Poonam-B10812; Jain Priyanka-B32167;
> Sethi Varun-B16395
> Subject: Re:
I see, thanks. ^_^
于 2013/9/17 3:42, Scott Wood 写道:
On Mon, 2013-09-16 at 16:12 +0800, Zhang Haijun wrote:
On 09/02/2013 06:37 PM, Haijun Zhang wrote:
We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD
On Mon, 2013-09-16 at 07:38 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2013-09-13 at 22:50 -0500, Scott Wood wrote:
> > The ISA says that a sync is needed to order a PTE write with a
> > subsequent hardware tablewalk lookup. On e6500, without this sync
> > we've been observed to die with a DSI
On Thu, 2013-09-12 at 18:07 +0800, Minghuan Lian wrote:
> The Freescale's Layerscape series processors will use the same PCI
> controller but change cores from PowerPC to ARM. This patch is to
> rework FSL PCI driver to support PowerPC and ARM simultaneously.
> PowerPC uses structure pci_controller
On 09/16/2013 04:38 PM, York Sun wrote:
> T4240EMU is an emulator target with minimum peripherals. It is based on
> T4240QDS and trimmed down most peripherals due to either not modeled or
> lack of board level connections. The main purpose of this minimum dts is
> to speed up booting on emulator.
>
On 09/16/2013 04:35 PM, York Sun wrote:
> Enable CONFIG_MTD_M25P80 for corenet64_smp_defconfig. Verified on
> P5040DS.
>
> Signed-off-by: York Sun
> ---
> Change log:
> v2: remote reviewed-by and tested-by lines added by gerrit
>
Pardon my typo. I meant to type "remove", instead of "remote".
B4860EMU is a emualtor target with minimum peripherals. It is based on
B4860QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun
---
Change log:
v2: rem
T4240EMU is an emulator target with minimum peripherals. It is based on
T4240QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun
---
Change log:
v2: re
Enable CONFIG_MTD_M25P80 for corenet64_smp_defconfig. Verified on
P5040DS.
Signed-off-by: York Sun
---
Change log:
v2: remote reviewed-by and tested-by lines added by gerrit
arch/powerpc/configs/corenet64_smp_defconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs
On Mon, Sep 16, 2013 at 11:10:27AM -0500, Kumar Gala wrote:
>
> On Sep 12, 2013, at 8:11 PM, Kevin Hao wrote:
>
> > On Thu, Sep 12, 2013 at 01:44:46PM -0500, Scott Wood wrote:
> >> On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote:
>
> Just a nit, but subject is missing 'e' in 'cornet' :)
Will
On Thu, 2013-09-12 at 18:15 +0100, Mark Rutland wrote:
> On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote:
> > On 09/02/2013 11:58 PM, Mark Rutland wrote:
> > > May some channels be unusable for some reason, or will all eight
> > > channels be wired on any given Elo3 DMA?
> > Sorry, not
On Fri, 2013-09-13 at 03:17 +, Zhao Qiang-B45475 wrote:
> On Sep 13, 2013, at 12:42 AM, Kumar Gala wrote:
>
> > -Original Message-
> > From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> > Sent: Friday, September 13, 2013 12:42 AM
> > To: Liu Shengzhou-B36685
> > Cc: Zhao Qiang-B4547
On Sun, 2013-09-15 at 19:31 +0530, Prabhakar Kushwaha wrote:
> The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
> processor cores with high-performance data path acceleration architecture
> and network peripheral interfaces required for networking &
> telecommunications.
>
On Thu, 2013-09-12 at 21:50 -0500, Tang Yuantian-B29983 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: 2013年9月12日 星期四 22:44
> > To: Tang Yuantian-B29983
> > Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc-
> > d...@lists.ozlabs.org; devicet...@vger.kernel.org
On Fri, 2013-09-13 at 02:30 -0500, Kushwaha Prabhakar-B32579 wrote:
> > I also question the need to define separate t1040 compatible values for
> > all of these, if the only difference is whether the onboard switch is
> > enabled or not.
> >
>
> so should I use T104x as compatible field. and in T
On Thu, 2013-09-12 at 21:53 -0500, Wang Dongsheng-B40534 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Friday, September 13, 2013 2:07 AM
> > To: Wang Dongsheng-B40534
> > Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc-
> > d...@lists.ozlabs.org
> > Subj
On Fri, 2013-09-13 at 07:04 +0200, leroy christophe wrote:
> Le 12/09/2013 20:44, Scott Wood a écrit :
> > On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
> >> This is a reorganisation of the setup of the TLB at kernel startup, in
> >> order
> >> to handle the CONFIG_PIN_TLB case in acc
On Fri, 2013-09-13 at 02:35 -0500, Kushwaha Prabhakar-B32579 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Thursday, September 12, 2013 5:11 AM
> > To: Kushwaha Prabhakar-B32579
> > Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Jain
> > Priyanka-B321
On Mon, 2013-09-16 at 16:12 +0800, Zhang Haijun wrote:
> On 09/02/2013 06:37 PM, Haijun Zhang wrote:
> > We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
> > to distinguish if the sdhc host has quirk
> > SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
> >
> > Signed-off-by: Haijun Zhang
>
On Sep 12, 2013, at 8:11 PM, Kevin Hao wrote:
> On Thu, Sep 12, 2013 at 01:44:46PM -0500, Scott Wood wrote:
>> On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote:
Just a nit, but subject is missing 'e' in 'cornet' :)
- k
___
Linuxppc-dev mailing lis
From: Mahesh Salgaonkar
Now that we are ready to handle machine check directly in linux, do not
register with firmware to handle machine check exception.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/platforms/powernv/opal.c |8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
From: Mahesh Salgaonkar
Add basic error handling in machine check exception handler.
- If MSR_RI isn't set, we can not recover.
- Check if disposition set to OpalMCE_DISPOSITION_RECOVERED.
- Check if address at fault is inside kernel address space, if not then send
SIGBUS to process if we hit
From: Mahesh Salgaonkar
When machine check real mode handler can not continue into host kernel
in V mode, it returns from the interrupt and we loose MCE event which
never gets logged. In such a situation queue up the MCE event so that
we can log it later when we get back into host kernel with r1
From: Mahesh Salgaonkar
Now that we handle machine check in linux, the MCE decoding should also
take place in linux host. This info is crucial to log before we go down
in case we can not handle the machine check errors. This patch decodes
and populates a machine check event which contain high lev
From: Mahesh Salgaonkar
This patch handles the memory errors on power8. If we get a machine check
exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to
recover.
Signed-off-by: Mahesh Salgaonkar
Acked-by: Paul Mackerras
---
arch/powerpc/include/asm/mce.h |3 +++
arch
From: Mahesh Salgaonkar
If we get a machine check exception due to SLB or TLB errors, then flush
SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning
on MMU. Otherwise we would run into nested machine checks.
If we get a machine check when we are in guest, then just flush
From: Mahesh Salgaonkar
This patch introduces flush_tlb operation in cpu_spec structure. This will
help us to invoke appropriate CPU-side flush tlb routine. This patch
adds the foundation to invoke CPU specific flush routine for respective
architectures. Currently this patch introduce flush_tlb f
From: Mahesh Salgaonkar
This patch adds the early machine check function pointer in cputable for
CPU specific early machine check handling. The early machine handle routine
will be called in real mode to handle SLB and TLB errors. We can not reuse
the existing machine_check hook because it is alw
From: Mahesh Salgaonkar
We can get machine checks from any context. We need to make sure that
we handle all of them correctly. If we are coming from hypervisor user-space,
we can continue in host kernel in virtual mode to deliver the MC event.
If we got woken up from power-saving mode then we may
From: Mahesh Salgaonkar
This patch introduces exclusive emergency stack for machine check exception.
We use emergency stack to handle machine check exception so that we can save
MCE information (srr1, srr0, dar and dsisr) before turning on ME bit and be
ready for re-entrancy. This helps us to pre
From: Mahesh Salgaonkar
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check routine that saves the MCE
information (srr1, srr0, dar and dsisr) to the emergenc
Hi,
Please find the patch set that performs the machine check handling inside linux
host. The design is to be able to handle re-entrancy so that we do not clobber
the machine check information during nested machine check interrupt.
The patch 2 introduces separate emergency stack in paca structure
From: Mahesh Salgaonkar
This patch splits the common exception prolog logic into three parts to
facilitate reuse of existing code in the next patch. This patch also
re-arranges few instructions in such a way that the second part now deals
with saving register values from paca save area to stack f
On 9/13/2013 7:49 PM, Sukadev Bhattiprolu wrote:
Implement is_instr_load_store() to detect whether a given instruction
is one of the fixed-point or floating-point load/store instructions.
This function will be used in a follow-on patch to save memory hierarchy
information of the load/store.
+/*
On 09/13/2013 04:53 PM, Kumar Gala wrote:
> On Sep 13, 2013, at 4:14 AM, Valentin Longchamp wrote:
>> On 09/11/2013 08:58 AM, Prabhakar Kushwaha wrote:
>>> +
>>> +&pci0 {
>>> + compatible = "fsl,t1042-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
>>> + device_type = "pci";
>>> + #size-cells
On Mon, Sep 09, 2013 at 05:20:44PM +0200, Alexander Gordeev wrote:
> On Fri, Sep 06, 2013 at 05:32:05PM -0600, Bjorn Helgaas wrote:
> > I propose that you rework it that way, and at least find out what
> > (if anything) would break if we do that. Or maybe we just give up
> > some optimization; it
On 09/13/2013 01:15 AM, Mark Rutland wrote:
On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote:
On 09/02/2013 11:58 PM, Mark Rutland wrote:
Hi,
On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-
On 09/02/2013 06:37 PM, Haijun Zhang wrote:
We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
Signed-off-by: Haijun Zhang
---
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
1 file changed,
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