On Wed, Sep 05, 2012 at 07:23:43PM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2012-09-05 at 10:02 +0200, Uwe Kleine-König wrote:
> > Hello,
> >
> > On Wed, Sep 05, 2012 at 12:40:17PM +1000, Benjamin Herrenschmidt wrote:
> > > On Mon, 2012-07-23 at 11:13 +0200, Uwe Kleine-König wrote:
> > > > T
On Mon, 2012-09-10 at 14:22 +, Arnd Bergmann wrote:
> Following up on the old discussion, I talked briefly about this
> issue with BenH at the kernel summit. The outcome basically is that
> it's a bit sad to have incompatible bindings, but it's not the end
> of the world,and it's more important
On Mon, 2012-09-10 at 22:42 -0700, Haren Myneni wrote:
>
> Thanks Michael. Yes, we noticed 6% overhead with null syscall test.
> Hence added cmdline option as suggested. I will add this comment in
> the
> changelog.
>
> Regarding the option name, I thought about various ones such as
> retain_proc
On Tue, 2012-09-11 at 10:20 +0800, Tiejun Chen wrote:
> We can't emulate stwu since that may corrupt current exception stack.
> So we will have to do real store operation in the exception return code.
>
> Firstly we'll allocate a trampoline exception frame below the kprobed
> function stack and co
On 09/09/2012 05:22 PM, Michael Neuling wrote:
> Benjamin Herrenschmidt wrote:
>
>> On Sun, 2012-09-09 at 04:37 -0700, Haren Myneni wrote:
>>> enable_ppr kernel parameter is used to enable PPR save and restore.
>>> Supported on Power7 and later processors.
>>>
>>> By default, CPU_FTR_HAS_PPR is s
On Mon, 2012-09-10 at 22:18 -0700, Haren Myneni wrote:
> We can also use thread struct, but the saved ppr is needed as long as
> the process is in kernel context. Once the process exits, we do not need
> this value - means the kernel or any other command will not be reading
> this value.
>
> Even
At 09/11/2012 01:18 PM, Jerry Wrote:
> Hi Kim,
>
> Thank you for your kindness. Let me clarify this:
>
> On ARM architecture, there are 32 bits physical addresses space. However,
> the addresses space is divided into 8 banks normally. Each bank
> disabled/enabled by a chip selector signal. In my
Hi Kim,
Thank you for your kindness. Let me clarify this:
On ARM architecture, there are 32 bits physical addresses space. However,
the addresses space is divided into 8 banks normally. Each bank
disabled/enabled by a chip selector signal. In my platform, bank0 connects
a DDR chip, and bank1 also
On 09/09/2012 05:05 PM, Benjamin Herrenschmidt wrote:
> On Sun, 2012-09-09 at 04:36 -0700, Haren Myneni wrote:
>> The first instruction in ACCOUNT_CPU_USER_ENTRY is 'beq' which checkes for
>> exceptions coming from kernel mode. PPR value will be saved immediately after
>> ACCOUNT_CPU_USER_ENTRY and
On 09/09/2012 09:24 PM, Benjamin Herrenschmidt wrote:
> On Sun, 2012-09-09 at 04:43 -0700, Haren Myneni wrote:
>> Several macros are defined for saving and restore user defined PPR value.
>>
>> Signed-off-by: Haren Myneni
>> ---
>> arch/powerpc/include/asm/exception-64s.h | 35
>> +
Hi Kumar,
Do you or Ben has any comment on this?
Please let me know.
Thanks.
From: Jia Hongtao-B38951
Sent: Friday, August 31, 2012 10:25 AM
To: Kumar Gala
Cc: linuxppc-dev@lists.ozlabs.org; Li Yang-R58472; Wood Scott-B07421
Subject: RE: [PATCH V10] power
The freescale V2 SATA controller checks if the received data length matches
the programmed length 'ttl', if not, it assumes that this is an error.
In ATAPI, the 'ttl' is based on max allocation length and not the actual
data transfer length, controller will raise 'DLM' (Data length Mismatch)
error
Hi, ishimatsu
At 09/05/2012 05:25 PM, we...@cn.fujitsu.com Wrote:
> From: Yasuaki Ishimatsu
>
> If system supports memory hot-remove, online_pages() may online removed pages.
> So online_pages() need to check whether onlining pages are present or not.
Because we use memory_block_change_state()
At 09/11/2012 10:24 AM, Yasuaki Ishimatsu Wrote:
> Hi Wen,
>
> 2012/09/11 11:15, Wen Congyang wrote:
>> Hi, ishimatsu
>>
>> At 09/05/2012 05:25 PM, we...@cn.fujitsu.com Wrote:
>>> From: Yasuaki Ishimatsu
>>>
>>> If system supports memory hot-remove, online_pages() may online
>>> removed pages.
>>
Hi Wen,
2012/09/11 11:15, Wen Congyang wrote:
Hi, ishimatsu
At 09/05/2012 05:25 PM, we...@cn.fujitsu.com Wrote:
From: Yasuaki Ishimatsu
If system supports memory hot-remove, online_pages() may online removed pages.
So online_pages() need to check whether onlining pages are present or not.
We don't do the real store operation for kprobing 'stwu Rx,(y)R1'
since this may corrupt the exception frame, now we will do this
operation safely in exception return code after migrate current
exception frame below the kprobed function stack.
So we only update gpr[1] here and trigger a thread fla
We need to add a new thread flag, TIF_EMULATE_STACK_STORE,
for emulating stack store operation while exiting exception.
Signed-off-by: Tiejun Chen
---
v3:
* rebase on next
* restore those clobbered registers
* add for 64-bit
* retest with kprobe do_fork()/show_interrupts()
for fsl-p4080 a
We can't emulate stwu since that may corrupt current exception stack.
So we will have to do real store operation in the exception return code.
Firstly we'll allocate a trampoline exception frame below the kprobed
function stack and copy the current exception frame to the trampoline.
Then we can do
Hi Jerry,
On Tue, Sep 11, 2012 at 08:27:40AM +0800, Jerry wrote:
> Hi Wen,
>
> I have been arranged a job related memory hotplug on ARM architecture.
> Maybe I know some new issues about memory hotplug on ARM architecture. I
> just enabled it on ARM, and it works well in my Android tablet now.
>
Hi Wen,
I have been arranged a job related memory hotplug on ARM architecture.
Maybe I know some new issues about memory hotplug on ARM architecture. I
just enabled it on ARM, and it works well in my Android tablet now.
However, I have not send out my patches. The real reason is that I don't
know
Thank you all, this is the updated patch for your review:
There are a few tracepoints in the interrupt code path, which is before
irq_enter(), or after irq_exit(), like
trace_irq_entry()/trace_irq_exit() in do_IRQ(),
trace_timer_interrupt_entry()/trace_timer_interrupt_exit() in
timer_interrupt().
x27; has
no member named 'pcie_type'
Caused by commit ac161fbfdaa2 ("powerpc/powernv: I/O and memory alignment
for P2P bridges"). pcie_type was removed in commit b2ef39be5744 ("PCI:
Remove unused field pcie_type from struct pci_dev") (also in the pci
tree).
I have use
Hi Ben,
> > Or could we just move these tracepoints inside the
> > irq_enter()/irq_exit() area? (Seems not good for the timer_interrupt
> > case).
>
> I'd say just move them in. Anton, any objection ?
Sounds reasonable, no objections from me.
Anton
_
At 09/11/2012 08:27 AM, Jerry Wrote:
> Hi Wen,
>
> I have been arranged a job related memory hotplug on ARM architecture.
> Maybe I know some new issues about memory hotplug on ARM architecture. I
> just enabled it on ARM, and it works well in my Android tablet now.
> However, I have not send out
On 09/07/2012 06:50 PM, Benjamin Herrenschmidt wrote:
> #endif /* CONFIG_PPC64 */
> @@ -377,7 +382,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb,
> unsigned long address)
> {
> int tsize = mmu_psize_defs[mmu_pte_psize].enc;
>
> - if (book3e_htw_enabled) {
>>>
On Mon, 2012-09-10 at 08:50 +, Bhushan Bharat-R65777 wrote:
> When I sent the patch I did not search the users, I agree that we can
> remove the __get_user64 and __put_user64 altogether.
Care to send a patch ?
Cheers,
Ben.
___
Linuxppc-dev mailing
On Mon, 2012-09-10 at 10:02 -0400, Steven Rostedt wrote:
> I agree too. I'm a bit concerned about the lack of coverage the
> irq_enter() and irq_exit() have in the timer interrupt:
>
> may_hard_irq_enable();
>
> trace_timer_interrupt_entry(regs);
>
> __get_cpu_var(irq_stat).tim
On Wed, 2012-09-05 at 15:27 +1000, Alexey Kardashevskiy wrote:
> On 05/09/12 15:17, Benjamin Herrenschmidt wrote:
> > On Tue, 2012-09-04 at 22:57 -0600, Alex Williamson wrote:
> >
> >> Do we need an extra region info field, or is it sufficient that we
> >> define a region to be mmap'able with getpa
On Thu, Sep 06, 2012 at 05:27:42PM +0300, Felipe Balbi wrote:
> Hi,
>
> On Thu, Sep 06, 2012 at 04:27:12PM +0200, Enrico Scholz wrote:
> > Felipe Balbi writes:
> >
> > >> > Because the fsl_udc_core driver shares one 'status_req' object for the
> > >> > complete ep0 control transfer, it is not po
On Tue, 2012-09-04 at 17:33 +1000, Alexey Kardashevskiy wrote:
> Cc: David Gibson
> Cc: Benjamin Herrenschmidt
> Cc: Paul Mackerras
> Signed-off-by: Alexey Kardashevskiy
> ---
Please at least cc kvm@vger as well since we list that as the devel list
for vfio.
> arch/powerpc/include/asm/iommu.
On Thursday 16 August 2012, Ian Molton wrote:
> Ping :)
>
> Can we get some consensus on the right approach here? I'm loathe to code
> this if its going to be rejected.
>
> I'd prefer the driver to be properly split so we dont have the MDIO
> driver mapping the ethernet drivers address spaces, bu
On Mon, 2012-09-10 at 15:10 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2012-09-10 at 12:58 +0800, Li Zhong wrote:
> > There are a few tracepoints in the interrupt code path, which is before
> > irq_enter(), or after irq_exit(), like
> > trace_irq_entry()/trace_irq_exit() in do_IRQ(),
> > trace_
Hi,
On Mon, Sep 10, 2012 at 10:01:44AM +0800, Wen Congyang wrote:
> At 09/10/2012 09:46 AM, Yasuaki Ishimatsu Wrote:
> > Hi Wen,
> >
> > 2012/09/01 5:49, Andrew Morton wrote:
> >> On Tue, 28 Aug 2012 18:00:07 +0800
> >> we...@cn.fujitsu.com wrote:
> >>
> >>> This patch series aims to support phys
From: "Aneesh Kumar K.V"
To clarify the meaning for future readers, replace the open coded
19 with CONTEXT_BITS
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/mmu_context_hash64.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powe
From: "Aneesh Kumar K.V"
slice array size and slice mask size depend on PGTABLE_RANGE.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h| 15 ++-
arch/powerpc/include/asm/mmu.h |9 +
arch/powerpc/inclu
From: "Aneesh Kumar K.V"
This update the proto-VSID and VSID scramble related information
to be more generic by using names instead of current values.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 40 ++---
From: "Aneesh Kumar K.V"
This patch simplify hpte_decode for easy switching of virtual address to
virtual page number in the later patch
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 49 ++
1 file chang
From: "Aneesh Kumar K.V"
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/paca.h |2 +-
arch/powerpc/mm/slb_low.S |8
2 files changed, 5 insertio
From: "Aneesh Kumar K.V"
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h| 42 --
arch/powerpc/include/asm/pgtable-ppc64-4k.h
From: "Aneesh Kumar K.V"
As we keep increasing PGTABLE_RANGE we need not increase the virual
map area for kernel.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arc
Hi,
This patchset include patches for supporting 64TB with ppc64. I haven't booted
this on hardware with 64TB memory yet. But they boot fine on real hardware with
less memory. Changes extend VSID bits to 38 bits for a 256MB segment
and 26 bits for 1TB segments.
Changes from V8:
* Address review
From: "Aneesh Kumar K.V"
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |6 +-
arch/powerpc/include/asm
From: "Aneesh Kumar K.V"
ASM_VSID_SCRAMBLE can leave non-zero bits in the high 28 bits of the result
for 256MB segment (40 bits for 1T segment). Properly mask them before using
the values in slbmte
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb_low.S | 1
From: "Aneesh Kumar K.V"
Don't open code the same
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/cell/beat_htab.c
b/arch/powerpc/platforms/ce
> * a value of 1 for all rates below 2400 (On 8250, fifo is set to 1
> for such rates)
> * a value of 2 for 2400 and 4800
> * a value of 4 for 9600 (which is the default on the 8250 for all
> rates above 2400)
> * a value of 8 for 19200
> * a value of 16 for 38400 and above (on UCC_UART, maxidl is
Hi Mikey,
On Fri, 7 Sep 2012, Michael Neuling wrote:
> Geert Uytterhoeven wrote:
> > On Fri, 7 Sep 2012, Michael Neuling wrote:
> > > Do you know if the ps3 hypervisor will allow us to set DABRX_BTI or
> > > DABRX_HYP? phyp wont.
> >
> > According to the documenation, all bits but DABRX_
> -Original Message-
> From: Sergei Shtylyov [mailto:sshtyl...@mvista.com]
> Sent: Monday, September 10, 2012 6:22 PM
> To: Xie Shaohui-B21989
> Cc: Kumar Gala; jgar...@pobox.com; linux-...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Bhartiya Anju-B0726
On POWER6 and POWER7 if the input operand to an instruction is a
denormalised single precision binary floating point value we can take
a denormalisation exception where it's expected that the hypervisor
(HV=1) will fix up the inputs before the instruction is run.
This adds code to handle this deno
Michael Ellerman wrote:
> On Mon, 2012-09-10 at 16:54 +1000, Michael Neuling wrote:
> > On POWER6 and POWER7 if the input operand to an instruction is a
> > denormalised single precision binary floating we can take a
>^
>
Hello.
On 10-09-2012 6:53, Xie Shaohui-B21989 wrote:
+ /* Workaround for data length mismatch errata */
+ if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
+ for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
+ qc = ata_qc_from_tag(ap, tag);
+
> -Original Message-
> From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
> Sent: Monday, September 10, 2012 7:38 AM
> To: Kumar Gala
> Cc: Xie Shaohui-B21989; linuxppc-dev@lists.ozlabs.org list; Hu Mingkai-
> B21284; Chen Yuanquan-B41889
> Subject: Re: [PATCH][v2] powerpc/mm: u
On 08/31/2012 01:30 AM, Michael Ellerman wrote:
I don't think you should be using driver_register().
I think instead you want this to be a platform_driver, and use
platform_driver_register() ?
Thank you for that. The test engineer was on vacation so it took a while
before I got feedback on w
> -Original Message-
> From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
> Sent: Monday, September 10, 2012 10:12 AM
> To: Bhushan Bharat-R65777
> Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; ag...@suse.de;
> Wood Scott-B07421; Bhushan Bharat-R65777
> Subject
On Mon, 2012-09-10 at 16:54 +1000, Michael Neuling wrote:
> On POWER6 and POWER7 if the input operand to an instruction is a
> denormalised single precision binary floating we can take a
^
point value?
Le 16/08/2012 17:21, Alan Cox a écrit :
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters
are received before the next data character, an idle timeout occurs
and the buffer is closed,
generating a maskable inte
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