On Thu, Mar 05 2009, Geert Uytterhoeven wrote:
> On Thu, 5 Mar 2009, Jens Axboe wrote:
> > On Thu, Mar 05 2009, Geert Uytterhoeven wrote:
> > > On Thu, 5 Mar 2009, Jens Axboe wrote:
> > > > On Wed, Mar 04 2009, Geert Uytterhoeven wrote:
> > > > > Below is the rewrite of the PS3 Video RAM Storage Dr
I'm running into a dilemma choosing between two approaches of defining device
tree binding. Let's say if we have several chips with a similar SoC block, but
each of them have different quirks. If I define different compatibles for each
of the chips, the driver will have a longer match table
Hi,
I'm running into a dilemma choosing between two approaches of defining device
tree binding. Let's say if we have several chips with a similar SoC block, but
each of them have different quirks. If I define different compatibles for each
of the chips, the driver will have a longer match tab
Did you enable the descriptor bit 3 to have a try?
From: Ben Menchaca [mailto:ben.mench...@gmail.com]
Sent: Friday, March 06, 2009 2:10 PM
To: Liu Dave-R63238
Cc: linuxppc-dev@ozlabs.org
Subject: Re: 83xx: Marking or Alloc
I can look at ACR morning...although I can say with a fair amount of
certainty that I have not changed it from the POR value.
I will try enabling No Snoop for CSB in the descriptor (bit 3, yes?)...this
seems a bit counterintuitive to me.
What is the hope regarding these two? Some combination I a
could you try to set '1' to DMA description bit3?
From: Liu Dave-R63238
Sent: Friday, March 06, 2009 1:41 PM
To: 'Ben Menchaca'
Cc: linuxppc-dev@ozlabs.org
Subject: RE: 83xx: Marking or Allocating Pages as
Cache-Inhibited
what is the value of ACR register?
From: Ben Menchaca [mailto:ben.mench...@gmail.com]
Sent: Friday, March 06, 2009 1:38 PM
To: Liu Dave-R63238
Cc: linuxppc-dev@ozlabs.org
Subject: Re: 83xx: Marking or Allocating Pages as
C
1. BAT2 in linux is set to WIMG=0010, and covers all 64M
2. PEX_DEVICE_CONTROL in PCI-E Config Space (0x54): 0x1020
3. PEX_xDMA_CTRL is set to 0x0401 at the initiation of the DMA.
4. OWAR0 is set to 0xF005, so NSNP is 0.
5. The DMA descriptor (randomly chosen when I hit a trigger...jus
and what settings is DMA description bit 3?
> -Original Message-
> From: linuxppc-dev-bounces+daveliu=freescale@ozlabs.org
> [mailto:linuxppc-dev-bounces+daveliu=freescale@ozlabs.org]
> On Behalf Of Liu Dave-R63238
> Sent: Friday, March 06, 2009 1:22 PM
> To: Ben Menchaca; linux
Did you enable the snoop bit at PEX_WDMA_CTRL[SNOOP]
and PEX_RDMA_CTRL[SNOOP]?
What is the freq settings? CORE/CSB bus.
Thanks, Dave
From: linuxppc-dev-bounces+daveliu=freescale@ozlabs.org
[mailto:linuxppc-dev-bounces+daveliu=freescale@ozlabs.org
I am working on a Freescale 8314e design, and the embedded device is
configured as a PCI-e endpoint running a 2.6.27-5 kernel. For context, we
have written a kernel module which, among other things, uses the RDMA/WDMA
engine in the PCI-e IP block. On the host side, these DMAs are coherent.
Howeve
The RPA PCI hotplug driver calls EEH routines, so should depend on
EEH. Also PPC_PSERIES implies PPC64, so remove that.
Signed-off-by: Michael Ellerman
---
drivers/pci/hotplug/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/hotplug/Kconfig b/drivers/
The Axon MSI driver depends on more than just PCI_MSI, so add a
Kconfig fragment for it. Fixes randconfig build failures.
Signed-off-by: Michael Ellerman
---
arch/powerpc/platforms/cell/Kconfig |5 +
arch/powerpc/platforms/cell/Makefile |2 +-
2 files changed, 6 insertions(+), 1 del
Signed-off-by: Michael Ellerman
---
arch/powerpc/platforms/pseries/Kconfig |5 +
arch/powerpc/platforms/pseries/Makefile |2 +-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/Kconfig
b/arch/powerpc/platforms/pseries/Kconfig
index ddc2a3
After UART interrupt handler is installed and rx is enabled, if an rx
interrupt comes before hardware init, rx->cur will be updated. Then the
hardware init will reset BD and make rx->cur out of sync, move the hardware
init code before request_irq.
Signed-off-by: Xiaotian Feng
---
drivers/ser
On Thu, Mar 5, 2009 at 5:34 PM, Scott Wood wrote:
> Does the above mean "SRCK, STCK, SRFS, and STFS must all be connected to the
> same clock", or does it mean "SRCK must be connected to the same clock as
> STCK, and SRFS must be connected to the same clock as STFS"?
The latter. I'll reword it.
There's no way for us to express to firmware that we want a
discontiguous, or non-zero based, range of MSI-X entries. So we
must reject such requests.
Signed-off-by: Michael Ellerman
---
arch/powerpc/platforms/pseries/msi.c | 24
1 files changed, 24 insertions(+), 0 de
Timur Tabi wrote:
+- fsl,ssi-asynchronous:
+If specific, the SSI is to be programmed in asynchronous
+mode. In this mode, SRCK and STCK must be connected to the
+same clock, and SRFS and STFS must also be connected to the
+
Add the definition of the fsl,ssi-asynchronous property to ssi.txt
(documentation
of the device tree bindings for the Freescale SSI device).
Also tidy up the layout of ssi.txt.
Signed-off-by: Timur Tabi
---
Documentation/powerpc/dts-bindings/fsl/ssi.txt | 64 +--
1 files
This patch adds a new driver: sdhci-of. The driver is similar to
the sdhci-pci, it contains common probe code, and controller-specific
ops and quirks.
So far there are only Freescale eSDHC ops and quirks.
Signed-off-by: Anton Vorontsov
Acked-by: Arnd Bergmann
---
drivers/mmc/host/Kconfig|
FSL eSDHC controllers can support maximum block size up to 4096 bytes,
the MBL (Maximum Block Length) field in the capabilities register
extended by one bit, and is set to 0x3.
But the SDHCI core doesn't support blocks of 4096 bytes, and thus
forces blksz to the lowest value -- 512 bytes. With thi
FSL eSDHC controllers losing signal/interrupt enable states after
reset, so we should re-enable them.
Signed-off-by: Anton Vorontsov
---
drivers/mmc/host/sdhci.c |7 +++
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sd
Small udelay is needed to make eSDHC work in PIO mode. Without
the delay reading causes endless interrupt storm, and writing
corrupts data. The first guess would be that we must wait for
some bit in some register, but I didn't find any reliable bits
that change before and after the delay.
Signed-o
FSL eSDHC hosts have incompatible register map to manage the SDCLK.
This patch adds set_clock callback so that drivers could overwrite
set_clock behaviour.
Similar patch[1] was posted by Ben Dooks, though in Ben's version the
callback is named change_clock, plus the patch has some unrelated bits
t
From: Ben Dooks
Some controllers do not provide clock information in their capabilities
(in the Samsung case, it is because there are multiple clock sources
available to the controller). Add hooks to allow the system to supply
clock information.
p.s.
In the original Ben's patch there was a bug t
This patch adds SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk. When
specified, the sdhci driver will invert WP state.
p.s. Actually, the quirk is more board-specific than
controller-specific.
Signed-off-by: Anton Vorontsov
---
drivers/mmc/host/sdhci.c |2 ++
drivers/mmc/host/sdhci.h |2
This patch adds SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk. When specified,
sdhci driver will set MMC_CAP_NEEDS_POLL MMC host capability, and won't
enable card insert/remove interrupts.
This is needed for hosts with unreliable card detection, such as FSL
eSDHC. The original eSDHC driver was tring to
Some hosts (that is, FSL eSDHC) throw PIO interrupts during DMA
transfers, this causes tons of unneeded interrupts, and thus highly
degraded speed.
This patch modifies the driver so that now we only enable relevant
(DMA or PIO) interrupts during transfers.
Signed-off-by: Anton Vorontsov
---
dri
Card detection interrupts should be handled separately as they should
not be enabled before mmc_add_host() returns and should be disabled
before calling mmc_remove_host(). The same is for suspend and resume
routines.
sdhci_init() no longer enables card-detection irqs. Instead, two new
functions im
Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
read{l,b,w}).
With this patch drivers may change memory accessors, so that we can
support hosts with "weird" IO memory access requirments.
For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit
width, with big-endi
Hi all,
Much thanks for the previous comments. Here comes v2.
Changes since v1:
- "Add support for bus-specific IO memory accessors" patch no longer
touches sdhci-pci. The changes were no longer needed since I dropped
"Add type checking ..." patch back in RFCv2;
- Patch "Add support for hosts
On Fri, Mar 06, 2009 at 01:07:05AM +1100, Michael Ellerman wrote:
> On Thu, 2009-03-05 at 01:13 -0600, Olof Johansson wrote:
> > On Thu, Mar 05, 2009 at 03:41:41PM +1100, Michael Ellerman wrote:
> > > The hardware is only present on those machines, and the driver
> > > depends on infrastructure whi
The return code from invoking the notifier chain when updating the
ibm,dynamic-memory property is not handled properly. In failure
cases (rc == NOTIFY_BAD) we should be restoring the original value
of the property. In success (rc == NOTIFY_OK) we should be returning
zero from the calling routine.
On Thu, Mar 05, Geert Uytterhoeven wrote:
> On Thu, 5 Mar 2009, Geert Uytterhoeven wrote:
> > On Thu, 5 Mar 2009, Olaf Hering wrote:
> > > I see our old mtddriver does not have modalias support for autoloading.
> >
> > You forgot to backport commit 0a2d15b928e0b1673d4ed5f48d95af211b6fcc06
> > ("m
Michael Ellerman wrote:
Dang it, that's my fault. Thanks for catching it Sachin.
I assumed pseries always enabled EEH, but I see now you can disable it
if you have EMBEDDED set (which your config does).
It's a bit yucky making the MSI code depend on EEH, but the only other
option would be to pu
On Thu, 5 Mar 2009, Jens Axboe wrote:
> On Thu, Mar 05 2009, Geert Uytterhoeven wrote:
> > On Thu, 5 Mar 2009, Jens Axboe wrote:
> > > On Wed, Mar 04 2009, Geert Uytterhoeven wrote:
> > > > Below is the rewrite of the PS3 Video RAM Storage Driver as a plain
> > > > block
> > > > device, as request
On Thu, Mar 5, 2009 at 12:41 AM, Michael Guntsche wrote:
> On Wed, 4 Mar 2009 08:57:59 -0700, Grant Likely
> wrote:
>> You might be able to use of_attach_node() & prom_add_property() to
>> modify the tree, but I've never done it myself. Give it a try and
>> tell me if it works. :-)
>>
>
> Hello
On Thu, 2009-03-05 at 01:13 -0600, Olof Johansson wrote:
> On Thu, Mar 05, 2009 at 03:41:41PM +1100, Michael Ellerman wrote:
> > The hardware is only present on those machines, and the driver
> > depends on infrastructure which is selected by the Kconfig for
> > cell blades.
>
> Wouldn't it make m
On Thu, 2009-03-05 at 17:06 +0530, Sachin P. Sant wrote:
> Next March 5th randconfig build fails with
>
> arch/powerpc/platforms/pseries/msi.c: In function find_pe_dn:
> arch/powerpc/platforms/pseries/msi.c:210: error: implicit declaration of
> function find_device_pe
>
> CONFIG_EEH is not set i
Hello,
I have an SPI device that sends an IRQ to the CPU (MPC5200) via GPIO (GPT6):
gpt6: ti...@660 { // General Purpose Timer GPT6 in GPIO mode for
SMC4000IO sample irq.
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
cell-index = <6>;
reg = <0x660 0x10
I forgot to include my changes in arch/powerpc/include/asm/gpio.h:
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
index ea04632..38762ed 100644
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -38,12 +38,9 @@ static inline int gpio_can
On Thu, Mar 05 2009, Geert Uytterhoeven wrote:
> Hi Jens,
>
> On Thu, 5 Mar 2009, Jens Axboe wrote:
> > On Wed, Mar 04 2009, Geert Uytterhoeven wrote:
> > > Below is the rewrite of the PS3 Video RAM Storage Driver as a plain block
> > > device, as requested by Arnd Bergmann.
> > >
> > > The
Hi Jens,
On Thu, 5 Mar 2009, Jens Axboe wrote:
> On Wed, Mar 04 2009, Geert Uytterhoeven wrote:
> > Below is the rewrite of the PS3 Video RAM Storage Driver as a plain block
> > device, as requested by Arnd Bergmann.
> >
> > The MTD-based PS3 Video RAM Storage Driver was integrated into t
On Thu, 5 Mar 2009, Geert Uytterhoeven wrote:
> On Thu, 5 Mar 2009, Olaf Hering wrote:
> > I see our old mtddriver does not have modalias support for autoloading.
>
> You forgot to backport commit 0a2d15b928e0b1673d4ed5f48d95af211b6fcc06
> ("mtd/ps3vram: Add modalias support to the ps3vram driver"
Hello Josh,
Today I want to check if there are new changes from your git tree,
I read it from the MAINTAINERS file, but git told it can't find that
tree, then I go to the web,
http://www.kernel.org/pub/scm/linux/kernel/git/jwboyer/
and found your tree's name has changed,
However, please remember
Geert Uytterhoeven wrote:
Ideally, we think it would be best if the existing MTD-based ps3vram driver
would be replaced by the new block-based ps3vram driver before 2.6.29 is
released. This would relieve the burden of supporting two different swap space
schemes on PS3 (swap on /dev/mtdblock0 vs.
On Wed, Mar 04 2009, Geert Uytterhoeven wrote:
> Hi,
>
> Below is the rewrite of the PS3 Video RAM Storage Driver as a plain block
> device, as requested by Arnd Bergmann.
>
> The MTD-based PS3 Video RAM Storage Driver was integrated into the mainline
> kernel in 2.6.29-rc1.
>
> Ideally, w
On Thu, 5 Mar 2009, Olaf Hering wrote:
> Am 04.03.2009 um 14:57 schrieb Geert Uytterhoeven:
> >Ideally, we think it would be best if the existing MTD-based ps3vram driver
> >would be replaced by the new block-based ps3vram driver before 2.6.29 is
> >released. This would relieve the burden of suppor
48 matches
Mail list logo
