[git pull] Please pull powerpc.git merge branch

Hi Linus ! Here's 4 small powerpc fixes, a couple are regression in .29, and the others are nasty enough bugs with trivial enough fixes that I deemed then ok to go into .29 (and back into stable). The following changes since commit b578f3fcca1e78624dfb5f358776e63711d7fda2: Linus Torvalds (1):

[PATCH] Reduce hashtable size when using 64kB pages

At the moment we size the hashtable based on 4kB pages / 2, even on a 64kB kernel. This results in a hashtable that is much larger than it needs to be. Grab the real page size and size the hashtable based on that. Note: this only works on non hypervisor machines. Signed-off-by: Anton Blanchard

Re: [PATCH] pci/msi: Use #ifdefs instead of weak functions

On Sunday, January 18, 2009 4:31 pm Michael Ellerman wrote: > Weak functions aren't all they're cracked up to be. They lead to > incorrect binaries with some toolchains, they require us to have empty > functions we otherwise wouldn't, and the unused code is not elided > (as of gcc 4.3.2 anyway). >

[PATCH] powerpc: New cpu type shows up as "unknown" even when logical PVR is recognized

When identify_cpu() is called a second time with a logical PVR, it only copies a subset of the cpu_spec structure to avoid overwriting the performance monitor fields that were initialized based on the real PVR. If the real PVR is not recognized, the structure is initialized with default data in wh

RE: LINUX BOOT UP PROBLEM-PPC405 ML403

Hi Grant, I can not find the /dev/ttyUL0 in my root filesystem. Is that the problem? What should I do? Just make a node, like : mknod /dev/ttyUL0? I am not familiar with the root filesystem. Thanks! Best regards, Li Jun -Original Message- From: Grant Likely [mailto:grant.lik...@secretlab

Re: LINUX BOOT UP PROBLEM-PPC405 ML403

Is there a /dev/ttyUL0 in your root filesystem? On Fri, Feb 13, 2009 at 10:10 AM, Li Jun (Aaron) wrote: > Hi, > > When I try to boot the linux on the Xilinx virtex4 fx ml403 board. > > > > The information below shows up: > >

Re: Chipselect in SPI binding with mpc5200-psc-spi

Thanks Greg, I'm having success more success with the driver now, The device gets nicely probed and the probe function gets the properties from the device tree, The following patch from Anton Vorontsov: http://kerneltrap.org/mailarchive/linux-kernel/2008/5/23/1922744 Was very useful as exampl

MPC8248 IDMA PCI burst

Hi, I am having some problem with the PCI burst using the MPC8248 IDMA feature. I can get a continuous burst of 2k when transferring data from the system memory to the PCI direction but in the other direction (i.e. PCI to system memory) the PCI burst is fragmented with 32 bytes of fragment. I

LINUX BOOT UP PROBLEM-PPC405 ML403

Hi, When I try to boot the linux on the Xilinx virtex4 fx ml403 board. The information below shows up: - Welcome to ML403 Linux 2.6 Starting system... mounting /proc: done. Mounting '/' read-write: done. brin

Re: [PATCH 11/13] sdhci: Add quirk for controllers that need IRQ re-init after reset

On Fri, Feb 13, 2009 at 04:47:13PM +0100, Laurent Pinchart wrote: > Hi Anton, > > On Friday 13 February 2009 15:47:38 Anton Vorontsov wrote: [...] > > sdhci_host *host) static void sdhci_reset(struct sdhci_host *host, u8 mask) > > { > > unsigned long timeout; > > + u32 ier = 0; /* shut up g

Re: [PATCH 11/13] sdhci: Add quirk for controllers that need IRQ re-init after reset

Hi Anton, On Friday 13 February 2009 15:47:38 Anton Vorontsov wrote: > FSL eSDHC controllers losing signal/interrupt enable states after > reset, so we should re-enable them. > > Signed-off-by: Anton Vorontsov > --- > drivers/mmc/host/sdhci.c |7 +++ > drivers/mmc/host/sdhci.h |2 ++

Re: [MPC8272ADS]Problem adding flash partitions inside the device tree

Jean-Michel Hautbois wrote: 2009/2/12 Scott Wood : On Thu, Feb 12, 2009 at 03:26:58PM +0100, Jean-Michel Hautbois wrote: I think that the problem is in the reg part, but I can't understand why. Isn't it the RAM mpping of my MTD that is the first address ? No, it's the offset into the chipselec

SCCx in Sync HDLC mode

Is there any work being proposed/done in this area? I'm looking at the drivers/serial/cpm_uart files and see no support for sync/HDLC SCCx channels. Can anyone offer some history or insight to this area? -- Jim Black Senior Software Engineer Aztek Networks, Inc. 2477 55th Street, Suite 202 Boulde

[PATCH v2] Configure PSC4 and PSC5 as UART.

On digsy MTC PSC4 and PSC5 should be configured as UART, not PSC3 and PSC4. Signed-off-by: Grzegorz Bernacki --- Version 2: - rebased to Ben Herrenschmidt's -next arch/powerpc/boot/dts/digsy_mtc.dts | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/powerp

Re: [PATCH 002/002] de2104x: support for systems lacking cache coherence

2009/2/13, Benjamin Herrenschmidt : > > Can you tell me more about the mesh crash ? Do you have a log ? > Please find attached the device-tree and a log of loading the mesh module after the boot. This way it didn't crash, but did odd things: all it should find, on the bus, is a cd-rom drive at 3. N

Re: Chipselect in SPI binding with mpc5200-psc-spi

On Fri, Feb 13, 2009 at 3:40 AM, Henk Stegeman wrote: > I'm busy adding support for slave deviced behind mpc52xx-psc-spi. > One complication I have is that my SPI slave device has an interrupt output > to the CPU. > My idea is to add it as a gpios property in the slave device's > configuration: >

Re: [PATCH] Configure PSC4 and PSC5 as UART.

Hi Grzegorz, Please rebase this patch on top of Ben Herrenschmidt's -next tree. This version is making changes to an older version of the digsy_mtc.dts file. g. On Fri, Feb 13, 2009 at 6:52 AM, Grzegorz Bernacki wrote: > On digsy MTC PSC4 and PSC5 should be configured as UART, not PSC3 and PSC4

[PATCH 1/2] powerpc, ftrace: use unsigned int for instruction manipulation

From: Steven Rostedt The original port of ftrace to PowerPC kept a lot of the code used by x86. Some of this code was to handle x86's 5 byte instruction. This was handled by using character arrays to manipulate the code. PowerPC has a consistent 4 byte instruction. Using unsigned ints makes the

[PATCH 2/2] powerpc, ftrace: use create_branch lib function

From: Steven Rostedt Impact: clean up, remove duplicate code When ftrace was first ported to PowerPC, there existed a create_function_call that would create the instruction to make a call to a given address. Unfortunately, this call expected to write to the address it was given, and since it use

[PATCH 0/2] [git-pull] powerpc, ftrace clean ups

Benjamin, Please pull the latest ppc/ftrace tree, which can be found at: git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-2.6-trace.git ppc/ftrace Steven Rostedt (2): powerpc, ftrace: use unsigned int for instruction manipulation powerpc, ftrace: use create_branch lib

[PATCH 13/13] mmc: Add OpenFirmware bindings for SDHCI driver

This patch adds a new driver: sdhci-of. The driver is similar to the sdhci-pci, it contains common probe code, and controller-specific ops and quirks. So far there are only Freescale eSDHC ops and quirks. Signed-off-by: Anton Vorontsov Acked-by: Arnd Bergmann --- drivers/mmc/host/Kconfig|

[PATCH 12/13] sdhci: Add quirk for controllers with max. block size up to 4096 bytes

FSL eSDHC controllers can support maximum block size up to 4096 bytes. The MBL (Maximum Block Length) field in the capabilities register extended by one bit, and bits 13:15 in the block size register reserved. Signed-off-by: Anton Vorontsov --- drivers/mmc/host/sdhci.c | 28 +++

[PATCH 11/13] sdhci: Add quirk for controllers that need IRQ re-init after reset

FSL eSDHC controllers losing signal/interrupt enable states after reset, so we should re-enable them. Signed-off-by: Anton Vorontsov --- drivers/mmc/host/sdhci.c |7 +++ drivers/mmc/host/sdhci.h |2 ++ 2 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/sd

[PATCH 10/13] sdhci: Add quirk for controllers that need small delays for PIO

Small udelay is needed to make eSDHC work in PIO mode. Without the delay reading causes endless interrupt storm, and writing corrupts data. The first guess would be that we must wait for some bit in some register, but I didn't find any reliable bits that change before and after the delay. Signed-o

[PATCH 09/13] sdhci: Add set_clock callback and a quirk for nonstandard clocks

FSL eSDHC hosts have incompatible register map to manage the SDCLK. This patch adds set_clock callback so that drivers could overwrite set_clock behaviour. Similar patch[1] was posted by Ben Dooks, though in Ben's version the callback is named change_clock, plus the patch has some unrelated bits t

[PATCH 08/13] sdhci: Add get_{max,timeout}_clock callbacks

From: Ben Dooks Some controllers do not provide clock information in their capabilities (in the Samsung case, it is because there are multiple clock sources available to the controller). Add hooks to allow the system to supply clock information. p.s. In the original Ben's patch there was a bug t

[PATCH 07/13] sdhci: Add support for hosts with strict 32 bit addressing

SDHCI driver must take special care when working with "triggering" registers on hosts with strict 32 bit addressing. In FSL eSDHC hosts all registers are 32 bit width, writing to the first half of any register will cause [undefined?] write the second half of the register. That is, 16 bit write to

[PATCH 06/13] sdhci: Add support for hosts reporting inverted write-protect state

This patch adds SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk. When specified, the sdhci driver will invert WP state. p.s. Actually, the quirk is more board-specific than controller-specific. Signed-off-by: Anton Vorontsov --- drivers/mmc/host/sdhci.c |2 ++ drivers/mmc/host/sdhci.h |2

[PATCH 05/13] sdhci: Add support for card-detection polling

This patch adds SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk. When specified, sdhci driver will set MMC_CAP_NEEDS_POLL MMC host capability, and won't enable card insert/remove interrupts. This is needed for hosts with unreliable card detection, such as FSL eSDHC. The original eSDHC driver was tring to

[PATCH 04/13] sdhci: Enable only relevant (DMA/PIO) interrupts during transfers

Some hosts (that is, FSL eSDHC) throw PIO interrupts during DMA transfers, this causes tons of unneeded interrupts, and thus highly degraded speed. This patch modifies the driver so that now we only enable relevant (DMA or PIO) interrupts during transfers. Signed-off-by: Anton Vorontsov --- dri

[PATCH 03/13] sdhci: Split card-detection IRQs management from sdhci_init()

Card detection interrupts should be handled separately as they should not be enabled before mmc_add_host() returns and should be disabled before calling mmc_remove_host(). The same is for suspend and resume routines. sdhci_init() no longer enables card-detection irqs. Instead, two new functions im

[PATCH 02/13] sdhci: Add support for bus-specific IO memory accessors

Currently the SDHCI driver works with PCI accessors (write{l,b,w} and read{l,b,w}). With this patch drivers may change memory accessors, so that we can support hosts with "weird" IO memory access requirments. For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit width, with big-endi

[PATCH 01/13] sdhci: Add quirk for controllers with no end-of-busy IRQ

From: Ben Dooks The Samsung SDHCI (and FSL eSDHC) controller block seems to fail to generate an INT_DATA_END after the transfer has completed and the bus busy state finished. Changes in e809517f6fa5803a5a1cd56026f0e2190fc13d5c to use the new busy method are the cause of the behaviour change. Si

[PATCH RFC 0/13] FSL eSDHC support

Hi all, Thanks for the comments on the previous version, here comes another RFC... Changes since the second RFC: - Addressed all comments that were raised by Pierre Ossman. There were too many to mention them all, so here is the link: http://lkml.org/lkml/2009/2/6/320 Changes since the first

Re: Gianfar ethernet MPC85xx driver not seen anymore when moving to 2.6.29 kernel

On Feb 13, 2009, at 4:34 AM, willy jacobs wrote: When I moved (config file and device tree) from 2.6.28 (and earlier kernel releases) to 2.6.29-rc2 for some reason the Gianfar driver is correctly compiled in, but not probed anymore during kernel booting. I looked into the Changelogs, but d

Re: [PATCH 10/11] sdhci: Add quirk for Freescale eSDHC controllers

On Sun, Feb 08, 2009 at 10:12:09PM +0100, Pierre Ossman wrote: > On Fri, 6 Feb 2009 21:07:01 +0300 > Anton Vorontsov wrote: > > > This patch adds SDHCI_QUIRK_FSL quirk. The quirk is used to instruct > > the sdhci driver about various FSL eSDHC host incompatibilities: > > > > No device quirks pl

Re: [PATCH 02/11] sdhci: Add support for bus-specific IO memory accessors

On Sun, Feb 08, 2009 at 09:50:20PM +0100, Pierre Ossman wrote: > On Fri, 6 Feb 2009 21:06:45 +0300 > Anton Vorontsov wrote: > > Currently the SDHCI driver works with PCI accessors (write{l,b,w} and > > read{l,b,w}). > > > > With this patch drivers may change memory accessors, so that we can > > s

[PATCH] Configure PSC4 and PSC5 as UART.

On digsy MTC PSC4 and PSC5 should be configured as UART, not PSC3 and PSC4. Signed-off-by: Grzegorz Bernacki --- arch/powerpc/boot/dts/digsy_mtc.dts | 16 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dt

Re: Chipselect in SPI binding with mpc5200-psc-spi

I'm busy adding support for slave deviced behind mpc52xx-psc-spi. One complication I have is that my SPI slave device has an interrupt output to the CPU. My idea is to add it as a gpios property in the slave device's configuration: s...@2400 {// PSC3 (SPI IF to the IO-controller )

Gianfar ethernet MPC85xx driver not seen anymore when moving to 2.6.29 kernel

When I moved (config file and device tree) from 2.6.28 (and earlier kernel releases) to 2.6.29-rc2 for some reason the Gianfar driver is correctly compiled in, but not probed anymore during kernel booting. I looked into the Changelogs, but did'nt see any change regarding this. Do I need to cha

Not able to see any output if kernel module loaded for the first time

Hello All, I am facing perhaps some strange kind of problem. I have mpc8313erdb eval board and wrote the GPIO driver, the driver is just making the assigned GPIO[3] pin high and low. If I load this module first time after bootup or if I make some change in the code and compile and load the module

Re: [PATCH] powerpc: Fix _PAGE_CHG_MASK

Benjamin Herrenschmidt wrote: > On Fri, 2009-02-13 at 13:49 +1100, Benjamin Herrenschmidt wrote: > >>> diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h >>> b/arch/powerpc/include/asm/pgtable-ppc32.h >>> index 75dded6..8298afc 100644 >>> --- a/arch/powerpc/include/asm/pgtable-ppc32.h >>> +++

Re: [MPC8272ADS]Problem adding flash partitions inside the device tree

2009/2/12 Scott Wood : > On Thu, Feb 12, 2009 at 03:26:58PM +0100, Jean-Michel Hautbois wrote: >> I think that the problem is in the reg part, but I can't understand why. >> Isn't it the RAM mpping of my MTD that is the first address ? > > No, it's the offset into the chipselect. > > -Scott > OK.

Re: 2.6.28 radeon.ko oops, QS22 (Cell) blade.

On Tue, 2009-02-10 at 14:18 +0300, Wartan Hachaturow wrote: > Hi there. > > While trying to bring up X.org on this beast, I've stumbled upon this > oops in radeon.ko > (right on the first write attempt): You may want to get whatever latest patches are in Dave Airlie's dri-next tree. I've fixed a