On Tue, 2008-12-16 at 16:10 +1100, Paul Mackerras wrote:
> I have added the following commits to the next and master branches of
> my powerpc.git tree (including commits pulled from Kumar's tree). I
> have also pulled in Linus' current tree and the 3 commits that I just
> asked him to pull.
Is th
Dave Hansen writes:
> The use of NODE_DATA() in the ppc init code is fragile. We use
> it for some nodes as we are initializing others. As the loop
> initializing them has gotten more complex and broken out into
> several functions it gets harder and harder to remember how
> this goes.
With thi
Tony Breeds wrote:
> ibm_configure_kernel_dump, is passed as the token to rtas_call() but I
> cannot see where it is initialised. Set it to something sane?
Yes, please.
Acked-by: Nathan Lynch
Would be good to know whether the dump area registration and dump
retrieval are working with your chan
I have added the following commits to the next and master branches of
my powerpc.git tree (including commits pulled from Kumar's tree). I
have also pulled in Linus' current tree and the 3 commits that I just
asked him to pull.
Paul.
Anton Vorontsov (2):
powerpc/qe: Move cmxgcr_lock definit
Dave Hansen writes:
> I'm debating whether this is worth it. It makes this a bit more clean
> looking, but doesn't seriously enhance readability. But, I do think
> it helps a bit.
I get this when compiling a pseries config (with the patches up to
this point applied but not 7/8 or 8/8):
CC
Linus,
Please pull from the 'merge' branch of
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git merge
to get three more commits that fix bugs causing kernel crashes on
powerpc.
Thanks,
Paul.
arch/powerpc/mm/hugetlbpage.c |3 +++
arch/powerpc/mm/numa.c
ibm_configure_kernel_dump, is passed as the token to rtas_call() but I
cannot see where it is initialised. Set it to something sane?
Signed-off-by: Tony Breeds
---
arch/powerpc/platforms/pseries/phyp_dump.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/p
print_dump_header() will be called at least once with a NULL pointer in
a normal boot sequence. if DEBUG is defined then we will get a deref,
add a quick fix to exit early in the NULL pointer case.
Signed-off-by: Tony Breeds
---
arch/powerpc/platforms/pseries/phyp_dump.c |3 +++
1 files cha
On Tue, 16 Dec 2008, Paul Mackerras wrote:
> Trent Piepho writes:
>> The MTD system supports operation where a direct mapped flash chip is
>> mapped twice. The normal mapping is a standard ioremap(), which is
>> non-cached and guarded on powerpc. The second mapping is used only for
>> reads and c
Trent Piepho writes:
> The MTD system supports operation where a direct mapped flash chip is
> mapped twice. The normal mapping is a standard ioremap(), which is
> non-cached and guarded on powerpc. The second mapping is used only for
> reads and can be cached and non-guarded. Currently, only t
Benjamin Herrenschmidt wrote:
>
> Don't 970MP have a shared L2 tho ?
The 970MP UM describes 1MB L2 per core, and the device tree on the
quad G5 reflects that... might be interesting to know what it looks
like on IBM JS21 for comparison's sake, but I think we're okay.
_
On Mon, 2008-12-15 at 16:33 -0600, Nathan Lynch wrote:
> Benjamin Herrenschmidt wrote:
> > On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> > > + /* OF on pmac has nodes instead of properties named "l2-cache"
> > > +* beneath CPU nodes.
> > > +*/
> > > + if (!str
On Mon, 2008-12-15 at 16:19 -0600, Kumar Gala wrote:
> Ok. Lets use MMU_FTR_LOCK_BCAST_TLB_OPS and have a comment about
> locking because bus implementations cant handle multiple ivax and/or
> multiple syncs.
>
Hi used MMU_FTR_LOCK_BCAST_INVAL :-) And I put a comment that says:
/* This indic
> Patches I want to still review and test:
>
> 6/16 powerpc/mm: Split mmu_context handling v3
> 7/16 powerpc/mm: Rework context management for CPUs with no hash table
> v2
> 9/16 powerpc/mm: Introduce MMU features v2
> 11/16 powerpc/mm: Add SMP support to no-hash TLB handling v3
> 12/16 powerpc
On Mon, 15 Dec 2008, Josh Boyer wrote:
>
> Did you actually change anything in this version when compared to the
> version you sent out last week? If not, is there a reason you sent it
> again without flagging it as a resend?
I sent it out last week? I'm trying to tie up loose ends before I leav
Benjamin Herrenschmidt wrote:
> On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> > + /* OF on pmac has nodes instead of properties named "l2-cache"
> > +* beneath CPU nodes.
> > +*/
> > + if (!strcmp(np->type, "cpu"))
> > + for_each_child_of_node(np
On Dec 15, 2008, at 3:18 PM, Benjamin Herrenschmidt wrote:
On Mon, 2008-12-15 at 15:10 -0600, Kumar Gala wrote:
Hmm.. are you mixing the two different locking needs together? The
is
locking of ivax vs tlbwe and there is locking around multiple "msgs"
on the bus. I know for us we can have
On Mon, 2008-12-15 at 15:10 -0600, Kumar Gala wrote:
> Hmm.. are you mixing the two different locking needs together? The is
> locking of ivax vs tlbwe and there is locking around multiple "msgs"
> on the bus. I know for us we can have any # of ivax's on the bus, but
> only one tlbsync.
I
On Dec 15, 2008, at 3:03 PM, Benjamin Herrenschmidt wrote:
The whole thing. Not totally clear, you have a better name ? Some
CPUs
want a lock on sync and some on ivax, I plan to lock the whole
sequence.
MMU_FTR_TLBIVAX_OR_SYNC_NEED_LOCK ?
Which completely blows away the nice tab'ing :-)
On Tue, 2008-12-16 at 08:03 +1100, Michael Ellerman wrote:
> On Mon, 2008-12-15 at 14:54 -0600, Kumar Gala wrote:
> > >
> > > #ifndef __ASSEMBLY__
> > > +
> > > +/*
> > > + * Macro to mark a page protection value as "uncacheable".
> > > + */
> > > +
> > > +#define _PAGE_CACHE_CTL (_PAGE_COHERENT |
On Dec 15, 2008, at 3:01 PM, Benjamin Herrenschmidt wrote:
-#ifdef CONFIG_44x
-#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
+#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
+#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED |
_PAGE_COHERENT)
#else
#define
> > The whole thing. Not totally clear, you have a better name ? Some CPUs
> > want a lock on sync and some on ivax, I plan to lock the whole
> > sequence.
>
> MMU_FTR_TLBIVAX_OR_SYNC_NEED_LOCK ?
Which completely blows away the nice tab'ing :-)
MMU_FTR_LOCK_BCAST_TLB_OPS ?
> Its probably a g
> > -#ifdef CONFIG_44x
> > -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
> > +#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
> > +#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
> > #else
> > #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
>
On Mon, 2008-12-15 at 14:54 -0600, Kumar Gala wrote:
> >
> > #ifndef __ASSEMBLY__
> > +
> > +/*
> > + * Macro to mark a page protection value as "uncacheable".
> > + */
> > +
> > +#define _PAGE_CACHE_CTL(_PAGE_COHERENT | _PAGE_COHERENT |
> > _PAGE_COHERENT | \
> > +_PAGE_WR
On Dec 15, 2008, at 2:46 PM, Benjamin Herrenschmidt wrote:
Index: linux-work/arch/powerpc/include/asm/mmu.h
===
--- linux-work.orig/arch/powerpc/include/asm/mmu.h 2008-12-15
14:36:20.0 +1100
+++ linux-work/arch/powerp
--- linux-work.orig/arch/powerpc/include/asm/pgtable-ppc32.h
2008-11-24 14:48:55.0 +1100
+++ linux-work/arch/powerpc/include/asm/pgtable-ppc32.h 2008-12-15
15:34:16.0 +1100
[snip]
@@ -436,20 +437,23 @@ extern int icache_44x_need_flush;
_PAGE_USER
On Mon, 15 Dec 2008 14:44:12 -0600
Kumar Gala wrote:
> Pathces left up to Josh & Ben
>
> 3/16 powerpc/4xx: Extended DCR support v2
I'd like to test this one a bit.
> 13/16 powerpc/44x: No need to mask MSR:CE, ME or DE in _tlbil_va on 440
This one should be good to go. I already Acked it.
>
On Mon, 2008-12-15 at 14:36 -0600, Kumar Gala wrote:
>
> Acked-by: Kumar Gala
>
> (I'm told git-format-patch -M is useful for such patches)
I'm still using quilt for my own developement.
Cheers,
Ben.
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> > +void local_flush_tlb_mm(struct mm_struct *mm)
> > +{
> > + unsigned int pid;
> > +
> > + preempt_disable();
> > + pid = mm->context.id;
> > + if (pid != MMU_NO_CONTEXT)
> > + _tlbil_pid(pid);
> > + preempt_enable();
> > +}
> > +EXPORT_SYMBOL(local_flush_tlb_mm);
>
> Do th
Paul,
Can you update powerpc.git to linus's top of tree (we need the
tlbil_va patch Linus picked up).
Also, can you pull in my next tree and some of Ben's trivial mmu
related changes:
1/16 powerpc: Fix bogus cache flushing on all 40x and BookE processors
v2 -- in my next tree (pull requ
On Tue, 16 Dec 2008 07:33:04 +1100
Michael Ellerman wrote:
> On Mon, 2008-12-15 at 13:35 -0600, Kumar Gala wrote:
> > On Dec 15, 2008, at 12:58 PM, Frank Fan wrote:
> >
> > > Hello,
> > >
> > > I am working on a freescale MPC8572 CPU board and use 32 bit
> > > Linux2.6.28. When I enable 64 bi
On Dec 14, 2008, at 11:44 PM, Benjamin Herrenschmidt wrote:
This renames the files to clarify the fact that they are used by
the hash based family of CPUs (the 603 being an exception in that
family but is still handled by that code).
This paves the way for the new tlb_nohash.c coming via a sub
On Mon, 2008-12-15 at 13:35 -0600, Kumar Gala wrote:
> On Dec 15, 2008, at 12:58 PM, Frank Fan wrote:
>
> > Hello,
> >
> > I am working on a freescale MPC8572 CPU board and use 32 bit
> > Linux2.6.28. When I enable 64 bit, it shows "kdump" in "kernel
> > options". Otherwise, "kdump" is disabl
Please pull from 'next' branch of
master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git next
to receive the following updates:
arch/powerpc/boot/dts/mpc8572ds.dts | 16
arch/powerpc/include/asm/cputable.h | 15 ---
2 files changed, 16 insertions(
On Dec 14, 2008, at 11:44 PM, Benjamin Herrenschmidt wrote:
This adds a local_flush_tlb_mm() call as a pre-requisite for some
SMP work for BookE processors
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/tlbflush.h |5 +
1 file changed, 5 insertions(+)
Acked-by: K
On Mon, 2008-12-15 at 16:43 +0100, Arnd Bergmann wrote:
> Didn't we lift the limit to 30,000 tasks at some point? The comment
> in linux/threads.h mentions that the PID space goes up to 4 million.
> What does actually happen when we increase pid_max to beyond 32768
> on those systems and try to use
On Dec 14, 2008, at 11:44 PM, Benjamin Herrenschmidt wrote:
This patch moves the whole no-hash TLB handling out of line into a
new tlb_nohash.c file, and implements some basic SMP support using
IPIs and/or broadcast tlbivax instructions.
Note that I'm using local invalidations for D->I cache c
On Dec 15, 2008, at 12:58 PM, Frank Fan wrote:
Hello,
I am working on a freescale MPC8572 CPU board and use 32 bit
Linux2.6.28. When I enable 64 bit, it shows "kdump" in "kernel
options". Otherwise, "kdump" is disabled.
Can someone give me some hint why kdump is for 64 bit PPC only?
Pr
Hello,
I am working on a freescale MPC8572 CPU board and use 32 bit Linux2.6.28.
When I enable 64 bit, it shows "kdump" in "kernel options". Otherwise,
"kdump" is disabled.
Can someone give me some hint why kdump is for 64 bit PPC only?
Thanks for the help,
Frank Fan
Alcatel-Lucent
Salt Lake Cit
On Mon, 15 Dec 2008 10:25:18 -0800
Trent Piepho wrote:
> The MTD system supports operation where a direct mapped flash chip is
> mapped twice. The normal mapping is a standard ioremap(), which is
> non-cached and guarded on powerpc. The second mapping is used only for
> reads and can be cached
The MTD system supports operation where a direct mapped flash chip is
mapped twice. The normal mapping is a standard ioremap(), which is
non-cached and guarded on powerpc. The second mapping is used only for
reads and can be cached and non-guarded. Currently, only the pxa2xx
mapping driver makes
Hi,
Does anyone has the UC1611 LCD controller driver of Kernel2.6?
Thanks for your help,
Mike
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On Monday 15 December 2008, Benjamin Herrenschmidt wrote:
> +/*
> + * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
> + * (virtual segment identifiers) for each context. Although the
> + * hardware supports 24-bit VSIDs, and thus >1 million contexts,
> + * we only use 32,768 of the
On Mon, 15 Dec 2008 16:45:05 +1100
Benjamin Herrenschmidt wrote:
> The handlers for Critical, Machine Check or Debug interrupts
> will save and restore MMUCR nowadays, thus we only need to
> disable normal interrupts when invalidating TLB entries.
>
> Signed-off-by: Benjamin Herrenschmidt
Acke
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