Paul,
Can you update powerpc.git to linus's top of tree (we need the
tlbil_va patch Linus picked up).
Also, can you pull in my next tree and some of Ben's trivial mmu
related changes:
1/16 powerpc: Fix bogus cache flushing on all 40x and BookE processors
v2 -- in my next tree (pull request sent)
2/16 powerpc: Fix asm EMIT_BUG_ENTRY with !CONFIG_BUG
4/16 powerpc/fsl-booke: Fix problem with _tlbil_va -- pick up via
update to linus head
5/16 powerpc/mm: Add local_flush_tlb_mm() to SW loaded TLB
implementations -- ack'd
8/16 powerpc/mm: Rename tlb_32.c and tlb_64.c to tlb_hash32.c and
tlb_hash64.c -- looks like a pure move
10/16 powerpc/mm: Remove flush_HPTE()
Patches I want to still review and test:
6/16 powerpc/mm: Split mmu_context handling v3
7/16 powerpc/mm: Rework context management for CPUs with no hash table
v2
9/16 powerpc/mm: Introduce MMU features v2
11/16 powerpc/mm: Add SMP support to no-hash TLB handling v3
12/16 powerpc/mm: Split low level tlb invalidate for nohash processors
14/16 powerpc/mm: Runtime allocation of mmu context maps for nohash
CPUs v2
15/16 powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED
Pathces left up to Josh & Ben
3/16 powerpc/4xx: Extended DCR support v2
13/16 powerpc/44x: No need to mask MSR:CE, ME or DE in _tlbil_va on 440
16/16 powerpc/44x: 44x TLB doesn't need "Guarded" set for all pages
- k
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