ct to keep the implementation straightforward. This
reduces duplication of cache-related fields while keeping cpuinfo_or1k
extensible in case more cache descriptors are added in the future.
This implementation is based on similar work done for MIPS and LoongArch.
Signed-off-by: Sahil Siddiq
---
B
ct to keep the implementation straightforward. This
reduces duplication of cache-related fields while keeping cpuinfo_or1k
extensible in case more cache descriptors are added in the future.
This implementation is based on similar work done for MIPS and LoongArch.
Signed-off-by: Sahil Siddiq
---
Ch
Hi,
On 3/15/25 2:26 AM, Stafford Horne wrote:
On Sat, Mar 15, 2025 at 01:34:03AM +0530, Sahil Siddiq wrote:
On 3/14/25 2:54 AM, Stafford Horne wrote:
On Tue, Mar 11, 2025 at 12:43:57AM +0530, Sahil Siddiq wrote:
Add cacheinfo support for OpenRISC.
[...]
None of the functions in drivers/base
that generalize this implementation and reduce
duplication.
Signed-off-by: Sahil Siddiq
---
Changes from v2 -> v3:
- arch/openrisc/include/asm/cacheflush.h: Declare new functions and macros.
- arch/openrisc/include/asm/cpuinfo.h: Implement new functions.
(cpu_cache_is_present):
1.
a few modifications.
This implementation is based on similar work done for MIPS and LoongArch.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq
---
Changes from v2 -> v3:
- arch/openrisc/kernel/cacheinfo.c:
1. Use new functions in
Hi Stafford,
On 3/18/25 1:13 PM, Stafford Horne wrote:
On Tue, Mar 18, 2025 at 12:06:30AM +0530, Sahil Siddiq wrote:
On 3/17/25 1:55 PM, Geert Uytterhoeven wrote:
On Sun, 16 Mar 2025 at 07:59, Stafford Horne wrote:
[...]
@@ -176,8 +177,11 @@ void __init paging_init(void)
barrier
Hi,
On 3/22/25 9:59 PM, Stafford Horne wrote:
On Sat, Mar 22, 2025 at 07:21:18PM +0530, Sahil Siddiq wrote:
On 3/18/25 1:13 PM, Stafford Horne wrote:
On Tue, Mar 18, 2025 at 12:06:30AM +0530, Sahil Siddiq wrote:
On 3/17/25 1:55 PM, Geert Uytterhoeven wrote:
On Sun, 16 Mar 2025 at 07:59
Hi,
On 3/22/25 9:10 PM, Markus Elfring wrote:
…
This patch provides a mechanism …
The patch also moves …
See also:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.14-rc7#n94
Thank you. I'll change the wording
Hi,
On 3/14/25 2:54 AM, Stafford Horne wrote:
On Tue, Mar 11, 2025 at 12:43:57AM +0530, Sahil Siddiq wrote:
Add cacheinfo support for OpenRISC.
[...]
None of the functions in drivers/base/cacheinfo.c that are capable of
pulling these details (e.g.: cache_size) have been used. This is because
Hi,
On 3/29/25 3:18 AM, Stafford Horne wrote:
On Sat, Mar 29, 2025 at 01:56:31AM +0530, Sahil Siddiq wrote:
[...]
diff --git a/arch/openrisc/include/asm/cpuinfo.h
b/arch/openrisc/include/asm/cpuinfo.h
index 82f5d4c06314..e46afbfe9b5a 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch
Hi,
Thank you for the review.
On 3/26/25 10:41 PM, Stafford Horne wrote:
On Mon, Mar 24, 2025 at 01:25:43AM +0530, Sahil Siddiq wrote:
According to the OpenRISC architecture manual, the dcache and icache may
not be present. When these caches are present, the invalidate and flush
registers may
a few modifications.
This implementation is based on similar work done for MIPS and LoongArch.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq
---
Changes from v3 -> v4:
- arch/openrisc/kernel/cacheinfo.c: Fix build warning det
Also add a new field "sets" to the new structure.
Signed-off-by: Sahil Siddiq
---
No changes from v3 -> v4.
Changes from v1/v2 -> v3:
- arch/openrisc/kernel/setup.c:
(print_cpuinfo):
1. Cascade changes made to struct cpuinfo_or1k.
2. These lines are ultimately shifted
that generalize this implementation and reduce
duplication.
Signed-off-by: Sahil Siddiq
---
Changes from v3 -> v4:
- arch/openrisc/include/asm/cpuinfo.h: Move new definitions to cache.c.
- arch/openrisc/mm/cache.c:
(cache_loop): Split function.
(cache_loop_page): New funct
ess/coding-style.html
Sahil Siddiq (3):
openrisc: Refactor struct cpuinfo_or1k to reduce duplication
openrisc: Introduce new utility functions to flush and invalidate
caches
openrisc: Add cacheinfo support
arch/openrisc/include/asm/cacheflush.h | 17
arch/openrisc/include/asm
eported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202503311807.bzauhy5l-...@intel.com/
Signed-off-by: Sahil Siddiq
---
Hi,
I noticed that the previous patches have already been merged in the
for-next branch of openrisc's repo. So, I thought I would send a separa
.0-or-later
+/*
+ * OpenRISC cacheinfo support
+ *
+ * Based on work done for MIPS and LoongArch. All original copyrights
+ * apply as per the original source declaration.
+ *
+ * OpenRISC implementation:
+ * Copyright (C) 2025 Sahil Siddiq
+ */
+
+#include
+#include
+#include
+#include
+
+s
Hi Stafford,
On 4/18/25 1:17 PM, Stafford Horne wrote:
On Fri, Apr 04, 2025 at 10:39:22AM +0530, Sahil Siddiq wrote:
[...]
Hi Sahil,
Sorry for delay in getting back on this.
No worries :)
I was working on getting this patches ready for upstreaming and noticed one
thing
Hi,
On 4/18/25 3:30 PM, Stafford Horne wrote:
On Fri, Apr 18, 2025 at 02:42:20PM +0530, Sahil Siddiq wrote:
On 4/18/25 1:17 PM, Stafford Horne wrote:
On Fri, Apr 04, 2025 at 10:39:22AM +0530, Sahil Siddiq wrote:
[...]
I was working on getting this patches ready for upstreaming and noticed one
that generalize this implementation and reduce
duplication.
Signed-off-by: Sahil Siddiq
---
Changes v5 -> v6:
- Changed 'From' and signed-off-by email addresses.
- cache.c:
(cache_loop): Make 'reg' unsigned short.
(cache_loop_page): Use __always_inline and make '
Also add a new field "sets" to the new structure.
Signed-off-by: Sahil Siddiq
---
Changes v5 -> v6:
- Changed 'From' and signed-off-by email addresses.
arch/openrisc/include/asm/cpuinfo.h | 16 +-
arch/openrisc/kernel/setup.c| 45 ++---
209875e262c1e2b60
[3]
https://lore.kernel.org/openrisc/aAMwri9RK2oNuC_p@antec/T/#mc42cafae92957171cef94065f25257e5bed37ed6
Sahil Siddiq (3):
openrisc: Refactor struct cpuinfo_or1k to reduce duplication
openrisc: Introduce new utility functions to flush and invalidate
caches
openrisc: Add cach
a few modifications.
This implementation is based on similar work done for MIPS and LoongArch.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq
---
Changes v5 -> v6:
- Changed 'From' and signed-off-by email addresses.
ar
Hi,
On 4/19/25 10:42 AM, Stafford Horne wrote:
On Fri, Apr 18, 2025 at 06:04:29PM +0530, Sahil Siddiq wrote:
On 4/18/25 3:30 PM, Stafford Horne wrote:
On Fri, Apr 18, 2025 at 02:42:20PM +0530, Sahil Siddiq wrote:
[...]
Maybe using another email in signed-off-by would be better. The current
a few modifications.
This implementation is based on similar work done for MIPS and LoongArch.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq
---
No change from v4 -> v5.
Changes from v3 -> v4:
- arch/openrisc/kernel/cache
that generalize this implementation and reduce
duplication.
Signed-off-by: Sahil Siddiq
---
Changes from v4 -> v5:
- arch/openrisc/include/asm/cpuinfo.h: Remove cb_inv_flush_is_implemented.
- arch/openrisc/mm/cache.c:
(cpu_cache_is_present): Shift definition to the
Also add a new field "sets" to the new structure.
Signed-off-by: Sahil Siddiq
---
No change from v3 -> v4/v5.
Changes from v1/v2 -> v3:
- arch/openrisc/kernel/setup.c:
(print_cpuinfo):
1. Cascade changes made to struct cpuinfo_or1k.
2. These lines are ultimately shifted
blocks.
While testing these changes with QEMU, I realized that the check being
performed in cpu_cache_is_present() would always get evaluated to true
when the UPR_UP bit was set. This series fixes this check and addresses
v4's review comments.
Thanks,
Sahil
Sahil Siddiq (3):
openrisc: Ref
Hi Stafford,
On 4/3/25 7:36 PM, Stafford Horne wrote:
[...]
I will just take this fix and apply it to the series (git fixup) rather than
take this patch as is. Also, as registers should be unsigned short, I think
we should change the type to that.
I will fixup patches in place.
Sure thing.
Sahil Siddiq (3):
openrisc: Refactor struct cpuinfo_or1k to reduce duplication
openrisc: Introduce new utility functions to flush and invalidate
caches
openrisc: Add cacheinfo support
arch/openrisc/include/asm/cacheflush.h | 17
arch/openrisc/include/asm/cpuinfo.h| 58
Also add a new field "sets" to the new structure.
Signed-off-by: Sahil Siddiq
---
Changes from v1/v2 -> v3:
- arch/openrisc/kernel/setup.c:
(print_cpuinfo):
1. Cascade changes made to struct cpuinfo_or1k.
2. These lines are ultimately shifted to the new file created in
pat
Hi,
On 3/29/25 3:42 PM, Stafford Horne wrote:
Thanks for the respin.
I will take this version and put it in linux next to see if any issues come up.
-Stafford
Sounds good. Let me know if any more changes are required.
On Sat, Mar 29, 2025 at 03:16:19PM +0530, Sahil Siddiq wrote:
Hi,
The
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