On Sat, 7 Jul 2018 05:37:22 +0200
Jann Horn wrote:
> The first checks in mtdchar_read() and mtdchar_write() attempt to limit
> `count` such that `*ppos + count <= mtd->size`. However, they ignore the
> possibility of `*ppos > mtd->size`, allowing the calculation of `count` to
> wrap around. `mtd
On Fri, 22 Jun 2018 09:52:20 +0800
Zhouyang Jia wrote:
> When ioremap_nocache fails, the lack of error-handling code may
> cause unexpected results.
>
> This patch adds error-handling code after calling ioremap_nocache.
>
> Signed-off-by: Zhouyang Jia
Applied.
Thanks,
Boris
> ---
> v1->v2:
On Thu, 28 Jun 2018 10:20:11 +0200
Geert Uytterhoeven wrote:
> Using "%4.4X" in the calculation of the buffer size is misleading, as
> the format string literal has no relation to the actual size needed.
> Hence this is fragile w.r.t. future modification.
>
> As this is not a hot path, fix this
On Tue, 3 Jul 2018 08:43:39 +0100
Colin King wrote:
> From: Colin Ian King
>
> Variable is_local is being assigned but is never used hence it is
> redundant and can be removed.
>
> Cleans up clang warning:
> warning: variable 'timeo' set but not used [-Wunused-but-set-variable]
>
> Signed-of
On Wed, 4 Jul 2018 07:46:09 +0100
Colin King wrote:
> From: Colin Ian King
>
> Variable nb_erases is being assigned but is never used hence it is
> redundant and can be removed.
>
> Cleans up clang warning:
> warning: variable 'nb_erases' set but not used [-Wunused-but-set-variable]
>
> Sign
On Wed, 4 Jul 2018 10:57:11 +0200
Alexandre Belloni wrote:
> On 04/07/2018 11:42:25+0300, Tudor Ambarus wrote:
> > Hi, Claudiu,
> >
> > On 06/04/2018 11:46 AM, Claudiu Beznea wrote:
> > > Implement suspend/resume hooks.
> > >
> > > Signed-off-by: Claudiu Beznea
Applied.
Thanks,
Boris
> >
On Fri, 6 Jul 2018 15:05:25 +0200
Benjamin Gaignard wrote:
> The format specifier "%p" can leak kernel addresses.
> Use "%pK" instead.
>
> Signed-off-by: Benjamin Gaignard
Applied.
Thanks,
Boris
> ---
> drivers/mtd/spi-nor/stm32-quadspi.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 d
Hi Sergey,
On Sun, 8 Jul 2018 14:29:22 +0300
Sergey Larin wrote:
> docg4 driver became broken and these patches will make it work again.
I guess you have a platform with a DoC G4 on it. If that's the case, I
might have a few changes I'd need you to test if you don't mind.
Thanks,
Boris
>
On Sun, 8 Jul 2018 14:29:23 +0300
Sergey Larin wrote:
> nand_scan_tail() invokes nand_chip->scan_bbt() at the end, which is not set
> by the driver. Use the default nand_default_bbt() function to avoid NULL
> dereferncing.
Wow! For how long has this driver been broken? The ->scan_bbt() hook
has
On Sun, 8 Jul 2018 14:29:24 +0300
Sergey Larin wrote:
> This fixes WARN() in nand_is_slc().
>
> DoC G4 is 2-bit MLC, so set bits_per_cell value according to this.
What you do here implies "no UBI on docg4". To be honest, I'm pretty
sure there's an FTL in there, which clearly does not make it a
On Sat, 7 Jul 2018 11:03:00 +0200
Jann Horn wrote:
> +cc linux-api
>
> On Sat, Jul 7, 2018 at 10:44 AM Boris Brezillon
> wrote:
> >
> > On Sat, 7 Jul 2018 05:37:22 +0200
> > Jann Horn wrote:
> >
> > > The first checks in mtdchar_read() and
Hi Stephen,
On Mon, 9 Jul 2018 11:51:15 +1000
Stephen Rothwell wrote:
> Hi Boris,
>
> After merging the nand tree, today's linux-next build (x86_64
> allmodconfig) produced this warning:
>
> drivers/mtd/nand/raw/davinci_nand.c: In function 'nand_davinci_hwcontrol':
> drivers/mtd/nand/raw/davin
Hi Arnd,
On Mon, 9 Jul 2018 17:57:02 +0200
Arnd Bergmann wrote:
> Now that we can build this driver everywhere, we run into a couple
> of warnings like:
>
> drivers/mtd/nand/raw/davinci_nand.c: In function 'nand_davinci_correct_4bit':
> drivers/mtd/nand/raw/davinci_nand.c:322:21: error: cast f
Hi Bean,
On Mon, 9 Jul 2018 15:54:11 +
"Bean Huo (beanhuo)" wrote:
> Hi, Boris and Chris
>
> >>
> >> I see 2 solutions to this problem:
> >> 1/ Bean provides us a solution to reliably detect when ECC can be
> >>de-actived and when it can't
> >> 2/ We only ever expose 64 bytes of OOB to
On Mon, 9 Jul 2018 18:31:24 +0200
Boris Brezillon wrote:
> Hi Bean,
>
> On Mon, 9 Jul 2018 15:54:11 +
> "Bean Huo (beanhuo)" wrote:
>
> > Hi, Boris and Chris
> >
> > >>
> > >> I see 2 solutions to this problem:
> > &
+Fabio
Hi Yogesh,
On Wed, 13 Jun 2018 11:38:12 +0530
Yogesh Gaur wrote:
> Some SPI controllers can't write nor->page_size bytes in a single
> step because their TX FIFO is too small.
>
> Allow nor->write() to return a size that is smaller than the requested
> write size to gracefully handle th
On Tue, 10 Jul 2018 11:40:08 +
"Bean Huo (beanhuo)" wrote:
> Hi, Boris
> >>
> >> Okay, I think we already had this discussion, but I'm asking it again.
> >> What are the possible values for that field and what do they mean?
> >
> >Still, it's not clear to me what "Internal ECC level" means
Hi Girish,
On Thu, 5 Jul 2018 15:46:42 -0600
Girish Mahadevan wrote:
> +
> +static int process_data(const struct spi_mem_op *op, struct qcom_qspi *ctrl)
> +{
> + int ret;
> +
> + ctrl->xfer.dir = (op->data.dir == SPI_MEM_DATA_IN) ?
> + QSPI_READ : QSP
red =m here so it can link against the BCMA driver.
>
> Signed-off-by: Arnd Bergmann
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
> i
On Wed, 11 Jul 2018 14:26:58 +0200
Arnd Bergmann wrote:
> Compile-testing this driver on x86 caused a link error:
>
> ERROR: "__phys_to_dma" [drivers/mtd/nand/raw/qcom_nandc.ko] undefined!
>
> The problem here is that the driver attempts to convert the physical
> address into the DMA controller
On Tue, 26 Jun 2018 09:10:05 +0200
Miquel Raynal wrote:
> Hi Martin, Boris,
>
> On Fri, 22 Jun 2018 16:50:25 +0200, Martin Kaiser
> wrote:
>
> > mxcnd_probe_dt is called from mxcnd_probe, which is not marked as __init.
> >
>
> I think this line is just a side note and should be at the end
Hi Andy,
On Tue, 26 Jun 2018 16:18:44 +0300
Andy Shevchenko wrote:
>
> > What is wrong? Some newlines are missing here between the MODULE_ macros,
> > but in my original patch it seems correct.
>
> It should be like
>
> MODULE_FOO(...);
> MODULE_BAR(...);
> MODULE_BAZ(...);
>
> One macro —
on, where dm-verity already checks integrity of the
> block device but this time at the block granularity instead of verifying
> the whole volume.
>
> Skipping this test drastically improves the boot-time.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Quentin Schulz
ag only tell for now whether we should skip
> the CRC check of a volume.
>
> This checks the UBI volume for which we are trying to skip the CRC check
> is static.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Quentin Schulz
Reviewed-by: Boris Brezillon
> ---
> d
>> wrote:
> >>
> >>> 2018-06-25 23:55 GMT+09:00 Boris Brezillon :
> >>>
> >>>> On Mon, 25 Jun 2018 09:50:18 -0500
> >>>> Dinh Nguyen wrote:
> >>>>
> >>>>> On 06/22/2018 10:58 AM, Richar
s a crash.
>
> mxcnd_probe used to be marked as __init, this was removed years ago.
> Remove the __init qualifier from from mxcnd_probe_dt as well.
>
> Fixes: 06f255106923 ("mtd: remove use of __devinit")
> Signed-off-by: Martin Kaiser
Reviewed-by: Boris Brezillon
> ---
On Sun, 24 Jun 2018 00:35:42 +0900
Masahiro Yamada wrote:
> With the special case handling for Blackfin and Metag was removed by
> commit 94e58e0ac312 ("export.h: remove code for prefixing symbols with
> underscore"), VMLINUX_SYMBOL_STR() can be replaced with string literal.
>
> Signed-off-by: M
On Thu, 24 May 2018 13:00:41 +0200
Stefan Agner wrote:
>
> >
> > Note that we're in fact using this patch set in Linux today, but
> > we had to remove the oobsize inference part. Currently we're
> > simply hard coding it to CFG_TVAL_4, but maybe it would be
> > cleaner to add ECC algo as a boar
Hi Benjamin,
On Thu, 24 May 2018 13:30:14 +0200
Benjamin Lindqvist wrote:
> Hi Stefan,
>
> It seems to me that a probe similar to what the BootROM does shouldn't
> be awfully complicated to implement - just cycle through the switch
> cases in case of an ECC error. But I guess that's more of an
On Thu, 24 May 2018 13:09:53 +0200
Stefan Agner wrote:
> On 24.05.2018 10:56, Boris Brezillon wrote:
> > On Thu, 24 May 2018 10:46:27 +0200
> > Stefan Agner wrote:
> >
> >> Hi Boris,
> >>
> >> Thanks for the initial review! One small ques
On Thu, 24 May 2018 13:09:53 +0200
Stefan Agner wrote:
> On 24.05.2018 10:56, Boris Brezillon wrote:
> > On Thu, 24 May 2018 10:46:27 +0200
> > Stefan Agner wrote:
> >
> >> Hi Boris,
> >>
> >> Thanks for the initial review! One small ques
On Thu, 24 May 2018 14:23:56 +0200
Boris Brezillon wrote:
> On Thu, 24 May 2018 13:09:53 +0200
> Stefan Agner wrote:
>
> > On 24.05.2018 10:56, Boris Brezillon wrote:
> > > On Thu, 24 May 2018 10:46:27 +0200
> > > Stefan Agner wrote:
> > >
>
On Sun, 27 May 2018 16:18:32 +0200
Miquel Raynal wrote:
> Hi Stefan,
>
> On Thu, 24 May 2018 14:19:18 +0200, Stefan Agner
> wrote:
>
> > On 24.05.2018 13:53, Boris Brezillon wrote:
> > > Hi Benjamin,
> > >
> > > On Thu, 24 May 201
On Sun, 27 May 2018 17:54:03 +0200
Miquel Raynal wrote:
> Hi Boris,
>
> On Sun, 27 May 2018 17:13:37 +0200, Boris Brezillon
> wrote:
>
> > On Sun, 27 May 2018 16:18:32 +0200
> > Miquel Raynal wrote:
> >
> > > Hi Stefan,
> > >
>
Hi Paul,
On Fri, 11 May 2018 23:29:12 +0200
Paul Cercueil wrote:
> By specifying the properties "mtd-oob-ecc" and "mtd-oob-free", it is
> now possible to specify from devicetree where the ECC data is located
> inside the OOB region.
Why would we want to do that? I mean, ECC/free regions are ECC
On Thu, 10 May 2018 14:28:37 -0700
Jane Wan wrote:
> Per ONFI specification (Rev. 4.0), if all parameter pages have invalid
> CRC values, the bit-wise majority may be used to recover the contents of
> the parameter pages from the parameter page copies present.
>
> Signed-off-by: Jane Wan
> ---
On Sat, 12 May 2018 08:55:40 -0300
Paul Cercueil wrote:
> Hi Boris,
>
> Le 12 mai 2018 02:55, Boris Brezillon a écrit :
> >
> > Hi Paul,
> >
> > On Fri, 11 May 2018 23:29:12 +0200
> > Paul Cercueil wrote:
> >
> > > By specifying
On Sat, 12 May 2018 11:38:26 -0300
Paul Cercueil wrote:
> Le sam. 12 mai 2018 à 10:42, Boris Brezillon
> a écrit :
> > On Sat, 12 May 2018 08:55:40 -0300
> > Paul Cercueil wrote:
> >
> >> Hi Boris,
> >>
> >> Le 12 mai 2018 02:55, Bo
On Sat, 12 May 2018 19:42:49 +0200
Paul Cercueil wrote:
> >> >> My motivation is to get rid of this (move it to devicetree):
> >> >>
> >> >>
> >> https://elixir.bootlin.com/linux/latest/source/arch/mips/jz4740/board-qi_lb60.c#L93
> >>
> >> >> And enable the support of other boards wit
Applied after fixing a few things (see below).
Changed the subject to "mtd: rawnand: use bit-wise majority to recover
the ONFI param page"
On Sun, 13 May 2018 04:30:02 +
"Wan, Jane (Nokia - US/Sunnyvale)" wrote:
> Per ONFI specification (Rev. 4.0), if all parameter pages have invalid CRC
>
link time.
Fix that by making ndelay() an inline function and then defining dummy
ndelay() macro that redirects to the ndelay() function (it's how most
archs do to implement ndelay()).
Fixes: c8ee038bd148 ("m68k: Implement ndelay() based on the existing udelay()
logic")
Signed-off-
On Mon, 14 May 2018 10:00:30 +0200
Geert Uytterhoeven wrote:
> On Tue, May 1, 2018 at 10:00 PM, Sasha Levin
> wrote:
> > On Tue, May 01, 2018 at 03:44:50PM -0400, Theodore Y. Ts'o wrote:
> >>On Tue, May 01, 2018 at 04:38:21PM +, Sasha Levin wrote:
> >>> - A merge window commit spent 50%
On Mon, 14 May 2018 10:29:04 +0200
Geert Uytterhoeven wrote:
> Hi Boris,
>
> On Mon, May 14, 2018 at 10:12 AM, Boris Brezillon
> wrote:
> > On Mon, 14 May 2018 10:00:30 +0200
> > Geert Uytterhoeven wrote:
> >> On Tue, May 1, 2018 at 10:00 PM, Sasha Levin
>
+Fengguang
On Mon, 14 May 2018 10:40:10 +0200
Geert Uytterhoeven wrote:
> Hi Boris,
>
> On Mon, May 14, 2018 at 10:34 AM, Boris Brezillon
> wrote:
> > On Mon, 14 May 2018 10:29:04 +0200
> > Geert Uytterhoeven wrote:
> >> On Mon, May 14, 2018 at 10:1
lease let me
> > > know.
> > >
> > > --
> > >
> > > From: Boris Brezillon
> > >
> > > commit 3057fcef385348fe85173f1b0c824d89f1176f72 upstream.
> > >
> > > NAND chips require a bit of time to take the NA
On Mon, 14 May 2018 12:49:37 +0200
Geert Uytterhoeven wrote:
> The __DIVIDE() macro checks whether it is called with a 32-bit or 64-bit
> dividend, to select the appropriate divide-and-round-up routine.
> As the check uses the ternary operator, the result will always be
> promoted to a type that
On Mon, 14 May 2018 13:32:30 +0200
Geert Uytterhoeven wrote:
> Hi Boris,
>
> On Mon, May 14, 2018 at 1:23 PM, Boris Brezillon
> wrote:
> > On Mon, 14 May 2018 12:49:37 +0200
> > Geert Uytterhoeven wrote:
> >> The __DIVIDE() macro checks whether it
On Mon, 14 May 2018 13:46:07 +0200
Boris Brezillon wrote:
> On Mon, 14 May 2018 13:32:30 +0200
> Geert Uytterhoeven wrote:
>
> > Hi Boris,
> >
> > On Mon, May 14, 2018 at 1:23 PM, Boris Brezillon
> > wrote:
> > > On Mon, 14 May 2018 12:4
On Mon, 14 May 2018 14:00:19 +0200
Geert Uytterhoeven wrote:
> Hi Boris,
>
> On Mon, May 14, 2018 at 1:46 PM, Boris Brezillon
> wrote:
> > On Mon, 14 May 2018 13:32:30 +0200
> > Geert Uytterhoeven wrote:
> >> On Mon, May 14, 2018 at 1:23 PM, Boris Brezillon
On Mon, 18 Jun 2018 09:09:02 +0200
Richard Weinberger wrote:
> Am Freitag, 15. Juni 2018, 03:18:50 CEST schrieb Masahiro Yamada:
> > According to the Denali User's Guide, this IP needs three clocks:
> >
> > - clk: controller core clock
> >
> > - clk_x: bus interface clock
> >
> > - ecc_clk:
On Fri, 15 Jun 2018 10:18:51 +0900
Masahiro Yamada wrote:
> The probe function references &pdev->dev many times. Add 'dev' as
> a shorthand.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
> ---
>
> Changes in v3: None
> Chang
problem for me.
>
> Signed-off-by: Peter Rosin
Reviewed-by: Boris Brezillon
Miquel, can you queue this one to nand/next.
> ---
> drivers/mtd/nand/raw/atmel/nand-controller.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand
Hi Robert,
On Sun, 17 Jun 2018 19:02:03 +0200
Robert Jarzmik wrote:
> As I gathered almost all the required acks, this is an information only post
> before queuing to the PXA tree.
We'll need an immutable branch/tag containing those changes, just in
case other conflicting changes get submitted
Hi Claudiu,
The subject prefix should be "mtd: spi-nor: atmel-quadspi: ". No need
to send a new version just for that, I'll fix it when applying the
patch.
Looks good otherwise. Marek, any objection? If not, can you add your
Acked-by?
Thanks,
Boris
On Mon, 4 Jun 2018 11:46:33 +0300
Claudiu Bez
On Sun, 17 Jun 2018 22:45:59 +0200
Stefan Agner wrote:
> Changes definitly calm down, most noteably probably the changes
> around checking whether a page is empty if the stack reports ECC
> errors.. I verified the code using raw nandwrites with OOB to
> simulate an empty page which has some bits
Hi Stefan,
On Mon, 18 Jun 2018 12:51:52 +0200
Stefan Agner wrote:
> On 18.06.2018 11:58, Boris Brezillon wrote:
> > On Sun, 17 Jun 2018 22:45:59 +0200
> > Stefan Agner wrote:
> >
> >> Changes definitly calm down, most noteably probably the changes
> >
On Mon, 18 Jun 2018 15:05:21 +0200
Miquel Raynal wrote:
> Hi Chris,
>
> On Mon, 18 Jun 2018 16:52:54 +1200, Chris Packham
> wrote:
>
> > Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
> > revision number field of the ONFI parameter page. Rather than rejecting
> > these ou
Hi Martin,
On Sun, 10 Jun 2018 15:31:27 +0200
Martin Kaiser wrote:
> The v21 version of the NAND flash controller contains a Spare Area Size
> Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> spare area size of 218 bytes. The size that is set in this register is
> used by th
Hi Yogesh,
On Mon, 18 Jun 2018 13:32:27 +
Yogesh Narayan Gaur wrote:
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Friday, June 15, 2018 7:26 PM
> To: Yogesh Narayan Gaur ; Fabio Estevam
> ; David Wolfe ;
> dw...@
Yogesh,
On Wed, 30 May 2018 15:14:32 +0200
Frieder Schrempf wrote:
> +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
> +{
> + unsigned long rate = spi->max_speed_hz;
> + int ret, i;
> + u32 map_addr;
> +
> + if (q->selected == spi->chip_select)
> +
On Mon, 18 Jun 2018 21:56:20 +0200
Robert Jarzmik wrote:
> Boris Brezillon writes:
>
> > Hi Robert,
> >
> > On Sun, 17 Jun 2018 19:02:03 +0200
> > Robert Jarzmik wrote:
> >
> >> As I gathered almost all the required acks, this is an information o
Hi Chris,
On Tue, 19 Jun 2018 01:44:24 +
Chris Packham wrote:
> On 19/06/18 12:35, Chris Packham wrote:
> > On 19/06/18 01:15, Miquel Raynal wrote:
> >> Hi Chris,
> >>
> >> On Mon, 18 Jun 2018 16:52:53 +1200, Chris Packham
> >> wrote:
> >>
> >>> Hi,
> >>>
> >>> I'm looking at adding sup
On Tue, 19 Jun 2018 17:31:24 +1200
Chris Packham wrote:
> Add ONFI_FEATURE_ON_DIE_ECC to the set/get features list for Micron
> NAND flash.
>
Fixes: 789157e41a06 ("mtd: rawnand: allow vendors to declare (un)supported
features")
Cc:
No need to send a new version, I'll add that when queuing the
On Mon, 18 Jun 2018 22:41:03 +0200
Martin Kaiser wrote:
> The v21 version of the NAND flash controller contains a Spare Area Size
> Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> spare area size of 218 bytes. The size that is set in this register is
> used by the controller
On Tue, 19 Jun 2018 17:31:20 +1200
Chris Packham wrote:
> From the controllers point of view this is the same as no or
> software only ECC.
>
> Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
> ---
> Changes in v2:
> - New
>
> drivers/mtd/nand/raw/mar
On Tue, 19 Jun 2018 17:31:21 +1200
Chris Packham wrote:
> This is called after the ONFI parameter page checksum is verified
> and allows us to override the contents of the parameter page.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Chris Packham
Reviewed-by:
Could you add a comment repeating what you have in your commit message
here?
With this addressed
Reviewed-by: Boris Brezillon
> + if (le16_to_cpu(p->revision) == 0)
> + p->revision = cpu_to_le16(1 << 1);
> +}
> +
> const struct nand_manufacturer_ops micron_nand_manuf_ops = {
> .init = micron_nand_init,
> + .fixup_onfi_param_page = micron_fixup_onfi_param_page,
> };
On Tue, 19 Jun 2018 17:31:25 +1200
Chris Packham wrote:
> Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
> per 512 bytes. Add support for this combination.
>
> Signed-off-by: Chris Packham
> ---
> This seems deceptively easy so I've probably missed something. I have
> tested w
Hi Yogesh,
Could you please use a mailer that is quoting things correctly. I have
a hard time differentiating your replies from mine.
On Tue, 19 Jun 2018 07:10:37 +
Yogesh Narayan Gaur wrote:
> Let us take below layout of memory address space map.
> QuadSPI Controller can access range from
On Tue, 19 Jun 2018 08:31:25 +
Yogesh Narayan Gaur wrote:
> >
> > Could you please use a mailer that is quoting things correctly. I
> > have a hard time differentiating your replies from mine.
>
> Sorry for this, have changed my mailer settings.
Thanks for doing. It's still not perfect,
Hi Masahiro,
On Fri, 15 Jun 2018 10:18:50 +0900
Masahiro Yamada wrote:
> According to the Denali User's Guide, this IP needs three clocks:
>
> - clk: controller core clock
>
> - clk_x: bus interface clock
>
> - ecc_clk: clock at which ECC circuitry is run
>
> Currently, denali_dt.c requir
On Wed, 20 Jun 2018 17:05:42 +1200
Chris Packham wrote:
> This is called after the ONFI parameter page checksum is verified
> and allows us to override the contents of the parameter page.
>
> Suggested-by: Boris Brezillon
> Reviewed-by: Boris Brezillon
Ditto.
> Signed-off
ail.com
> >>
> >> Signed-off-by: Kees Cook
> >> ---
> >> v3: fix r_bytes to whole-word size
> >> v2: switch to fixed-size stack array
> >> ---
> >> lib/Makefile | 1 +
> >> lib/bch.c| 23 +++----
> >
On Wed, 20 Jun 2018 17:05:44 +1200
Chris Packham wrote:
> Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
> per 512 bytes. Add support for this combination.
>
> Signed-off-by: Chris Packham
> ---
> Changes in v2:
> - New
> Changes in v3:
> - Handle reporting of corrected errors
Hi Chris,
On Wed, 20 Jun 2018 17:05:41 +1200
Chris Packham wrote:
> From the controllers point of view this is the same as no or
> software only ECC.
>
> Reviewed-by: Boris Brezillon
I'm nitpicking, but we usually put the R-b/A-b tags after the author
SoB.
> Signed-o
gt; Reviewed-by: Boris Brezillon
> Signed-off-by: Chris Packham
> ---
> This is now qualified on vendor == MICRON. I haven't qualified this
> based on specific chips the ABAFA (id=d1) and ABBFA (id=a1) variants are
> documented to have this behaviour.
>
> Changes in v2:
>
On Tue, 19 Jun 2018 17:31:24 +1200
Chris Packham wrote:
> Add ONFI_FEATURE_ON_DIE_ECC to the set/get features list for Micron
> NAND flash.
>
> Signed-off-by: Chris Packham
Queued to master (AKA mtd/fixes).
Thanks,
Boris
> ---
> Changes in v2:
> - New
>
> drivers/mtd/nand/raw/nand_micron.
On Tue, 19 Jun 2018 11:07:41 +0200
Miquel Raynal wrote:
> On Mon, 18 Jun 2018 22:41:03 +0200, Martin Kaiser
> wrote:
>
> > The v21 version of the NAND flash controller contains a Spare Area Size
> > Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> > spare area size of 218 b
On Wed, 13 Jun 2018 23:23:32 +0200
Richard Weinberger wrote:
> When multiple PEBs are used for a fastmap, found_pebs
> can be wrong and the assert triggers.
>
> The current approach is broken in two ways:
> 1. The "continue" in list_for_each_entry() over all fastmap PEBs
>misses the counter
On Wed, 13 Jun 2018 23:23:31 +0200
Richard Weinberger wrote:
> PEB numbers can be used as indices, make sure that they
> are within bounds.
>
> Signed-off-by: Richard Weinberger
> ---
> drivers/mtd/ubi/fastmap.c | 71
> ++-
> 1 file changed, 58 inse
Hi Janusz,
On Sat, 26 May 2018 00:20:45 +0200
Janusz Krzysztofik wrote:
> Now as the Amstrad Delta board provides GPIO lookup tables, switch from
> GPIO numbers to GPIO descriptors and use the table to locate required
> GPIO pins.
>
> Declare static variables for storing GPIO descriptors and re
Hi Yogesh,
On Wed, 30 May 2018 13:50:51 +
Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> Thanks for migrating the fsl-quadspi.c driver on the new SPI
> framework. This patch is using dynamic LUT approach to create the LUT
> at run time instead of fixed static LUT as being used in current
> dr
Hi Frieder,
On Wed, 30 May 2018 15:14:30 +0200
Frieder Schrempf wrote:
> When porting (Q)SPI controller drivers from the MTD layer to the SPI
> layer, the naming scheme for the memory devices changes. To be able
> to keep compatibility with the old drivers naming scheme, a function
> is added to
Hi Frieder,
On Wed, 30 May 2018 15:14:32 +0200
Frieder Schrempf wrote:
> +
> +static const char *fsl_qspi_get_name(struct spi_mem *mem)
> +{
> + struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> + struct device *dev = &mem->spi->dev;
> + const char *name;
> +
> +
On Wed, 30 May 2018 15:14:33 +0200
Frieder Schrempf wrote:
> Move the documentation of the old SPI NOR driver to the place of the new
> SPI memory interface based driver and adjust the content to reflect the
> new drivers settings.
Maybe it's better to do that in 2 steps so that people can easil
On Wed, 30 May 2018 15:14:34 +0200
Frieder Schrempf wrote:
> The FSL QSPI driver was moved to the SPI framework and it now
> acts as a SPI controller. Therefore the subnodes need to set
> spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
We should try to keep the current behavior
On Wed, 30 May 2018 19:43:09 +0200
Janusz Krzysztofik wrote:
> On Wednesday, May 30, 2018 11:05:00 AM CEST Boris Brezillon wrote:
> > Hi Janusz,
>
> Hi Boris,
>
> > On Sat, 26 May 2018 00:20:45 +0200
> > Janusz Krzysztofik wrote:
> > > ...
> >
On Thu, 31 May 2018 19:54:08 +0200
Stefan Agner wrote:
> >> +
> >> + mtd->dev.parent = &pdev->dev;
> >> + mtd->name = "tegra_nand";
> >
> > I just figured it was undocumented (yet) but you could have a label
> > string property in your nand DT node that tells you the name of the
> > MTD devi
On Fri, 1 Jun 2018 00:16:32 +0200
Stefan Agner wrote:
> Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
>
> Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nand_base.c | 1 +
> include/linux/mtd/rawnand.h | 1 +
>
y: Stefan Agner
Reviewed-by: Boris Brezillon
> ---
> Documentation/devicetree/bindings/mtd/nand.txt | 4
> drivers/mtd/nand/raw/nand_base.c | 3 +++
> include/linux/mtd/rawnand.h| 6 ++
> 3 files changed, 13 insertions(+)
>
> diff --git
ames = "nand";
> + resets = <&tegra_car 13>;
> + reset-names = "nand";
> +
> + nand-chip@0 {
nand@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-bus-width = <8>;
> + nand-on-flash-bbt;
> + nand-ecc-algo = "bch";
> + nand-ecc-strength = <8>;
> + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
> + };
> + };
With this addressed,
Reviewed-by: Boris Brezillon
On Fri, 1 Jun 2018 09:26:00 +0200
Boris Brezillon wrote:
> On Fri, 1 Jun 2018 00:16:32 +0200
> Stefan Agner wrote:
>
> > Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
> >
> > Signed-off-by: Stefan Agner
>
> Reviewed-by: Boris Brezillon
>
On Fri, 01 Jun 2018 15:34:33 +0200
Stefan Agner wrote:
> On 01.06.2018 11:25, Boris Brezillon wrote:
> > On Fri, 1 Jun 2018 09:26:00 +0200
> > Boris Brezillon wrote:
> >
> >> On Fri, 1 Jun 2018 00:16:32 +0200
> >> Stefan Agner wrote:
> >>
>
> See https://lkml.org/lkml/2018/5/30/176 for example case.
>
> Signed-off-by: Janusz Krzysztofik
> ---
> If accepted, please add
> Suggested-by: Boris Brezillon
> if Boris doesn't mind.
>
> Thanks,
> Janusz
>
> drivers/gpio/gpiolib.c
Hi Miquel,
On Tue, 3 Jul 2018 23:59:58 +0200
Miquel Raynal wrote:
> In order to remove the limitation that forbids dynamic allocation in
> nand_scan_ident(), we must create a path that will be the same for all
> controller drivers. The idea is to use nand_scan() instead of the widely
> implemen
On Tue, 3 Jul 2018 23:59:59 +0200
Miquel Raynal wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_
See https://lkml.org/lkml/2018/5/30/176 for example case.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Janusz Krzysztofik
> Reviewed-by: Boris Brezillon
> ---
> Changelog
> v2: fix typo (latar -> later) - thanks Boris and Andy for catching this
>
> I'
On Wed, 4 Jul 2018 08:29:39 +
Wei Yongjun wrote:
> Add the missing unlock before return from function
> spinand_mtd_(read|write) in the error handling case.
>
> Fixes: c898e0526fb6 ("mtd: nand: Add core infrastructure to support SPI
> NANDs")
> Signed-off-by: Wei Yongjun
> ---
> drivers/m
; Signed-off-by: Wei Yongjun
Acked-by: Boris Brezillon
> ---
> drivers/mtd/nand/spi/core.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> index 17d207a..011683e 100644
> --- a/drivers
Hi Frieder,
On Thu, 5 Jul 2018 13:14:57 +0200
Frieder Schrempf wrote:
> When porting (Q)SPI controller drivers from the MTD layer to the SPI
> layer, the naming scheme for the memory devices changes. To be able
> to keep compatibility with the old drivers naming scheme, a function
> is added to
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