On Tue, 19 Jun 2018 17:31:25 +1200 Chris Packham <chris.pack...@alliedtelesis.co.nz> wrote:
> Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits > per 512 bytes. Add support for this combination. > > Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> > --- > This seems deceptively easy so I've probably missed something. I have > tested with running some of the ubifs stress tests from mtd-utils and > things seem OK. > > Changes in v2: > - New > > drivers/mtd/nand/raw/nand_micron.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/mtd/nand/raw/nand_micron.c > b/drivers/mtd/nand/raw/nand_micron.c > index d1e8f57544a0..2164dd112f5c 100644 > --- a/drivers/mtd/nand/raw/nand_micron.c > +++ b/drivers/mtd/nand/raw/nand_micron.c > @@ -240,9 +240,9 @@ static int micron_supports_on_die_ecc(struct nand_chip > *chip) > > /* > * Some Micron NANDs have an on-die ECC of 4/512, some other > - * 8/512. We only support the former. > + * 8/512. > */ > - if (chip->ecc_strength_ds != 4) > + if (chip->ecc_strength_ds != 4 && chip->ecc_strength_ds != 8) > return MICRON_ON_DIE_UNSUPPORTED; I remember that chips with 8bits/512bytes on-die ECC had an extra command to query a more precise number of bitflips (see this discussion [1]). It's probably worth implementing that, since those chips are more likely to have bitflips than the 4bit/512 versions, and you don't want to move the data around as soon as you have one bitflip. > > return MICRON_ON_DIE_SUPPORTED; > @@ -274,9 +274,9 @@ static int micron_nand_init(struct nand_chip *chip) > return -EINVAL; > } > > - chip->ecc.bytes = 8; > + chip->ecc.bytes = chip->ecc_strength_ds * 2; > chip->ecc.size = 512; > - chip->ecc.strength = 4; > + chip->ecc.strength = chip->ecc_strength_ds; > chip->ecc.algo = NAND_ECC_BCH; > chip->ecc.read_page = micron_nand_read_page_on_die_ecc; > chip->ecc.write_page = micron_nand_write_page_on_die_ecc; [1]http://lists.infradead.org/pipermail/linux-mtd/2017-March/072974.html
