This serie adds the initial support for the Marvell BG2-Q DMP (part of the
Berlin family). SoC has nodes for cpu, l2 cache controller, interrupt
controllers, local timer, apb timers and uarts for now.
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
Antoine Ténart (2
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/berlin2q-dmp.dts | 32
2 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/berlin2q-dmp.dts
diff --git a/arch/arm/boot/dts
Signed-off-by: Antoine Ténart
Signed-off-by: Alexandre Belloni
---
Documentation/arm/Marvell/README | 5 +
.../devicetree/bindings/arm/marvell,berlin.txt | 1 +
arch/arm/boot/dts/berlin2q.dtsi| 167 +
3 files changed, 173
On 12/03/2014 12:20, Arnd Bergmann wrote:
On Wednesday 12 March 2014 12:06:04 Antoine Ténart wrote:
+
+ soc {
+ apb@fc {
+ uart0: uart@9000 {
+ status = "
n the bg2q.
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Hi Sebastian,
On 13/03/2014 10:51, Sebastian Hesselbarth wrote:
On 03/12/2014 11:35 AM, Alexandre Belloni wrote:
On 12/03/2014 at 12:06:02 +0100, Antoine Ténart wrote :
This serie adds the initial support for the Marvell BG2-Q DMP (part
of the
Berlin family). SoC has nodes for cpu, l2 cache
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/berlin2q.dtsi
Adds basic informations about the Armada 1500 Pro in the Berlin family of the
Marvell ARM SoC documentation and the Armada 1500 Pro SoC compatible in the
related device tree documentation.
Signed-off-by: Antoine Ténart
---
Documentation/arm/Marvell/README | 5
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/berlin2q-marvell-dm
- moved documentation changes into a single patch
- fixed documentation typo
Antoine Ténart (3):
ARM: dts: berlin2q: add the Marvell Armada 1500 pro
ARM: berlin2q: add the Marvell Armada 1500 pro in the documentation
ARM: dts: berlin2q: add the Marvell BG2-Q DMP device tree
Sebastian,
On 14/03/2014 10:31, Sebastian Hesselbarth wrote:
On 03/13/2014 03:06 PM, Antoine Ténart wrote:
+clocks {
+#address-cells = <0>;
+#size-cells = <0>;
+
+smclk: sysmgr-clock {
+compatible = "fixed-clock";
+
Signed-off-by: Antoine Ténart
---
Documentation/arm/Marvell/README | 5 +
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 1 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/berlin2q.dtsi
- updated the memory size
- added more information in commit logs
- shorted nodes by address
- fixed clocks cells config
- renamed the Marvell BG2-Q DMP device tree
- moved documentation changes into a single patch
- fixed documentation typo
Antoi
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/berlin2q-marvell-dm
lock-div = <3>;
+ };
Can you please name it as twdclk to avoid confusion? On Berlin, sysclk is
another
clk rather than the clk for twd.
Sure, I'll change the name and send a v4.
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://fre
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/berlin2q-marvell-dm
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/berlin2q.dtsi
Signed-off-by: Antoine Ténart
---
Documentation/arm/Marvell/README | 5 +
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 1 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index
more information in commit logs
- shorted nodes by address
- fixed clocks cells config
- renamed the Marvell BG2-Q DMP device tree
- moved documentation changes into a single patch
- fixed documentation typo
Antoine Ténart (3):
ARM: dts: berlin2q: add the
: Antoine Ténart
Also tested on the BG2Q,
Tested-by: Antoine Ténart
---
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Russell King
Cc: Antoine Tenart
Cc: Alexandre Belloni
Cc: devicet...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc
.
Signed-off-by: Sebastian Hesselbarth
Acked-by: Antoine Ténart
Also tested on the BG2Q,
Tested-by: Antoine Ténart
---
Cc: Russell King
Cc: Antoine Tenart
Cc: Alexandre Belloni
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm/mach-berlin/Kconfig | 1
Signed-off-by: Antoine Ténart
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 333f4aea3029..a9e42a2dbc99 100644
--- a/Documentation
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2.dtsi | 1 +
arch/arm/boot/dts/berlin2q.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 4d85312dc17a..596f6bd07677 100644
--- a/arch/arm/boot/dts/berlin2
Get rid of the smp ops in the machine descriptor and select the cpu
enable method in the device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/mach-berlin/berlin.c | 1 -
arch/arm/mach-berlin/common.h | 2 --
arch/arm/mach-berlin/platsmp.c | 3 ++-
3 files changed, 2 insertions(+), 4
ch [2]
rebased on top of linux-next.
Tested on the Berlin BG2Q.
[1] https://patchwork.kernel.org/patch/3399311/
[2] https://github.com/shesselba/linux-berlin/tree/topic/smp-bg2-bg2q
Antoine Ténart (3):
ARM: berlin: use CPU_METHOD_OF_DECLARE for smp
ARM: dts: document the berlin enable-m
Jisheng,
On 03/04/2014 10:22, Jisheng Zhang wrote:
Hi,
On Thu, 3 Apr 2014 01:08:15 -0700
Antoine Ténart wrote:
Signed-off-by: Antoine Ténart
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm
On 03/04/2014 10:54, Antoine Ténart wrote:
Jisheng,
On 03/04/2014 10:22, Jisheng Zhang wrote:
Hi,
On Thu, 3 Apr 2014 01:08:15 -0700
Antoine Ténart wrote:
Signed-off-by: Antoine Ténart
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 ++
1 file changed, 2 insertions(+)
diff
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart
---
.../devicetree/bindings/phy/berlin-sata-phy.txt| 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree
registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: Antoine Ténart
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-berlin-sata.c
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart
---
.../devicetree/bindings/ata/ahci-platform.txt | 37 ++
1 file changed, 37 insertions(+)
diff --git a
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b
-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the port_map mask is computed automatically when using
this.
Signed-off-by: Antoine Ténart
---
drivers/ata/ahci.h | 3 +-
drivers/ata
This patch moves force_port_map and mask_port_map into the
ahci_host_priv structure. This allows to modify them into the AHCI
framework. This is needed by the new dt bindings representing ports as
the port_map mask is computed automatically.
Signed-off-by: Antoine Ténart
---
drivers/ata/ahci.h
The ahci_platform driver is a generic driver using the libahci_platform
functions. Add a generic compatible to avoid having an endless list of
compatibles with no differences for the same driver.
Signed-off-by: Antoine Ténart
---
drivers/ata/ahci_platform.c | 2 ++
1 file changed, 2 insertions
AHCI driver
- removed BG2 / BG2CD nodes
Antoine Ténart (8):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: libahci_platform: move port_map parameters into the AHCI
structure
ata: libahci: allow to use multiple PHYs
ata: ahci
Hi,
On Fri, Jul 18, 2014 at 03:17:45PM +0200, Lothar Waßmann wrote:
> Antoine Ténart wrote:
> > diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
> > index db9b90d876dd..2c2439b4101d 100644
> > --- a/drivers/ata/libahci_platform.c
Hi,
On Fri, Jul 18, 2014 at 09:47:30AM -0400, Tejun Heo wrote:
> On Fri, Jul 18, 2014 at 02:30:02PM +0200, Antoine Ténart wrote:
> > @@ -321,6 +321,8 @@ struct ahci_host_priv {
> > u32 cap;/* cap to use */
> > u32 ca
Hi,
On Fri, Jul 18, 2014 at 09:27:28PM +0400, Sergei Shtylyov wrote:
> On 07/18/2014 04:30 PM, Antoine Ténart wrote:
>
> >diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
> >b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
> >new f
y we still have a 1:1 way to map ports <-> phys if
> we want to do something with phys on a per port basis in the future.
>
> Note please also add a check that reg < nports so that we don't use
> the array out of bounds if there is an error in the dts.
Ok. I'll
The BG2 has an AHCI SATA controller. Add the corresponding node
in its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 56a1af2f1052
Add support for the Berlin SoCs AHCI SATA controller allowing to
interface with devices like external hard drives.
Signed-off-by: Antoine Ténart
---
drivers/ata/Kconfig | 9 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_berlin.c | 175
This series adds the support for Berlin SoCs AHCI controllers. The
controller allows to use the SATA host interface and, for example, the
eSATA port on the BG2Q.
Also enable the eSATA interface on the BG2Q DMP.
Tested on the BG2Q DMP.
Antoine Ténart (6):
ata: ahci: add AHCI support for Berlin
The BG2CD has an AHCI SATA controller. Add the corresponding node
in its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2cd.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index
The BG2Q has an AHCI SATA controller. Add the corresponding node
in its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
The berlin-achi driver allows Berlin SoCs to support their AHCI SATA controller.
Add the compatible to the device tree bindings documentation.
Signed-off-by: Antoine Ténart
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Linus,
On Tue, Apr 22, 2014 at 02:52:10PM +0200, Linus Walleij wrote:
> On Fri, Apr 11, 2014 at 3:35 PM, Sebastian Hesselbarth
> wrote:
> > On 04/11/2014 02:37 PM, Antoine Ténart wrote:
> >> On Fri, Apr 11, 2014 at 11:03:48AM +0200, Sebastian Hesselbarth wrote:
> &g
Linus,
On Tue, Apr 22, 2014 at 02:48:04PM +0200, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 3:07 PM, Antoine Ténart
> wrote:
>
> > When using a group only pinctrl driver, which does not have any
> > information on the pins it is useless to define a get_group_pins
&g
Hi,
On Tue, Apr 22, 2014 at 06:54:27PM +0200, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Tuesday, April 22, 2014 05:38:20 PM Antoine Ténart wrote:
[…]
> > +static struct platform_driver ahci_berlin_driver = {
> > + .probe = ahci_berlin_probe,
> > + .re
Sebastian,
On Tue, Apr 22, 2014 at 07:20:52PM +0200, Sebastian Hesselbarth wrote:
> On 04/22/2014 05:38 PM, Antoine Ténart wrote:
[…]
> > +static inline void ahci_berlin_reg_set(void __iomem *reg, u32 val)
> > +{
> > + writel(val, reg);
> > +}
>
> Antoine,
Rob,
On Tue, Apr 22, 2014 at 01:54:33PM -0500, Rob Herring wrote:
> On Tue, Apr 22, 2014 at 1:47 PM, Rob Herring wrote:
> > On Tue, Apr 22, 2014 at 10:38 AM, Antoine Ténart
> > wrote:
> >> Add support for the Berlin SoCs AHCI SATA controller allowing to
> >> int
Rob,
On Tue, Apr 22, 2014 at 01:47:43PM -0500, Rob Herring wrote:
> On Tue, Apr 22, 2014 at 10:38 AM, Antoine Ténart
> wrote:
[…]
> > +static inline void ahci_berlin_reg_clear_set(void __iomem *reg, u32
> > clear_val,
> > +
Jisheng,
On Wed, Apr 23, 2014 at 10:45:39AM +0800, Jisheng Zhang wrote:
> On Tue, 22 Apr 2014 08:38:24 -0700
> Antoine Ténart wrote:
>
> > The BG2 has an AHCI SATA controller. Add the corresponding node
> > in its device tree.
>
> The AHCI IP of BG2 is different with
Sebastian,
On Tue, Apr 22, 2014 at 07:35:27PM +0200, Sebastian Hesselbarth wrote:
> On 04/22/2014 10:27 AM, Antoine Ténart wrote:
[…]
> > + sdhci0: sdhci@ab {
> > + compatible = "mrvl,pxav3-mmc";
> > +
Signed-off-by: Antoine Ténart
---
arch/arm/mach-berlin/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index d3c5f14dc142..9c2b569e54ba 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -4,6
Add the pin-controller driver for the Berlin BG2 SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.
Signed-off-by: Antoine Ténart
---
drivers/pinctrl/berlin/Kconfig | 4 +
drivers/pinctrl/berlin/Makefile | 1 +
drivers/pinctrl/berlin/berlin
BG2CD function definitions
Antoine Ténart (7):
pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs
pinctrl: berlin: add the BG2Q pinctrl driver
pinctrl: berlin: add the BG2 pinctrl driver
pinctrl: berlin: add the BG2CD pinctrl driver
ARM: berlin: add the pinctrl dependency fo
The uart0 pinmux configuration is in the dtsi because uart0 will always
use uart0-pmux to work, no other possibility. Same thing for uart1.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2.dtsi | 24
arch/arm/boot/dts/berlin2cd.dtsi | 17
Add the pin-controller driver for the Berlin BG2CD SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.
Signed-off-by: Antoine Ténart
---
drivers/pinctrl/berlin/Kconfig| 4 +
drivers/pinctrl/berlin/Makefile | 1 +
drivers/pinctrl/berlin
Add the documentation related to the Berlin pin-controller driver and
explain how to configure this group based controller.
Signed-off-by: Antoine Ténart
---
.../bindings/pinctrl/marvell,berlin-pinctrl.txt| 44 ++
1 file changed, 44 insertions(+)
create mode 100644
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.
Signed-off-by: Antoine Ténart
---
drivers/pinctrl/berlin/Kconfig | 4 +
drivers/pinctrl/berlin/Makefile | 1 +
drivers/pinctrl/berlin
GSM12 UART0_TXIrDA0_TXGPIO10
So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &= ff3f.
Signed-off-by: Antoine Ténart
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile| 1 +
drivers
Sebastian,
On Wed, Apr 23, 2014 at 07:26:23PM +0200, Sebastian Hesselbarth wrote:
> On 04/22/2014 10:27 AM, Antoine Ténart wrote:
> > Enable the SD Card reader and the internal eMMC on the Berlin BG2Q DMP
> > using two of the SDHCI nodes of the Berlin BG2Q.
> >
> > Si
toine
> + };
> +
> apb@fc0000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> --
> 1.9.1
>
>
> ___
> linux-arm-kernel mailing list
> li
clocks = <&syspll>;
> + #clock-cells = <0>;
> + reg = <0xea0240 4>;
> + };
> +
> apb@fc {
> compatible = "simple-bus";
>
Hi Jisheng,
On Thu, Apr 24, 2014 at 05:50:41PM +0800, Jisheng Zhang wrote:
> Hi Antoine,
>
> On Tue, 22 Apr 2014 08:38:20 -0700
> Antoine Ténart wrote:
>
> > + /* CT timing fix */
> > + ahci_berlin_reg_set(ctrl_reg + PORT_V
On Tue, Jul 29, 2014 at 10:34:38AM -0400, Tejun Heo wrote:
> On Tue, Jul 29, 2014 at 09:20:47AM +0200, Antoine Ténart wrote:
> > The current implementation of the libahci does not allow to use multiple
> > PHYs. This patch adds the support of multiple PHYs by the libahci while
>
On Tue, Jul 29, 2014 at 10:40:42AM -0400, Tejun Heo wrote:
> On Thu, Jul 24, 2014 at 11:17:25AM +0200, Antoine Ténart wrote:
> > @@ -321,6 +321,8 @@ struct ahci_host_priv {
> > u32 cap;/* cap to use */
> > u32 cap2;
On Wed, Jul 30, 2014 at 11:35:26AM -0400, Tejun Heo wrote:
> On Wed, Jul 30, 2014 at 10:20:38AM +0200, Antoine Ténart wrote:
> > How do you want me to send the series? There is two conflicts when
> > applying to libata/for-3.17:
> > - patch 4/8: it takes into account a patch n
registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: Antoine Ténart
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-berlin-sata.c
flags have been
removed from the ahci_platform_init_host() function, and inputs in the
ahci_host_priv structure are now directly filled.
Signed-off-by: Antoine Ténart
---
drivers/ata/ahci.h | 10 ++
drivers/ata/ahci_da850.c | 3 +--
drivers/ata/ahci_imx.c | 3
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart
---
.../devicetree/bindings/ata/ahci-platform.txt | 41 ++
1 file changed, 41 insertions(+)
diff --git a
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart
---
.../devicetree/bindings/phy/berlin-sata-phy.txt| 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree
nd removed the 'force-port-map' property
- made the drivers a bit less magic :)
- wrote a function to select and configure registers in the
AHCI driver
- removed BG2 / BG2CD nodes
Antoine Ténart (8):
phy: add a driver for the Berlin SATA PHY
Documentation:
The ahci_platform driver is a generic driver using the libahci_platform
functions. Add a generic compatible to avoid having an endless list of
compatibles with no differences for the same driver.
Signed-off-by: Antoine Ténart
---
drivers/ata/ahci_platform.c | 2 ++
1 file changed, 2 insertions
-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the port_map mask is computed automatically when using
this.
Signed-off-by: Antoine Ténart
Acked-by: Hans de Goede
Acked-by: Kishon Vijay Abraham I
---
drivers
ilulre. Can you please look into it?
Sorry for that... I just fixed it. I'll test and send a new version.
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm
-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the port_map mask is computed automatically when using
this.
Signed-off-by: Antoine Ténart
Acked-by: Hans de Goede
Acked-by: Kishon Vijay Abraham I
---
drivers
flags have been
removed from the ahci_platform_init_host() function, and inputs in the
ahci_host_priv structure are now directly filed.
Signed-off-by: Antoine Ténart
---
drivers/ata/acard-ahci.c | 2 +-
drivers/ata/ahci.c | 3 +--
drivers/ata/ahci.h | 10
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart
---
.../devicetree/bindings/phy/berlin-sata-phy.txt| 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree
registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: Antoine Ténart
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-berlin-sata.c
onfigure registers in the
AHCI driver
- removed BG2 / BG2CD nodes
Antoine Ténart (8):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: libahci_platform: move port_map parameters into the AHCI
structure
ata: libahci: allow t
The ahci_platform driver is a generic driver using the libahci_platform
functions. Add a generic compatible to avoid having an endless list of
compatibles with no differences for the same driver.
Signed-off-by: Antoine Ténart
---
drivers/ata/ahci_platform.c | 2 ++
1 file changed, 2 insertions
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart
---
.../devicetree/bindings/ata/ahci-platform.txt | 41 ++
1 file changed, 41 insertions(+)
diff --git a
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b
Linus,
On Fri, May 16, 2014 at 03:35:48PM +0200, Linus Walleij wrote:
> On Mon, May 5, 2014 at 7:27 AM, Antoine Ténart
> wrote:
>
> > Add the documentation related to the Berlin pin-controller driver and
> > explain how to configure this group based controller.
> >
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Only enable the first port, the BG2Q DMP does not support the second one.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm
The libahci now allows to use multiple PHYs and to represent each port
as a sub-node. Add these bindings to the documentation.
Signed-off-by: Antoine Ténart
---
.../devicetree/bindings/ata/ahci-platform.txt | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff
The BG2Q has an AHCI SATA controller. Add the corresponding nodes
(AHCI, PHY) into its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot
-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the default port_map is computed automatically when using
this.
Signed-off-by: Antoine Ténart
---
drivers/ata/Kconfig| 1 +
drivers/ata/ahci.h
The Marvell Berlin AHCI has all his specific in the PHY driver. It then
only need to use the libahci functions to work properly.
Add its compatible into the libahci_platform driver.
Signed-off-by: Antoine Ténart
---
drivers/ata/ahci_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git
select and configure registers in the
AHCI driver
- removed BG2 / BG2CD nodes
Antoine Ténart (7):
phy: add a driver for the Berlin SATA PHY
Documentation: bindings: add the Berlin SATA PHY
ata: libahci: allow to use multiple PHYs
ata: ahci_platform: add the Marvell B
registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: Antoine Ténart
---
drivers/phy/Kconfig | 5 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-berlin-sata.c | 230
The Berlin SATA PHY drives the PHY related to the SATA interface. Add
the corresponding documentation.
Signed-off-by: Antoine Ténart
---
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree
On Tue, May 20, 2014 at 11:11:17AM +0200, Sebastian Hesselbarth wrote:
> On 05/20/2014 11:04 AM, Antoine Ténart wrote:
> >+#define HOST_VSA_ADDR 0x0
> >+#define HOST_VSA_DATA 0x4
> >+#define PORT_VSR_ADDR 0x78
> >+#define P
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