ls1046afrwy board is based on nxp ls1046a SoC.
Board support's 4GB ddr memory, i2c, microSD card,
serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
usb 3.0 and serdes interface to support two x1gen3 pcie interface.
Signed-off-by: Vabhav Sharma
Signed-off-by: Pramod Kumar
---
Dear Friend,
How are you I hope you are very fine with your entire family? If so glory be to
Almighty God.
I'm happy to inform you about my success in getting those funds transferred
under the cooperation of a new partner from GREECE, Presently i'm in GREECE
for a better treatment and buildi
Hi Thomas, Jason, Marc,
This is a set of miscellaneous cleanups and improvements for the Renesas
R-Mobile APE6 and R-Car interrupt controller for external interrupts
(IRQC/INTC-EX) driver.
Changes compared to v1:
- Add Reviewed-by,
- s/devm_kzalloc/kzalloc/ in patch description, rewor
add micron nor flash support for ls1046a frwy board.
Signed-off-by: Ashish Kumar
Signed-off-by: Pramod Kumar
---
.../boot/dts/freescale/fsl-ls1046a-frwy.dts| 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.d
There is no need to print error messages if kzalloc() or
ioremap_nocache() fail, as the memory allocation core already takes care
of that.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by,
- s/devm_kzalloc/kzalloc/ in patch description, reword.
---
drive
Simplify error handling by converting the driver to use managed
allocations and initializations.
Note that platform_get_resource() and ioremap_nocache() are combined in
devm_platform_ioremap_resource().
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by.
---
The probe function uses "&pdev->dev" a lot, hence add a shorthand for
that.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by,
---
drivers/irqchip/irq-renesas-irqc.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --
Add "fsl,ls1046a-frwy" bindings for ls1046afrwy board based on ls1046a SoC
Signed-off-by: Vabhav Sharma
Signed-off-by: Pramod Kumar
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/
if saa7164_proc_create() fails, saa7164_fini() will trigger a warning,
name 'saa7164'
WARNING: CPU: 1 PID: 6311 at fs/proc/generic.c:672 remove_proc_entry+0x1e8/0x3a0
? remove_proc_entry+0x1e8/0x3a0
? try_stop_module+0x7b/0x240
? proc_readdir+0x70/0x70
? rcu_read_lock_sched_held+0xd7/0x100
Use the preferred KMEM_CACHE helper for brevity.
Signed-off-by: Peng Wang
---
block/blk-core.c | 3 +--
block/blk-ioc.c | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/block/blk-core.c b/block/blk-core.c
index 1bf83a0df0f6..841bf0b12755 100644
--- a/block/blk-core.c
+++
On 27/05/19 12:37 PM, Brian Masney wrote:
> On Sun, May 26, 2019 at 03:58:19PM -0400, Brian Masney wrote:
>> I attached a patch that shows how I was able to determine what had
>> already claimed the host.
> On Mon, May 27, 2019 at 10:48:24AM +0300, Adrian Hunter wrote:
>> This is because SDHCI is u
For each page scheduled for compaction (e. g. by z3fold_free()),
try to apply inter-page compaction before running the traditional/
existing intra-page compaction. That means, if the page has only one
buddy, we treat that buddy as a new object that we aim to place into
an existing z3fold page. If s
We've had minimal OCP softreset support in ti-sysc interconnect target
module driver only used for MCAN driver so far. But it turns out that
MCAN has the sysstatus register resetdone bit inverted compared to most
other modules.
Let's make OCP softreset work for other typical cases with reset statu
We need to deassert rstctrl resets before enabling clocks to avoid clock
"failed to enable" errors. For asserting rstctrl reset, the clocks need
to be enabled.
As the reset controller status is not available for arrays, let's use
devm_reset_control_get_optional() so we can get the status after res
Modules with clockactivity need it configured during enable.
Signed-off-by: Tony Lindgren
---
drivers/bus/ti-sysc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -845,6 +845,7 @@
Hi all,
Here are changes to improve ti-sysc driver to the point where we can
finally drop the custom hwmods property for most cases. This series
drops hwmods property only for omap4 UART and MMC as those can be
tested with core retention idle.
I'll be posting more patches for dropping hwmods prop
Looks like we currently only detect UART on omap36xx, let's also
add support for omap34xx. And let's also fix the SWSUP mode, it should
be SWSUP_SIDLE for omap3, not SWSUP_SIDLE_ACT like for omap4 and later.
Note that we are still booting omap3 for most part without ti-sysc,
so no need to treat th
We need to specify QUIRK_LEGACY_IDLE for device drivers that still have
pm_runtime_irq_safe() set like 8250.
Signed-off-by: Tony Lindgren
---
drivers/bus/ti-sysc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++
Some modules have idlemodes wired, but not completely functional. We have
quirks for SWSUP_SIDLE and SWSUP_SIDLE_ACT to manage interconnect target
modules without hardware support, but we've been only using them so far
in legacy mode. Let's add support for SWSUP quirks in non-legacy mode too.
Sign
With recent ti-sysc driver changes, we can now finally probe most
modules without needing the custom ti,hwmods property.
Let's drop it for omap4 MMC as we can test that for runtime PM
for core retention idle mode for wlcore WLAN.
Cc: devicet...@vger.kernel.org
Cc: Rob Herring
Signed-off-by: Tony
since hdr was never used, we need not reserve and init it
Signed-off-by: Weitao Hou
---
drivers/mtd/mtdoops.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c
index e078fc41aa61..6ae4b70ebdbb 100644
--- a/drivers/mtd/mtdoops.c
+++ b/drivers/m
With recent ti-sysc driver changes, we can now finally probe most
modules without needing the custom ti,hwmods property.
Let's start with omap4 uart as we can test that for runtime PM
for core retention idle mode.
Cc: devicet...@vger.kernel.org
Cc: Rob Herring
Signed-off-by: Tony Lindgren
---
For interconnect target modules with autoidle bit wired, we need to manage
it for enable and disable.
Signed-off-by: Tony Lindgren
---
drivers/bus/ti-sysc.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drive
We need to also support 16-bit writes for i2c in addition to the reads
when we start configuring the sysconfig register for reset and idle modes.
Signed-off-by: Tony Lindgren
---
drivers/bus/ti-sysc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/
On Thu 23 May 2019 at 21:18, Atish Patra wrote:
> Currently, the last stage boot loaders such as U-Boot can accept only
> uImage which is an unnecessary additional step in automating boot
> process.
>
> Add an image header that boot loader understands and boot Linux from
> flat Image directly.
>
We must not assert reset for modules with no child device drivers
until in runtime_suspend. Otherwise register access will fail without
legacy mode helping us.
Let's add a flag for disable_on_idle and move the reset driver
handling to runtime suspend and resume. We can then also use the
disable_on
Some modules have ENAWAKEUP bit that we need to configure when not
relying on platform data callbacks.
Signed-off-by: Tony Lindgren
---
drivers/bus/ti-sysc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/d
Hi,
Thanks for working on this!
On Sat, May 25, 2019 at 02:13:28PM -0400, Yangtao Li wrote:
> This patch adds binding document for allwinner h6 thermal controller.
>
> Signed-off-by: Yangtao Li
> ---
> .../bindings/thermal/sun8i-thermal.yaml | 71 +++
>
> 1 file changed, 7
Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
Reviewed-by: Rob Herring
---
v4:
- Add Reviewed-by,
v3:
- Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
of renesas,gic-spi-base,
v2:
- Add "r
Add a driver for the Renesas RZ/A1 Interrupt Controller.
This supports using up to 8 external interrupts on RZ/A1, with
configurable sense select.
NMI edge select is not yet supported.
Signed-off-by: Geert Uytterhoeven
Tested-by: Chris Brandt
Reviewed-by: Simon Horman
---
For simplicity, inte
Hi all,
Unlike on most other Renesas SoCs, the GPIO controller blocks on RZ/A1
and RZ/A2 SoCs lack interrupt functionality. While the GPIOs can be
routed to the GIC as pin interrupts, this is of limited use, as the
PL390 or GIC-400 supports rising edge and high-level interrupts only.
For
While the Hardware User Manual does not document the maximum time needed
for modifying bits in the MSIOF Control Register, experiments on R-Car
Gen2/Gen3 and SH-Mobile AG5 revealed the following typical modification
times for the various bits:
- CTR.TXE and CTR.RXE: no delay,
- CTR.TSCKE: less
Hi Weitao,
Weitao Hou wrote on Mon, 27 May 2019 20:14:40
+0800:
> since hdr was never used, we need not reserve and init it
What about "MTD oops 'hdr' header is never used, drop its
initialization."
Maybe a Fixes tag would be appropriate.
>
> Signed-off-by: Weitao Hou
> ---
> drivers/mtd/m
On Tue, May 21, 2019 at 01:51:36PM -0700, Rick Edgecombe wrote:
> The calculation of the direct map address range to flush was wrong.
> This could cause problems on x86 if a RO direct map alias ever got loaded
> into the TLB. This shouldn't normally happen, but it could cause the
> permissions to r
The correct spelling is EACCES:
include/uapi/asm-generic/errno-base.h:#define EACCES 13 /* Permission denied */
Signed-off-by: Geert Uytterhoeven
---
fs/nfsd/vfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c
index fc24ee47eab51ad4..c85783e53
On Mon, May 27, 2019 at 05:07:41PM +0800, Zhenyu Wang wrote:
> On 2019.05.27 16:43:11 +0800, Tina Zhang wrote:
> > Add VFIO_DEVICE_SET_GFX_FLIP_EVENTFD ioctl command to set eventfd
> > based signaling mechanism to deliver vGPU framebuffer page flip
> > event to userspace.
>
> Should we add probe t
The correct spelling is EACCES:
include/uapi/asm-generic/errno-base.h:#define EACCES 13 /* Permission denied */
Signed-off-by: Geert Uytterhoeven
---
include/linux/perf_event.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/perf_event.h b/include/linux/perf_ev
On 5/25/19 8:28 PM, Andrew Morton wrote:
> (Cc Vlastimil)
Oh dear, 2 years and I forgot all the details about how this works.
> On Sat, 25 May 2019 15:07:23 +0800 zhong jiang wrote:
>
>> We bind an different node to different vma, Unluckily,
>> it will bind different vma to same node by checkin
The correct spelling is EACCES:
include/uapi/asm-generic/errno-base.h:#define EACCES 13 /* Permission denied */
Signed-off-by: Geert Uytterhoeven
---
include/linux/scif.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/linux/scif.h b/include/linux/scif.h
inde
Make sure only the portals for the online CPUs are used.
Without this change, there are issues when someone boots with
maxcpus=n, with n < actual number of cores available as frames
either received or corresponding to the transmit confirmation
path would be offered for dequeue to the offline CPU po
On Tue, May 21, 2019 at 01:51:37PM -0700, Rick Edgecombe wrote:
> In a rare case, flush_tlb_kernel_range() could be called with a start
> higher than the end. Most architectures should be fine with with this, but
> some may not like it, so avoid doing this.
>
> In vm_remove_mappings(), in case pag
Fix a silly word ordering typo.
Fixes: 42337b9d4d958daa ("HID: add driver for U2F Zero built-in LED and RNG")
Signed-off-by: Geert Uytterhoeven
---
drivers/hid/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig
index c3c390ca3690
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> This is a preparation for a future cleanup. Pass struct pwm_device
> instead of passing the individual values required by each function as
> these can be obtained for each struct pwm_device instance.
>
> As a nice side-effect the driver now uses "s
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> Simplify the code which fetches the input clock for a PWM channel by
> using devm_clk_get_optional().
> This comes with a small functional change: previously all errors except
> EPROBE_DEFER were ignored. Now all other errors are also treated as
> e
Adds a compile-time option to ensure urandom reads block until
the cryptographic random number generator (CRNG) is initialized.
This fixes a long standing security issue, the so called boot-time
entropy hole, where systems (particularly headless and embededd)
generate cryptographic keys before the
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> meson_pwm_calc() ensures that "lo" is always less than 16 bits wide
> (otherwise it would overflow into the "hi" part of the REG_PWM_{A,B}
> register).
> Use GENMASK and FIELD_PREP for the lo and hi values to make it easier to
> spot how wide these
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> MISC_CLK_SEL_WIDTH is only used in one place where it's converted into
> a bit-mask. Rename and change the macro to be a bit-mask so that
> conversion is not needed anymore. No functional changes intended.
>
> Signed-off-by: Martin Blumenstingl
>
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> Let meson_pwm_calc() use the polarity from struct pwm_state directly.
> This removes a level of indirection where meson_pwm_apply() first had to
> set a driver-internal inverter mask which was then only used by
> meson_pwm_calc().
>
> Instead of ad
There is no need to print error messages if kcalloc() or
alloc_cpumask_var() fail, as the memory allocation core already takes
care of that.
Signed-off-by: Geert Uytterhoeven
---
drivers/base/arch_topology.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/base/arc
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> meson_pwm_calc() is the last function that accepts a struct
> meson_pwm_channel. meson_pwm_enable(), meson_pwm_disable() and
> meson_pwm_apply() for example are all taking a struct pwm_device as
> parameter. When they need the struct meson_pwm_chann
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> Make struct meson_pwm_channel accessible from struct meson_pwm.
>
> PWM core has a limitation: per-channel data can only be set after
> pwmchip_add() is called. However, pwmchip_add() internally calls
> pwm_ops.get_state(). If pwm_ops.get_state() n
There is no need to print an error message if kstrdup() fails, as the
memory allocation core already takes care of that.
Note that commit 59d84ca8c46a93ad ("PM / OPP / clk: Remove unnecessary
OOM message") already removed similar error messages, but this one was
forgotten.
Signed-off-by: Geert Uy
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> Introduce struct meson_pwm_channel_data which contains the per-channel
> offsets for the PWM register and REG_MISC_AB bits. Replace the existing
> switch (pwm->hwpwm) statements with an access to the new struct.
>
> This simplifies the code and wil
Hi!
Thanks for submitting a new version
On Sat, May 25, 2019 at 02:13:27PM -0400, Yangtao Li wrote:
> This patch adds the support for allwinner thermal sensor, within
> allwinner SoC. It will register sensors for thermal framework
> and use device tree to bind cooling device.
>
> Signed-off-by: Y
On Sun, May 26, 2019 at 09:00:30PM +0200, Clément Péron wrote:
> Hi Maxime,
>
> On Sun, 26 May 2019 at 20:24, Maxime Ripard wrote:
> >
> > On Sat, May 25, 2019 at 06:23:19PM +0200, Clément Péron wrote:
> > > Allwinner H6 has a different bit to flush the TX FIFO.
> > >
> > > Add a quirks to prepare
On Mon, May 27, 2019 at 12:45 PM Christian Brauner wrote:
> On Mon, May 27, 2019 at 12:02:37PM +0200, Arnd Bergmann wrote:
> > On Sun, May 26, 2019 at 12:27 PM Christian Brauner
> > wrote:
> > >
> > > Wire up the clone6() call on x86.
> > >
> > > This patch only wires up clone6() on x86. Some of
There is no need to print an error message and backtrace if
kmalloc_node() fails, as the memory allocation core already takes care
of that.
Signed-off-by: Geert Uytterhoeven
---
lib/cpumask.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/lib/cpumask.c b/lib/cpumask.c
index 0cb672eb10
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> All existing PWM drivers (except pwm-meson and two other ones) call
> pwm_set_chip_data() from their pwm_ops.request() callback. Now that we
> can access the struct meson_pwm_channel from struct meson_pwm we can do
> the same.
>
> Move the call to
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> Update the meson_pwm_get_state() implementation to take care of all
> information in the registers instead of only reading the "enabled"
> state.
>
> The PWM output is only enabled if two conditions are met:
> 1. the per-channel clock is enabled
>
Add "fsl,ls1046a-frwy" bindings for ls1046afrwy board based on ls1046a SoC
Signed-off-by: Vabhav Sharma
Signed-off-by: Pramod Kumar
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/
add micron nor flash support for ls1046a frwy board.
Signed-off-by: Ashish Kumar
Signed-off-by: Pramod Kumar
---
.../boot/dts/freescale/fsl-ls1046a-frwy.dts| 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.d
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> The PWM core already caches the "current struct pwm_state" as the
> "current state of the hardware registers" inside struct pwm_device.
>
> Drop the struct pwm_state from struct meson_pwm_channel in favour of the
> struct pwm_state in struct pwm_de
Changes for v3:
- Remove undocumented propert i2c-mux-never-disable
- Sort nodes at i2c mux in unit-address
- Remove Unnecessary newline
Changes for v2:
- Modified comit message
- Add dts entry for qspi nor flash
Pramod Kumar (3):
dt-bindings: arm: nxp: Add device tree binding for ls1046a-frwy
ls1046afrwy board is based on nxp ls1046a SoC.
Board support's 4GB ddr memory, i2c, microSD card,
serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
usb 3.0 and serdes interface to support two x1gen3 pcie interface.
Signed-off-by: Vabhav Sharma
Signed-off-by: Pramod Kumar
---
The keygen extracted fields are used as input for the hash that
determines the incoming frames distribution. Adding IPSEC SPI so
different IPSEC flows can be distributed to different CPUs.
Signed-off-by: Madalin Bucur
---
drivers/net/ethernet/freescale/fman/fman_keygen.c | 3 ++-
1 file changed,
On Mon, May 27, 2019 at 12:21:59PM +0200, Paolo Bonzini wrote:
> On 27/05/19 11:47, Peter Zijlstra wrote:
> > --- a/arch/x86/kernel/kvm.c
> > +++ b/arch/x86/kernel/kvm.c
> > @@ -580,7 +580,7 @@ static void __init kvm_apf_trap_init(voi
> >
> > static DEFINE_PER_CPU(cpumask_var_t, __pv_tlb_mask);
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> meson_pwm_apply() has to consider the PWM polarity when disabling the
> output.
> With enabled=false and polarity=PWM_POLARITY_NORMAL the output needs to
> be LOW. The driver already supports this.
> With enabled=false and polarity=PWM_POLARITY_INVE
On 25/05/2019 20:11, Martin Blumenstingl wrote:
> Add a link to the datasheet and a short summary how the hardware works.
> The goal is to make it easier for other developers to understand why the
> pwm-meson driver is implemented the way it is.
>
> Suggested-by: Uwe Kleine-König
> Co-authored-by
On Mon, May 27, 2019 at 02:28:33PM +0200, Arnd Bergmann wrote:
> On Mon, May 27, 2019 at 12:45 PM Christian Brauner
> wrote:
> > On Mon, May 27, 2019 at 12:02:37PM +0200, Arnd Bergmann wrote:
> > > On Sun, May 26, 2019 at 12:27 PM Christian Brauner
> > > wrote:
> > > >
> > > > Wire up the clone
On 26/05/2019 21:41, Uwe Kleine-König wrote:
> On Sat, May 25, 2019 at 08:11:29PM +0200, Martin Blumenstingl wrote:
>> Replace the loop to calculate the pre-divider and count with two
>> separate div64_u64() calculations. This makes the code easier to read
>> and improves the precision.
>>
>> Two e
MTD oops 'hdr' header is never used, drop its initialization
Signed-off-by: Weitao Hou
---
Changes in v2:
-fix comment for patch
---
drivers/mtd/mtdoops.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c
index e078fc41aa61..6ae4b70ebdbb 1006
Hi Mason,
masonccy...@mxic.com.tw wrote on Thu, 23 May 2019 16:58:02 +0800:
> Hi Miquel,
>
> > >
> > > > > +
> > > > > +static void mxic_nand_select_chip(struct nand_chip *chip, int
> chipnr)
> > > >
> > > > _select_target() is preferred now
> > >
> > > Do you mean I implement mxic_n
From: Jerome Brunet
The Amlogic G12A SDIO Controller has a bug preventing direct DDR access,
add the port A (SDIO) pinctrl and controller nodes and mark this specific
controller with the amlogic,dram-access-quirk property.
Signed-off-by: Jerome Brunet
Signed-off-by: Neil Armstrong
---
arch/ar
On the Amlogic G12A SoC family, (only) the SDIO controller has a bug which
makes any DRAM access from the MMC controller fail.
Add the amlogic,dram-access-quirk property so signal this particular
controller has this bug and needs a quirk to work properly.
Reviewed-by: Martin Blumenstingl
Signed-
On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
the data from DRAM, leading to a broken controller.
Add the amlogic,ddr-access-quirk property so signal this particular
controller has this bug and needs a quirk to work properly.
But each MMC controller has 1,5KiB of SRAM
On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
the data from DRAM, leading to a broken controller.
But each MMC controller has 1,5KiB of SRAM after the registers, that can
be used as bounce buffer to avoid direct DRAM access from the integrated
DMAs (this SRAM may be us
On Mon 27-05-19 16:58:11, Minchan Kim wrote:
> On Tue, May 21, 2019 at 08:26:28AM +0200, Michal Hocko wrote:
> > On Tue 21-05-19 11:55:33, Minchan Kim wrote:
> > > On Mon, May 20, 2019 at 11:28:01AM +0200, Michal Hocko wrote:
> > > > [cc linux-api]
> > > >
> > > > On Mon 20-05-19 12:52:54, Minchan
On 27/05/19 14:32, Peter Zijlstra wrote:
> On Mon, May 27, 2019 at 12:21:59PM +0200, Paolo Bonzini wrote:
>> On 27/05/19 11:47, Peter Zijlstra wrote:
>
>>> --- a/arch/x86/kernel/kvm.c
>>> +++ b/arch/x86/kernel/kvm.c
>>> @@ -580,7 +580,7 @@ static void __init kvm_apf_trap_init(voi
>>>
>>> static
On Thu 2019-05-23 15:59:47, Sergey Senozhatsky wrote:
> On (05/15/19 16:47), Petr Mladek wrote:
> > On Fri 2019-04-26 14:44:45, Sergey Senozhatsky wrote:
> > >
> > > Forgot to mention that the series is still in RFC phase.
> > >
> > >
> > > On (04/26/19 14:33), Sergey Senozhatsky wrote:
> > > [.
On Sun, May 26, 2019 at 09:12:36PM +0200, Clément Péron wrote:
> Hi Maxime,
>
> On Sun, 26 May 2019 at 20:34, Maxime Ripard wrote:
> >
> > On Sat, May 25, 2019 at 06:38:17PM +0200, Clément Péron wrote:
> > > From: Jernej Skrabec
> > >
> > > H6 DMA has more than 32 supported DRQs, which means that
On Mon, May 27, 2019 at 03:08:07PM +0300, Adrian Hunter wrote:
> On 27/05/19 12:37 PM, Brian Masney wrote:
> > On Sun, May 26, 2019 at 03:58:19PM -0400, Brian Masney wrote:
> >> I attached a patch that shows how I was able to determine what had
> >> already claimed the host.
> > On Mon, May 27, 201
The Amlogic G12A has the hwrng module at the end of an unknown
"EFUSE" bus.
The hwrng is not enabled on the vendor G12A DTs, but is enabled on
next generation SM1 SoC family sharing the exact same memory mapping.
Let's add the "EFUSE" bus and the hwrng node.
This hwrng has been checked with the
Because this driver will support multiple configurations for software,
the software configuration was made generic.
Signed-off-by: Beniamin Bia
Acked-by: Jonathan Cameron
---
Changes in v2:
-nothing changed
drivers/iio/adc/ad7606.c | 40 +---
drivers/iio/adc
Support for ad7616 running in software was added. In order
to activate the software mode, HW_RNGSEL pins must be pulled low.
Oversampling and input ranges are now configured in corresponding
registers. Ad7616 has multiple scale options when it is configured
in software mode.
Also, in order to suppo
Support for register access was added for spi devices.
Signed-off-by: Beniamin Bia
Acked-by: Jonathan Cameron
---
Changes in v2:
-nothing changed
drivers/iio/adc/ad7606.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/a
The device dependent options which are going to be different for devices
which will be supported in the future by this driver,
were moved in chip info for a more generic driver. This patch allows
supporting more devices by the driver. Also, it is an intermediate
step of adding support for ad7616 i
On Mon, 27 May 2019 11:38:42 +0200
"Uladzislau Rezki (Sony)" wrote:
> Move the BUG_ON()/RB_EMPTY_NODE() check under unlink_va()
> function, it means if an empty node gets freed it is a BUG
> thus is considered as faulty behaviour.
Can we switch it to a WARN_ON(). We are trying to remove all BUG_
Enable the network interface of the X96 Mac using an external
Realtek RTL8211F gigabit PHY, needing the same broken-eee properties
as the previous Amlogic SoC generations.
Signed-off-by: Neil Armstrong
---
Changes since v1:
- Fixed eth_rmii_pins into eth_pins
.../boot/dts/amlogic/meson-g12a-x9
On Thu 2019-05-23 16:50:36, Sebastian Andrzej Siewior wrote:
> On 2019-05-23 10:37:24 [+0200], Pavel Machek wrote:
> > Hi!
> Hi,
>
> > > I did not notice any new crashes.
> >
> > New crash now; different machine, way -next kernel... and I even have
> > a backtrace.
>
> could you please send me (
On Thu 2019-05-23 16:50:36, Sebastian Andrzej Siewior wrote:
> On 2019-05-23 10:37:24 [+0200], Pavel Machek wrote:
> > Hi!
> Hi,
>
> > > I did not notice any new crashes.
> >
> > New crash now; different machine, way -next kernel... and I even have
> > a backtrace.
>
> could you please send me (
In tegra_hsp_doorbell_create(), 'db->name' is allocated by
devm_kstrdup_const(). It returns NULL when fails. So 'db->name' should
be checked.
Signed-off-by: Gen Zhang
---
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 11fc9fd..b613c46 100644
--- a/drivers/mailbox/te
On 2019-05-27 15:03:17 [+0200], Pavel Machek wrote:
> > could you please send me (offlist) your .config? Also, what kind of
> > userland do you run? Something like Debian stable?
>
> Yep, debian stable.
Since we had a little bit of development recently, could you please
check if
http://lk
Refer to the Intel SDM Vol.4, the package C-state residency counters
of modern IA micro-architecture are all ticking in TSC frequency,
hence we can apply simple math to transform the ticks into microseconds.
i.e.,
residency (ms) = count / tsc_khz
residency (us) = count / tsc_khz * 1000
This also a
On Fri, May 24, 2019 at 8:19 PM Martin Blumenstingl
wrote:
>
> The TRONFY MXQ comes with either 1GB or 2GB RAM.
>
> Both variants share (like most boards based on Amlogic reference
> designs):
> - 10/100 PHY (IC Plus IP101GR) with GPIOH_4 being the reset line and
> GPIOH_3 the interrupt line
> -
request_key and ecryptfs_get_encrypted_key never
return a NULL pointer, so no need do a null check.
Signed-off-by: YueHaibing
---
fs/ecryptfs/keystore.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fs/ecryptfs/keystore.c b/fs/ecryptfs/keystore.c
index 95662fd46b1d..a1a
On 5/27/19 9:53 AM, Potyra, Stefan wrote:
> If mlockall() is called with only MCL_ONFAULT as flag,
> it removes any previously applied lockings and does
> nothing else.
>
> This behavior is counter-intuitive and doesn't match the
> Linux man page.
>
> For mlockall():
>
> EINVAL Unknown flag
From: Christian Hewitt
- Remove serial1 alias
- Add support for uart_A rts/cts
- Add bluetooth uart_A subnode qith shutdown gpio
Fixes: b8b74dda3908 ("ARM64: dts: meson-gxm: Add support for Khadas VIM2")
Signed-off-by: Christian Hewitt
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/aml
Add HDMI nodes to support graphics on Vega S95
Suggested-by: Christian Hewitt
Signed-off-by: Neil Armstrong
---
.../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
b/arch/arm
This patchset :
- Fixes GPIO key DT on Khadas VIM2 board
- Fixes regulator naming on Vega S95 board
- Enable SARADC on Wetek and Vega S95 boards
- Enable/Fix Bluetooth on VIM2, Wetek and Vega S95 boards
- Enable CEC & HDMI on Vega S95 board
- Adds ethernet PHY interrupt on Vega S95 board
Christian
Fix the SDIO WiFi support and add proper Bluetooth support on the
Vega S95 board.
Suggested-by: Christian Hewitt
Signed-off-by: Neil Armstrong
---
.../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/bo
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