On Tue, Oct 11, 2016 at 11:57:52AM -0500, Nilay Vaish wrote:
> I think we should go with Fenghua' suggestion on this. Reading the
> code around the edits from this patch, it seems word 7 is not owned by
> anyone. Both AMD and Intel seem to be using it.
No, this is wrong. The 0x0 CPUID leaf is ow
On 8 October 2016 at 14:52, Borislav Petkov wrote:
> On Sat, Oct 08, 2016 at 01:54:54PM -0700, Fenghua Yu wrote:
>> > I think these #defines are specific to Intel. I would prefer if we
>> > have _INTEL_ somewhere in them.
>
> We don't generally add vendor names to those defines. Even more so if
>
On Mon, Oct 10, 2016 at 09:01:44AM -0700, Dave Hansen wrote:
> While that isn't a horrible idea, it's also not something that we've
> enforced at *all* in the past. Would you suggest that we do this only
> for features in the generic CPUID leaves, or all features?
There's no reason to do anything
On 10/08/2016 10:11 AM, Nilay Vaish wrote:
>> > #define X86_FEATURE_RTM( 9*32+11) /* Restricted
>> > Transactional Memory */
>> > #define X86_FEATURE_CQM( 9*32+12) /* Cache QoS Monitoring
>> > */
>> > #define X86_FEATURE_MPX( 9*32+14) /* Memory P
On Sat, Oct 08, 2016 at 01:54:54PM -0700, Fenghua Yu wrote:
> > I think these #defines are specific to Intel. I would prefer if we
> > have _INTEL_ somewhere in them.
We don't generally add vendor names to those defines. Even more so if
the 0x0... leaf range is Intel-specific anyway.
> Is adding
On Sat, Oct 08, 2016 at 12:11:22PM -0500, Nilay Vaish wrote:
> On 7 October 2016 at 21:45, Fenghua Yu wrote:
> > From: Fenghua Yu
> >
> > Check CPUID leaves for all the Resource Director Technology (RDT)
> > Cache Allocation Technology (CAT) bits.
> >
> > Prescence of allocation features:
>
> Pr
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Check CPUID leaves for all the Resource Director Technology (RDT)
> Cache Allocation Technology (CAT) bits.
>
> Prescence of allocation features:
Presence
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include
From: Fenghua Yu
Check CPUID leaves for all the Resource Director Technology (RDT)
Cache Allocation Technology (CAT) bits.
Prescence of allocation features:
CPUID.(EAX=7H, ECX=0):EBX[bit 15] X86_FEATURE_RDT_A
L2 and L3 caches are each separately enabled:
CPUID.(EAX=10H, ECX=0):EBX[bit 1
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