Hi Peter,
On Thu, Apr 15, 2021 at 7:51 AM Peter Zijlstra wrote:
>
> On Tue, Apr 13, 2021 at 08:53:36AM -0700, Namhyung Kim wrote:
> > As we can run many jobs (in container) on a big machine, we want to
> > measure each job's performance during the run. To do that, the
> > perf_event can be assoc
Hi,
I would like to re-emphasize why this patch is important. As Namhyung
outlined in his cover message,
cgroup monitoring build on top of per-cpu monitoring and offers
maximum flexibility by allowing each event
to be attached to a single cgroup. Although this is fine when the
machines were much s
On Tue, Mar 16, 2021 at 5:28 AM Liang, Kan wrote:
>
>
>
> On 3/16/2021 3:22 AM, Namhyung Kim wrote:
> > Hi Peter and Kan,
> >
> > On Thu, Mar 4, 2021 at 5:22 AM Peter Zijlstra wrote:
> >>
> >> On Wed, Mar 03, 2021 at 02:53:00PM -0500, Liang, Kan wrote:
> >>> On 3/3/2021 1:59 PM, Peter Zijlstra wr
On Wed, Mar 3, 2021 at 10:16 AM Vince Weaver wrote:
>
> Hello
>
> on my Haswell machine the perf_fuzzer managed to trigger this message:
>
> [117248.075892] unchecked MSR access error: WRMSR to 0x3f1 (tried to write
> 0x0400) at rIP: 0x8106e4f4 (native_write_msr+0x4/0x20)
> [1
Hi Peter,
Any comments on this patch series?
It is quite useful to be able to count the number of cgroup switches
simply using perf stat/record.
Not all context switches (cs) are necessarily cgroup switches.
Thanks.
On Wed, Feb 10, 2021 at 12:33 AM Namhyung Kim wrote:
>
> In some cases, we need
On Wed, Jan 6, 2021 at 1:49 AM Jiri Olsa wrote:
>
> On Tue, Jan 05, 2021 at 05:33:38PM -0800, Stephane Eranian wrote:
> > Hi,
> >
> > On Wed, Dec 30, 2020 at 3:09 AM Jiri Olsa wrote:
> > >
> > > Currently we allow pipe input/output only through &#
Hi,
On Wed, Dec 30, 2020 at 3:09 AM Jiri Olsa wrote:
>
> Currently we allow pipe input/output only through '-' string
> being passed to '-o' or '-i' options, like:
>
It seems to me it would be useful to auto-detect that the perf.data
file is in pipe vs. file mode format.
Your patch detects the ty
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27
Gitweb:
https://git.kernel.org/tip/fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27
Author:Stephane Eranian
AuthorDate:Thu, 26 Nov 2020 20:09:22 +09:00
On Wed, Dec 2, 2020 at 2:42 PM Andi Kleen wrote:
>
> On Wed, Dec 02, 2020 at 11:47:25AM -0800, Stephane Eranian wrote:
> > On Wed, Dec 2, 2020 at 11:28 AM Andi Kleen wrote:
> > >
> > > > + prev_cgrp = task_css_check(prev, perf_event_cgrp_id, 1)
On Wed, Dec 2, 2020 at 11:28 AM Andi Kleen wrote:
>
> > + prev_cgrp = task_css_check(prev, perf_event_cgrp_id, 1)->cgroup;
> > + next_cgrp = task_css_check(next, perf_event_cgrp_id, 1)->cgroup;
> > +
> > + if (prev_cgrp != next_cgrp)
> > + perf_sw_event_sched(PERF_COUNT_SW_
Hi,
Another remark on the PEBS drainage code, it seems to me like a test
is not quite correct:
intel_pmu_drain_pebs_nhm()
{
...
if (p->status != (1ULL << bit)) {
for_each_set_bit(i, (unsigned long *)&pebs_status, size)
error[i]
On Tue, Nov 10, 2020 at 7:37 AM Peter Zijlstra wrote:
>
> On Tue, Nov 10, 2020 at 04:12:57PM +0100, Peter Zijlstra wrote:
> > On Mon, Nov 09, 2020 at 10:12:37AM +0800, Like Xu wrote:
> > > The Precise Event Based Sampling(PEBS) supported on Intel Ice Lake server
> > > platforms can provide an arch
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: cadbaa039b99a6d5c26ce1c7f2fc0325943e605a
Gitweb:
https://git.kernel.org/tip/cadbaa039b99a6d5c26ce1c7f2fc0325943e605a
Author:Stephane Eranian
AuthorDate:Wed, 28 Oct 2020 12:42:47 -07:00
On Thu, Nov 5, 2020 at 11:40 AM Liang, Kan wrote:
>
>
>
> On 11/5/2020 10:54 AM, Namhyung Kim wrote:
> >> -void perf_sched_cb_inc(struct pmu *pmu)
> >> +void perf_sched_cb_inc(struct pmu *pmu, bool systemwide)
> >>{
> >> struct perf_cpu_context *cpuctx =
> >> this_cpu_ptr(pmu->pmu_cp
On Mon, Oct 26, 2020 at 7:19 AM Namhyung Kim wrote:
>
> I found that order of events in a group impacts performance during the
> open. If a group has a software event as a leader and has other
> hardware events, the lead needs to be moved to a hardware context.
> This includes RCU synchronization
On Mon, Nov 2, 2020 at 6:52 AM Namhyung Kim wrote:
>
> Hello,
>
> It was reported that system-wide events with precise_ip set have a lot
> of unknown symbols on Intel machines. Depending on the system load I
> can see more than 30% of total symbols are not resolved (actually
> don't have DSO mapp
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 995f088efebe1eba0282a6ffa12411b37f8990c2
Gitweb:
https://git.kernel.org/tip/995f088efebe1eba0282a6ffa12411b37f8990c2
Author:Stephane Eranian
AuthorDate:Thu, 01 Oct 2020 06:57:49 -07:00
the CPUID 0xa leaf
function to determine if anythread is supported or not as described in the
Intel SDM Vol3b 18.2.5.1 AnyThread Deprecation section.
In V2, we remove intel_arch_v4_format_attrs because it is a duplicate
of intel_arch_format_attrs.
Signed-off-by: Stephane Eranian
---
arch/x86
On Thu, Oct 22, 2020 at 1:00 AM Peter Zijlstra wrote:
>
> On Wed, Oct 21, 2020 at 02:16:12PM -0700, Stephane Eranian wrote:
> > Starting with Arch Perfmon v5, the anythread filter on generic counters may
> > be
> > deprecated. The current kernel was exporting the any filt
the CPUID 0xa leaf
function to determine if anythread is supported or not as described in the
Intel SDM Vol3b 18.2.5.1 AnyThread Deprecation section.
Signed-off-by: Stephane Eranian
---
arch/x86/events/intel/core.c | 20
arch/x86/events/perf_event.h | 1 +
arch/x86
On Wed, Sep 30, 2020 at 10:30 AM Peter Zijlstra wrote:
>
> On Wed, Sep 30, 2020 at 07:48:48AM -0700, Dave Hansen wrote:
> > On 9/30/20 7:42 AM, Liang, Kan wrote:
> > >> When I tested on my kernel, it panicked because I suspect
> > >> current->active_mm could be NULL. Adding a check for NULL avoide
On Wed, Sep 30, 2020 at 7:48 AM Dave Hansen wrote:
>
> On 9/30/20 7:42 AM, Liang, Kan wrote:
> >> When I tested on my kernel, it panicked because I suspect
> >> current->active_mm could be NULL. Adding a check for NULL avoided the
> >> problem. But I suspect this is not the correct solution.
> >
>
On Mon, Sep 21, 2020 at 8:29 AM wrote:
>
> From: Kan Liang
>
> Current perf can report both virtual addresses and physical addresses,
> but not the MMU page size. Without the MMU page size information of the
> utilized page, users cannot decide whether to promote/demote large pages
> to optimize
Hi,
On Mon, Sep 21, 2020 at 2:46 AM Namhyung Kim wrote:
>
> The --for-each-cgroup option is a syntax sugar to monitor large number
> of cgroups easily. Current command line requires to list all the
> events and cgroups even if users want to monitor same events for each
> cgroup. This patch addr
On Mon, Sep 14, 2020 at 2:08 AM wrote:
>
> On Sun, Sep 13, 2020 at 11:41:00PM -0700, Stephane Eranian wrote:
> > On Sun, Sep 13, 2020 at 2:03 PM Jiri Olsa wrote:
> > what happens if I set mmap3 and mmap2?
> >
> > I think using mmap3 for every mmap may be overkill a
On Sun, Sep 13, 2020 at 2:03 PM Jiri Olsa wrote:
>
> Add new version of mmap event. The MMAP3 record is an
> augmented version of MMAP2, it adds build id value to
> identify the exact binary object behind memory map:
>
> struct {
> struct perf_event_header header;
>
> u32
ommu_7 18:amd_iommu_5 2:tracepoint 21:msr 12:ibs_op 16:amd_iommu_3
11:ibs_fetch
Signed-off-by: Stephane Eranian
---
tools/perf/util/header.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/tools/perf/util/header.c b/tools/perf/util/heade
u_3
11:ibs_fetch
Signed-off-by: Stephane Eranian
---
tools/perf/util/header.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c
index 7a67d017d72c3..cf72124da9350 100644
--- a/tools/perf/util/header.c
+++ b/to
On Thu, Jun 4, 2020 at 6:11 AM Johannes Hirte
wrote:
>
> On 2020 Jun 01, Stephane Eranian wrote:
> > On Mon, Jun 1, 2020 at 5:39 AM Johannes Hirte
> > wrote:
> > >
> > > On 2020 Mai 27, Stephane Eranian wrote:
> > >
> > > ...
> >
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 16accae3d97f97d7f61c4ee5d0002bccdef59088
Gitweb:
https://git.kernel.org/tip/16accae3d97f97d7f61c4ee5d0002bccdef59088
Author:Stephane Eranian
AuthorDate:Thu, 28 May 2020 13:16:14 -07:00
On Mon, Jun 1, 2020 at 5:39 AM Johannes Hirte
wrote:
>
> On 2020 Mai 27, Stephane Eranian wrote:
>
> ...
> > diff --git a/arch/x86/events/Makefile b/arch/x86/events/Makefile
> > index 6f1d1fde8b2de..12c42eba77ec3 100644
> > --- a/arch/x86/events/Makefile
>
On Thu, May 28, 2020 at 2:30 PM Kim Phillips wrote:
>
> On 5/28/20 3:16 PM, Stephane Eranian wrote:
> > This patch fixes a bug introduced by:
> >
> > commit fd3ae1e1587d6 ("perf/x86/rapl: Move RAPL support to common x86 code")
> >
> > The Kconf
This patch fixes a bug introduced by:
commit fd3ae1e1587d6 ("perf/x86/rapl: Move RAPL support to common x86 code")
The Kconfig variable name was wrong. It was missing the CONFIG_ prefix.
Signed-off-by: Stephane Eranian
---
arch/x86/events/Makefile | 2 +-
1 file changed, 1 inser
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 5c95c68949880035b68e5c48fdf4899ec0989631
Gitweb:
https://git.kernel.org/tip/5c95c68949880035b68e5c48fdf4899ec0989631
Author:Stephane Eranian
AuthorDate:Wed, 27 May 2020 15:46:56 -07:00
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 2a3e3f73a23b4ff2c0065d3a42edc18ad94b7851
Gitweb:
https://git.kernel.org/tip/2a3e3f73a23b4ff2c0065d3a42edc18ad94b7851
Author:Stephane Eranian
AuthorDate:Wed, 27 May 2020 15:46:57 -07:00
The following commit has been merged into the perf/core branch of tip:
Commit-ID: fd3ae1e1587d64ef8cc8e361903d33625458073e
Gitweb:
https://git.kernel.org/tip/fd3ae1e1587d64ef8cc8e361903d33625458073e
Author:Stephane Eranian
AuthorDate:Wed, 27 May 2020 15:46:55 -07:00
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 5cde265384cad739b162cf08afba6da8857778bd
Gitweb:
https://git.kernel.org/tip/5cde265384cad739b162cf08afba6da8857778bd
Author:Stephane Eranian
AuthorDate:Wed, 27 May 2020 15:46:59 -07:00
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 4c953f879460bf65ea3c119354026b126fe8ee57
Gitweb:
https://git.kernel.org/tip/4c953f879460bf65ea3c119354026b126fe8ee57
Author:Stephane Eranian
AuthorDate:Wed, 27 May 2020 15:46:58 -07:00
rule
applies which is to make the group visible. Without the patch,
you would get a kernel crash with a NULL group.
Signed-off-by: Stephane Eranian
---
arch/x86/events/probe.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c
index
This patch enables AMD Fam17h RAPL support for the Package level metric.
The support is as per AMD Fam17h Model31h (Zen2) and model 00-ffh (Zen1) PPR.
The same output is available via the energy-pkg pseudo event:
$ perf stat -a -I 1000 --per-socket -e power/energy-pkg/
Signed-off-by: Stephane
This patch modifies the rapl_model struct to include architecture specific
knowledge to Intel specific structure, and in particular the MSR for
POWER_UNIT and the rapl_msrs array.
No functional changes.
Signed-off-by: Stephane Eranian
---
arch/x86/events/rapl.c | 29
eed to handle unpopulated entries in the array and in
perf_msr_probe()
which is what patch 4 does.
Signed-off-by: Stephane Eranian
Stephane Eranian (5):
perf/x86/rapl: move RAPL support to common x86 code
perf/x86/rapl: refactor code for Intel/AMD sharing
perf/x86/rapl: flip logic on d
To prepare for support of both Intel and AMD RAPL.
Signed-off-by: Stephane Eranian
---
arch/x86/events/Kconfig| 6 +++---
arch/x86/events/Makefile | 1 +
arch/x86/events/intel/Makefile | 2 --
arch/x86/events/{intel => }/rapl.c | 9 ++---
4 files changed,
0 (no visible).
Signed-off-by: Stephane Eranian
---
arch/x86/events/rapl.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 72990e9a4e71f..fcb21fbcfe0d0 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -
Hi,
On Mon, May 18, 2020 at 1:16 PM Stephane Eranian wrote:
>
> On Mon, May 18, 2020 at 2:34 AM Peter Zijlstra wrote:
> >
> > On Fri, May 15, 2020 at 02:57:33PM -0700, Stephane Eranian wrote:
> >
> > > +static struct perf_msr amd_rapl_msrs[] = {
&
On Mon, May 18, 2020 at 2:34 AM Peter Zijlstra wrote:
>
> On Fri, May 15, 2020 at 02:57:33PM -0700, Stephane Eranian wrote:
>
> > +static struct perf_msr amd_rapl_msrs[] = {
> > + [PERF_RAPL_PP0] = { 0, &rapl_events_cores_group, NULL},
> > + [PERF_RAPL_PKG]
On Mon, May 18, 2020 at 12:21 PM Jiri Olsa wrote:
>
> On Mon, May 18, 2020 at 02:12:42PM -0500, Paul A. Clarke wrote:
> > I'm curious how hard it would be to define metrics using other metrics,
> > in the metrics definition files.
> >
> > Currently, to my understanding, every metric definition mus
This patch modifies the rapl_model struct to include architecture specific
knowledge to Intel specific structure, and in particular the MSR for
POWER_UNIT and the rapl_msrs array.
No functional changes.
Signed-off-by: Stephane Eranian
---
arch/x86/events/rapl.c | 29
This patch enables AMD Fam17h RAPL support for the Package level metric.
The support is as per AMD Fam17h Model31h (Zen2) and model 00-ffh (Zen1) PPR.
The same output is available via the energy-pkg pseudo event:
$ perf stat -a -I 1000 --per-socket -e power/energy-pkg/
Signed-off-by: Stephane
To prepare for support of both Intel and AMD RAPL.
Move rapl.c to arch/x86/events. Rename config option.
Fixup header paths.
Signed-off-by: Stephane Eranian
---
arch/x86/events/Kconfig| 8
arch/x86/events/Makefile | 1 +
arch/x86/events/intel/Makefile | 2
then
adds the support.
>From the user's point of view, the interface is identical with
/sys/devices/power. The energy-pkg event is the only one supported.
$ perf stat -a --per-socket -I 1000 -e power/energy-pkg/
Signed-off-by: Stephane Eranian
Stephane Eranian (3):
perf/x86/rapl: m
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 5ef86146de941f273d669a8e018036f549bf058c
Gitweb:
https://git.kernel.org/tip/5ef86146de941f273d669a8e018036f549bf058c
Author:Stephane Eranian
AuthorDate:Wed, 29 Apr 2020 16:14:41 -07:00
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 3a50dc76058d7cd8315f9c712b793d81a7ff4541
Gitweb:
https://git.kernel.org/tip/3a50dc76058d7cd8315f9c712b793d81a7ff4541
Author:Stephane Eranian
AuthorDate:Wed, 29 Apr 2020 16:14:42 -07:00
The following commit has been merged into the perf/core branch of tip:
Commit-ID: fad1f1e7dedcd97593e8af36786b6bbdd093990d
Gitweb:
https://git.kernel.org/tip/fad1f1e7dedcd97593e8af36786b6bbdd093990d
Author:Stephane Eranian
AuthorDate:Sat, 18 Apr 2020 16:19:08 -07:00
The following commit has been merged into the perf/core branch of tip:
Commit-ID: d99c22eabee45f40ca44b877a1adde028f14b6b4
Gitweb:
https://git.kernel.org/tip/d99c22eabee45f40ca44b877a1adde028f14b6b4
Author:Stephane Eranian
AuthorDate:Wed, 22 Apr 2020 08:50:38 -07:00
On Wed, May 6, 2020 at 4:37 AM Peter Zijlstra wrote:
>
> On Tue, May 05, 2020 at 08:37:40PM -0700, Stephane Eranian wrote:
> > Hi,
> >
> > I have received reports from users who have noticed a change of
> > behaviour caused by
> > commit:
> >
> > 6
Hi,
I have received reports from users who have noticed a change of
behaviour caused by
commit:
6cbc304f2f360 ("perf/x86/intel: Fix unwind errors from PEBS entries (mk-II)")
When using PEBS sampling on Intel processors.
Doing simple profiling with:
$ perf record -g -e cycles:pp ...
Before:
1
On Wed, Apr 29, 2020 at 7:09 PM Andi Kleen wrote:
>
> > I was under the impression that perf script was generating one line
> > per sample. Otherwise, seems hard to parse.
>
> That's only true for simple cases. A lot of the extended output options
> have long generated multiple lines. And of cours
On Mon, Apr 27, 2020 at 7:47 PM Andi Kleen wrote:
>
> On Sat, Apr 18, 2020 at 04:19:08PM -0700, Stephane Eranian wrote:
> > When printing iregs, there was a double newline printed because
> > perf_sample__fprintf_regs() was printing its own and then at the
> > end of all
On Wed, Oct 23, 2019 at 4:02 AM Peter Zijlstra wrote:
>
> On Wed, Oct 23, 2019 at 12:30:03AM -0700, Stephane Eranian wrote:
> > On Mon, Oct 21, 2019 at 3:21 AM Peter Zijlstra wrote:
> > >
> > > On Thu, Oct 17, 2019 at 05:27:46PM -0700, Stephane Eranian wrote:
>
On Mon, Oct 21, 2019 at 3:21 AM Peter Zijlstra wrote:
>
> On Thu, Oct 17, 2019 at 05:27:46PM -0700, Stephane Eranian wrote:
> > This patch complements the following commit:
> > 7fa343b7fdc4 ("perf/core: Fix corner case in perf_rotate_context()")
> >
&
On Mon, Oct 21, 2019 at 3:06 AM Peter Zijlstra wrote:
>
> On Thu, Oct 17, 2019 at 05:27:46PM -0700, Stephane Eranian wrote:
> > @@ -2153,6 +2157,7 @@ __perf_remove_from_context(struct perf_event *event,
> > void *info)
> > {
> > unsign
On Thu, Oct 17, 2019 at 11:13 PM Song Liu wrote:
>
>
>
> > On Oct 17, 2019, at 5:27 PM, Stephane Eranian wrote:
> >
> > This patch complements the following commit:
> > 7fa343b7fdc4 ("perf/core: Fix corner case in perf_rotate_context()")
> >
&g
9uncore_cha_0/event=0x0/
(90.18%)
Signed-off-by: Stephane Eranian
---
kernel/events/core.c | 67
1 file changed, 67 insertions(+)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 9ec0
Alexander Shishkin
> Cc: Jiri Olsa
> Cc: Namhyung Kim
> Cc: Stephane Eranian
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Steve MacLean
Corrections are valid.
Acked-by: Stephane Eranian
> ---
> tools/perf/Documentation/jitdump-specification.txt | 4 ++--
>
On Fri, Sep 20, 2019 at 12:12 PM Jiri Olsa wrote:
>
> On Tue, Sep 03, 2019 at 11:26:03PM -0700, Stephane Eranian wrote:
> > Now that the default perf_events paranoid level is set to 2, a regular user
> > cannot monitor kernel level activity anymore. As such, with the fol
space.
Signed-off-by: Stephane Eranian
---
tools/perf/util/evsel.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 85825384f9e8..3cbe06fdf7f7 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
On Tue, Sep 3, 2019 at 11:26 PM Stephane Eranian wrote:
>
> Now that the default perf_events paranoid level is set to 2, a regular user
> cannot monitor kernel level activity anymore. As such, with the following
> cmdline:
>
> $ perf record -e cycles date
>
> The perf to
: Stephane Eranian
---
tools/perf/util/evsel.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 85825384f9e8..3cbe06fdf7f7 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -2811,9 +2811,11 @@ bool
Andi,
On Fri, Aug 30, 2019 at 5:31 PM Andi Kleen wrote:
>
> > the same manner. It would greatly simplify the kernel implementation.
>
> I tried that originally. It was actually more complicated.
>
> You can't really do deltas on raw metrics, and a lot of the perf
> infrastructure is built around
On Fri, Aug 30, 2019 at 3:49 PM Namhyung Kim wrote:
>
> On Fri, Aug 30, 2019 at 4:35 PM Peter Zijlstra wrote:
> >
> > On Fri, Aug 30, 2019 at 12:46:51PM +0900, Namhyung Kim wrote:
> > > Hi Peter,
> > >
> > > On Wed, Aug 28, 2019 at 6:45 PM Peter Zijlstra
> > > wrote:
> > > >
> > > > On Wed, Aug
Hi,
On Mon, Aug 26, 2019 at 7:48 AM wrote:
>
> From: Kan Liang
>
> Intro
> =
>
> Icelake has support for measuring the four top level TopDown metrics
> directly in hardware. This is implemented by an additional "metrics"
> register, and a new Fixed Counter 3 that measures pipeline "slots".
>
On Wed, Aug 28, 2019 at 5:47 AM Peter Zijlstra wrote:
>
> On Mon, Aug 26, 2019 at 02:59:15PM -0500, Kim Phillips wrote:
> > The core AMD PMU has a 4-bit wide per-cycle increment for each
> > performance monitor counter. That works for most counters, but
> > now with AMD Family 17h and above proce
Hi,
When trying the following command line with perf from tip,git, I got:
$ perf record --group -c 10 -e '{branch-misses,branches}' -a -o -
sleep 1| perf report --no-group -F sample,cpu,period -i -
# To display the perf.data header info, please use
--header/--header-only options.
#
Segmentati
On Mon, Jul 15, 2019 at 12:59 AM Jiri Olsa wrote:
>
> On Sun, Jul 14, 2019 at 02:36:42PM -0700, Stephane Eranian wrote:
> > On Sun, Jul 14, 2019 at 1:55 PM Jiri Olsa wrote:
> > >
> > > On Sun, Jul 14, 2019 at 10:44:36PM +0200, Jiri Olsa wrote:
> > > >
On Sun, Jul 14, 2019 at 1:55 PM Jiri Olsa wrote:
>
> On Sun, Jul 14, 2019 at 10:44:36PM +0200, Jiri Olsa wrote:
> > On Wed, Jul 10, 2019 at 01:45:40PM -0700, Numfor Mbiziwo-Tiapo wrote:
> > > When perf stat is called with event groups and the repeat option,
> > > a segfault occurs because the cpu
ock problem.
>
> Can you tell my why am I actually reviewing patches and spending time on
> this when the result is ignored anyway?
>
> I also tried to figure out why you went away from the IPI broadcast
> design. The only information I found is:
>
> Changes vs. v1:
>
&g
On Thu, Jun 13, 2019 at 9:13 AM Liang, Kan wrote:
>
>
>
> On 6/1/2019 4:27 AM, Ian Rogers wrote:
> > Currently perf_rotate_context assumes that if the context's nr_events !=
> > nr_active a rotation is necessary for perf event multiplexing. With
> > cgroups, nr_events is the total count of events
Commit-ID: 23e3983a466cd540ffdd2bbc6e0c51e31934f941
Gitweb: https://git.kernel.org/tip/23e3983a466cd540ffdd2bbc6e0c51e31934f941
Author: Stephane Eranian
AuthorDate: Mon, 20 May 2019 17:52:46 -0700
Committer: Ingo Molnar
CommitDate: Tue, 21 May 2019 10:25:29 +0200
perf/x86/intel/ds
a cmdline such as:
$ perf top -e cycles:pp
would fail with EINVAL.
This patch fixes this issue by properly using INTEL_FLAGS_UEVENT_CONSTRAINT()
when needed in the PEBS constraint tables.
In v2:
- add fixes for Core2, Nehalem, Silvermont, and Atom
Reported-by: Ingo Molnar
Signed-off-by
a cmdline such as:
$ perf top -e cycles:pp
would fail with EINVAL.
This patch fixes this issue by properly using INTEL_FLAGS_UEVENT_CONSTRAINT()
when needed in the PEBS constraint tables.
Reported-by: Ingo Molnar
Signed-off-by: Stephane Eranian
---
arch/x86/events/intel
On Sat, May 18, 2019 at 2:16 PM Ingo Molnar wrote:
>
>
> * tip-bot for Stephane Eranian wrote:
>
> > Commit-ID: 6b89d4c1ae8596a8c9240f169ef108704de373f2
> > Gitweb:
> > https://git.kernel.org/tip/6b89d4c1ae8596a8c9240f169ef108704de373f2
> > Author: S
Commit-ID: c7a286577d7592720c2f179aadfb325a1ff48c95
Gitweb: https://git.kernel.org/tip/c7a286577d7592720c2f179aadfb325a1ff48c95
Author: Stephane Eranian
AuthorDate: Mon, 13 May 2019 17:34:00 -0700
Committer: Ingo Molnar
CommitDate: Tue, 14 May 2019 09:07:58 +0200
perf/x86/intel: Allow
means that in watermark mode, PEBS multi-entry is also disabled which is not the
intent. This patch fixes this by checking is watermark mode is enabled.
Signed-off-by: Stephane Eranian
Change-Id: I8362bbcf9035c860b64b4c2e8faf310ebd74c234
---
arch/x86/events/intel/core.c | 2 +-
1 file changed, 1
Commit-ID: 6b89d4c1ae8596a8c9240f169ef108704de373f2
Gitweb: https://git.kernel.org/tip/6b89d4c1ae8596a8c9240f169ef108704de373f2
Author: Stephane Eranian
AuthorDate: Thu, 9 May 2019 14:45:56 -0700
Committer: Ingo Molnar
CommitDate: Fri, 10 May 2019 08:04:17 +0200
perf/x86/intel: Fix
have *UEVENT*.
This bug fixes the issue by checking only the event code in the mask.
Both single and range version are modified.
Signed-off-by: Stephane Eranian
---
arch/x86/events/perf_event.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/perf_event.h b
Vince
On Tue, Apr 16, 2019 at 11:06 PM Ingo Molnar wrote:
>
>
> * Vince Weaver wrote:
>
> > On Tue, 16 Apr 2019, tip-bot for Stephane Eranian wrote:
> >
> > > Commit-ID: f447e4eb3ad1e60d173ca997fcb2ef2a66f12574
> > > Git
Commit-ID: f447e4eb3ad1e60d173ca997fcb2ef2a66f12574
Gitweb: https://git.kernel.org/tip/f447e4eb3ad1e60d173ca997fcb2ef2a66f12574
Author: Stephane Eranian
AuthorDate: Mon, 8 Apr 2019 10:32:52 -0700
Committer: Ingo Molnar
CommitDate: Tue, 16 Apr 2019 12:19:35 +0200
perf/x86/intel: Force
Commit-ID: c68d224e5ed15605e651e2482c6ffd95915ddf58
Gitweb: https://git.kernel.org/tip/c68d224e5ed15605e651e2482c6ffd95915ddf58
Author: Stephane Eranian
AuthorDate: Mon, 8 Apr 2019 10:32:51 -0700
Committer: Ingo Molnar
CommitDate: Tue, 16 Apr 2019 12:19:34 +0200
perf/core: Add
On Mon, Apr 15, 2019 at 8:57 AM Peter Zijlstra wrote:
>
> On Mon, Apr 08, 2019 at 10:32:52AM -0700, Stephane Eranian wrote:
> > +static ssize_t set_sysctl_tfa(struct device *cdev,
> > + struct device_attribute *attr,
> > +
56,978 branches
13.022630819125,109,380,471 branches
14.023114989125,133,140,817 branches
14.023501880125,133,785,858 branches
14.023868339125,133,852,700 branches
Signed-off-by: Stephane Eranian
Change-Id: Ib443265edce31b93ca4d10fe7695c05d00
This patch add perf_ctx_resched() a global function that can be called
to force rescheduling of events based on event types. The function locks
both cpuctx and task_ctx internally. This will be used by a subsequent patch.
Signed-off-by: Stephane Eranian
Change-Id
switched from ksttoul() to kstrtobool() and added the proper
get_online_cpus()/put_online_cpus().
Signed-off-by: Stephane Eranian
Stephane Eranian (2):
perf/core: add perf_ctx_resched() as global function
perf/x86/intel: force resched when TFA sysctl is modified
arch/x86/events/core.c | 4
On Fri, Apr 5, 2019 at 1:26 PM Peter Zijlstra wrote:
>
> On Fri, Apr 05, 2019 at 10:00:03AM -0700, Stephane Eranian wrote:
>
> > > > +static void update_tfa_sched(void *ignored)
> > > > +{
> > > > + struct cpu_hw_events *cpuc = this_cpu_ptr(&
On Fri, Apr 5, 2019 at 12:13 AM Peter Zijlstra wrote:
>
> On Thu, Apr 04, 2019 at 11:32:19AM -0700, Stephane Eranian wrote:
> > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> > index a4b7711ef0ee..8d356c2096bc 100644
> > --- a/arch/x86/event
56,978 branches
13.022630819125,109,380,471 branches
14.023114989125,133,140,817 branches
14.023501880125,133,785,858 branches
14.023868339125,133,852,700 branches
Signed-off-by: Stephane Eranian
---
arch/x86/events/core.c | 4 +++
ar
This patch renames ctx_resched() to perf_ctx_resched() and makes
the function globally accessible. This is to prepare for the next
patch which needs to call this function from arch specific code.
Signed-off-by: Stephane Eranian
---
include/linux/perf_event.h | 12
kernel/events
open to suggestions here.
Signed-off-by: Stephane Eranian
Stephane Eranian (3):
perf/core: make perf_ctx_*lock() global inline functions
perf/core: make ctx_resched() a global function
perf/x86/intel: force resched when TFA sysctl is modified
arch/x86/events/core.c | 4 +++
arch/x86
This patch makes the perf_ctx_lock()/perf_ctx_unlock() inlined functions
available throughout the perf_events code and not just in kernel/events/core.c
This will help with the next patch.
Signed-off-by: Stephane Eranian
---
include/linux/perf_event.h | 16
kernel/events/core.c
Commit-ID: 583feb08e7f7ac9d533b446882eb3a54737a6dbb
Gitweb: https://git.kernel.org/tip/583feb08e7f7ac9d533b446882eb3a54737a6dbb
Author: Stephane Eranian
AuthorDate: Wed, 6 Mar 2019 11:50:48 -0800
Committer: Ingo Molnar
CommitDate: Wed, 3 Apr 2019 09:57:43 +0200
perf/x86/intel: Fix
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