The following commit has been merged into the perf/urgent branch of tip: Commit-ID: fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27 Gitweb: https://git.kernel.org/tip/fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27 Author: Stephane Eranian <eran...@google.com> AuthorDate: Thu, 26 Nov 2020 20:09:22 +09:00 Committer: Peter Zijlstra <pet...@infradead.org> CommitterDate: Thu, 03 Dec 2020 10:00:26 +01:00
perf/x86/intel: Check PEBS status correctly The kernel cannot disambiguate when 2+ PEBS counters overflow at the same time. This is what the comment for this code suggests. However, I see the comparison is done with the unfiltered p->status which is a copy of IA32_PERF_GLOBAL_STATUS at the time of the sample. This register contains more than the PEBS counter overflow bits. It also includes many other bits which could also be set. Signed-off-by: Namhyung Kim <namhy...@kernel.org> Signed-off-by: Stephane Eranian <eran...@google.com> Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org> Link: https://lkml.kernel.org/r/20201126110922.317681-2-namhy...@kernel.org --- arch/x86/events/intel/ds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 89dba58..485c506 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1916,7 +1916,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d * that caused the PEBS record. It's called collision. * If collision happened, the record will be dropped. */ - if (p->status != (1ULL << bit)) { + if (pebs_status != (1ULL << bit)) { for_each_set_bit(i, (unsigned long *)&pebs_status, size) error[i]++; continue;
