+ YC Lin in loop,
--
>
> Subject
>
> [PATCH v4 6/7] spi: mxic: patch for octal DTR mode support
>
> Driver patch for octal 8D-8D-8D mode support.
>
> Signed-off-by: Mason Yang
> ---
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information
and/or persona
+ YC Lin in loop,
--
>
> Subject
>
> [PATCH v4 5/7] mtd: spi-nor: core: execute command sequences to change
octal DTR mode
>
> Execute command sequences to change octal DTR mode.
>
> Signed-off-by: Mason Yang
> ---
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confid
+ YC Lin in loop,
--
> Subject
>
> [PATCH v4 3/7] mtd: spi-nor: sfdp: parse command sequences to change
octal DTR mode
>
> A set of simple command sequences is provided which can be executed
> directly by the host controller to enable octal DTR mode.
>
> Each command sequence is 8 per byte f
+ YC Lin in loop,
YC(ycl...@mxic.com.tw)will take over this patch set.
> Subject
>
> [PATCH v4 0/7] mtd: spi-nor: add xSPI Octal DTR support
>
> Hello,
>
> JESD216C has defined specification for Octal 8S-8S-8S and 8D-8D-8D.
> Based on JEDEC216C Basic Flash Parameter Table (BFPT) driver extr
+ YC Lin in loop,
>
> Subject
>
> [PATCH v4 1/7] mtd: spi-nor: sfdp: get octal mode maximum speed from
BFPT
>
> Get maximum operation speed of device in octal mode from
> BFPT 20th DWORD.
>
> Signed-off-by: Mason Yang
> ---
CONFIDENTIALITY NOTE:
This e-mail and any attachments may conta
+ YC Lin in loop,
--
>
> Subject
>
> [PATCH v4 2/7] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
>
> JESD251, xSPI profile 1.0 table supports octal DTR mode.
> Extract information like the fast read opcode, dummy cycles for various
> frequencies, the number of dummy cycles needed for a Re
+ YC Lin in loop,
--
>
> Subject
>
> [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read &
write support
>
> Configuration register 2 is to set the device operation condition like
> STR or DTR mode at address offset 0 and DQS mode at address offset
0x200.
>
> Each device h
+ YC Lin in loop,
--
>
> Subject
>
> [PATCH v4 7/7] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports for
> Macronix mx25uw51245g
>
> Macronix mx25uw51245g is a SPI NOR that supports 1-1-1/8-8-8 mode.
>
> Correct the dummy cycles to device for various frequencies
> after xSPI profile 1.0
> > > >
> > > > +#define MXIC_CR2_DUMMY_SET_ADDR 0x300
> > > > +
> > > > +/* Fixup the dummy cycles to device and setup octa_dtr_enable()
*/
> > > > +static void mx25uw51245g_post_sfdp_fixups(struct spi_nor *nor)
> > > > +{
> > > > + struct spi_nor_flash_parameter *params = nor->params;
> > >
Hi Pratyush,
> Subject
>
> Re: [PATCH v4 7/7] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports
for
> Macronix mx25uw51245g
>
> On 29/05/20 03:36PM, Mason Yang wrote:
> > Macronix mx25uw51245g is a SPI NOR that supports 1-1-1/8-8-8 mode.
> >
> > Correct the dummy cycles to device for va
Hi Pratyush,
>
> Subject
>
> Re: [PATCH v4 1/7] mtd: spi-nor: sfdp: get octal mode maximum speed from
BFPT
>
> On 29/05/20 03:36PM, Mason Yang wrote:
> > Get maximum operation speed of device in octal mode from
> > BFPT 20th DWORD.
>
> I don't like the idea of getting the maximum operation
Hi Boris,
> >
> >
> > Summary of change log
> > v3:
> > Add support command sequences to change octal DTR mode and based on
> > part of Pratyush's patches set.
> >
> > v2:
> > Parse BFPT & xSPI table for Octal 8D-8D-8D mode parameters and enable
Octal
> > mode in spi_nor_late_init_params().
Hi Pratyush,
> +/**
> + * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem
op.
> + * @nor: pointer to a 'struct spi_nor'
> + * @op: pointer to the 'struct spi_mem_op' whose properties
> + * need to be initialized.
> + * @proto: the protocol from which
Hi Pratyush,
> @@ -311,6 +313,7 @@ struct flash_info {
> * BP3 is bit 6 of status register.
> * Must be used with SPI_NOR_4BIT_BP.
> */
> +#define SPI_NOR_OCTAL_DTR_READ BIT(19) /* Flash supports octal DTR
Read. */
#define SPI_NOR_OCTAL_DTR
Hi Pratyush,
Given cmd.nbytes a initial value & check it !
>
> [PATCH v5 01/19] spi: spi-mem: allow specifying whether an op is DTR or
not
>
> Each phase is given a separate 'dtr' field so mixed protocols like
> 4S-4D-4D can be supported.
>
> Signed-off-by: Pratyush Yadav
> ---
> drivers/
Hi Pratyush,
> >
> > > > > +/**
> > > > > + * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
> > > > > + * @nor: pointer to a 'struct spi_nor'
> > > > > + * @param_header: pointer to the 'struct
sfdp_parameter_header'
> > > > describing
> > > > > + * the 4-Byte Ad
Hi Pratyush,
> > > +/**
> > > + * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
> > > + * @nor: pointer to a 'struct spi_nor'
> > > + * @param_header: pointer to the 'struct sfdp_parameter_header'
> > describing
> > > + * the 4-Byte Address Instruction Table lengt
Hi Pratyush,
> +/**
> + * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
> + * @nor: pointer to a 'struct spi_nor'
> + * @param_header: pointer to the 'struct sfdp_parameter_header'
describing
> + * the 4-Byte Address Instruction Table length and version.
> + * @par
Hi Pratyush,
> > > > I can't apply your patches to enable xSPI Octal mode for
> > > > mx25uw51245g because your patches set up Octal protocol first and
> > > > then using Octal protocol to write Configuration Register 2(CFG
> > > > Reg2). I think driver
> > > > should write CFG Reg2 in SPI 1-
Hi Boris,
> > > >
> > > > To clarify a bit more, the idea is that we transmit the opcode MSB
> > > > first, just we do for the address. Assume we want to issue the
command
> > > > 0x05. In 1S mode, we set cmd.opcode to 0x05. Here cmd.nbytes == 1.
Treat
> > >
> > > > is as a 1-byte value
Hi Vignesh,
> >>>
> >>> Our mx25uw51245g supports BFPT DWORD-18,19 and 20 data and xSPI
> > profile
> >>> 1.0,
> >>> and it comply with BFPT DWORD-19, octal mode enable sequences by
write
> > CFG
> >>> Reg2
> >>> with instruction 0x72. Therefore, I can't apply your patches.
> >>
> >> I did
Hi Pratyush,
> > > > >
> > > > > I posted a re-roll of my series here [0]. Could you please base
your
> >
> > > > > changes on top of it? Let me know if the series is missing
something
> > you
> > > >
> > > > > need.
> > > > >
> > > > > [0]
> > > >
> >
https://lore.kernel.org/linux-m
Hi Pratyush,
> > > > On Tue, 21 Apr 2020 14:39:42 +0800
> > > > Mason Yang wrote:
> > > >
> > > > > Hello,
> > > > >
> > > > > This is repost of patchset from Boris Brezillon's
> > > > > [RFC,00/18] mtd: spi-nor: Proposal for 8-8-8 mode support [1].
> > > >
> > > > I only quickly went thro
Hi Boris,
> > > > On Tue, 21 Apr 2020 14:39:42 +0800
> > > > Mason Yang wrote:
> > > >
> > > > > Hello,
> > > > >
> > > > > This is repost of patchset from Boris Brezillon's
> > > > > [RFC,00/18] mtd: spi-nor: Proposal for 8-8-8 mode support [1].
> > > >
> > > > I only quickly went through
Hi Tudor,
>
> 2020/04/28 下午 04:39
>
> To
>
> ,
>
> cc
>
> , ,
,
> , ,
>
> Subject
>
> Re: [PATCH v2 0/2] mtd: spi-nor: macronix: Add support for
mx25l512/mx25u512
>
> On Thursday, April 23, 2020 11:38:41 AM EEST Mason Yang wrote:
> > EXTERNAL EMAIL: Do not click links or open attach
Hi Boris,
>
> Assign mtd lock/unlock/is_locked hooks to the generic wrappers in
> nand_scan_tail():
>
>mtd->_lock = nand_lock;
>mtd->_unlock = nand_unlock;
>mtd->_is_locked = nand_is_locked;
>
> Seriously, we've almost implemented the thing for you with all the
> details we've giv
Hi Boris,
> > > > > > Then fill-in these two hooks from the manufacturer code,
without
> > the
> > > > > > postponed init.
> > > > > >
> > > > >
> > > > > But in the final of nand_scan_tail(), mtd->_lock/_unlock will be
> > > > > filled by NULL, right ?
> > > >
> > > > The NAND core shou
Hi Miquel,
> > > > Then fill-in these two hooks from the manufacturer code, without
the
> > > > postponed init.
> > > >
> > >
> > > But in the final of nand_scan_tail(), mtd->_lock/_unlock will be
> > > filled by NULL, right ?
> >
> > The NAND core should set mtd->_lock/_unlock() to NAND sp
Hi Miquel,
> >
> > > > > > + nand_select_target(chip, 0);
> > > > >
> > > > > On several NAND controllers there is no way to act on the CS
line
> > > > > without actually writing bytes to the NAND chip. So basically
this
> > > > > is very likely to not work.
> > > >
> > > > any other wa
Hi Miquel,
> > > >
> > > > > Macronix AC series support using SET/GET_FEATURES to change
> > > > > Block Protection and Unprotection.
> > > > >
> > > > > MTD default _lock/_unlock function replacement by manufacturer
> > > > > postponed initialization.
> > > >
> > > > Why would we do that?
>
Hi Boris,
> > > > + nand_select_target(chip, 0);
> > >
> > > On several NAND controllers there is no way to act on the CS line
> > > without actually writing bytes to the NAND chip. So basically this
> > > is very likely to not work.
> >
> > any other way to make it work ? GPIO ?
> > or
Hi Miquel,
> > changelog
> > v3:
> > To enable randomizer by specific DT property in children nodes,
> > mxic,enable-randomizer-otp;
> >
> > v2:
> > To enable randomizer by checking chip options NAND_NO_SUBPAGE_WRITE
> >
> > v1:
> > To enable randomizer by sys-fs
> >
> > Signed-off-by: Mason
Hi Miquel,
> >
> > > Macronix AC series support using SET/GET_FEATURES to change
> > > Block Protection and Unprotection.
> > >
> > > MTD default _lock/_unlock function replacement by manufacturer
> > > postponed initialization.
> >
> > Why would we do that?
> >
> > Anyway your solution loo
Hi Miquel,
> > +int nand_power_down_op(struct nand_chip *chip)
> > +{
> > + int ret;
> > +
> > + if (nand_has_exec_op(chip)) {
> > + struct nand_op_instr instrs[] = {
> > + NAND_OP_CMD(NAND_CMD_POWER_DOWN, 0),
> > + };
> > +
> > + struct nand_operation op = NAND_OPE
Hi Richard,
> Subject
>
> Re: [PATCH] Add support for Macronix NAND randomizer
>
> On Mon, Sep 2, 2019 at 8:54 AM wrote:
> > > > nand@0 {
> > > > reg = <0>;
> > > > nand-reliability = "randomizer";
> > >
> > >
Hi Miquel,
> > > >
> > > > If subpage write not available with hardware ECC, for example,
> > > > NAND chip options NAND_NO_SUBPAGE_WRITE be set in driver and
> > > > randomizer function is recommended for high-reliability.
> > > > Driver checks byte 167 of Vendor Blocks in ONFI parameter pa
Hi Miquel,
> >
> > If subpage write not available with hardware ECC, for example,
> > NAND chip options NAND_NO_SUBPAGE_WRITE be set in driver and
> > randomizer function is recommended for high-reliability.
> > Driver checks byte 167 of Vendor Blocks in ONFI parameter page table
> > to see i
Hi Miquel,
>
> Re: [PATCH] Add support for Macronix NAND randomizer
>
> Hi Mason,
>
> masonccy...@mxic.com.tw wrote on Mon, 26 Aug 2019 10:52:31 +0800:
>
> > Hi Miquel,
> > >
> > > Mason Yang wrote on Tue, 20 Aug 2019
13:53:48
> > > +0800:
> > >
> > > > Macronix NANDs support randomizer
Hi Miquel,
>
> Mason Yang wrote on Tue, 20 Aug 2019 13:53:48
> +0800:
>
> > Macronix NANDs support randomizer operation for user data scrambled,
> > which can be enabled with a SET_FEATURE.
> >
> > User data written to the NAND device without randomizer is still
readable
> > after randomizer
Hi Boris,
> > +
> > +static int mxic_nfc_wait_ready(struct nand_chip *chip)
> > +{
> > + struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
> > + u32 sts;
> > +
> > + return readl_poll_timeout(nfc->regs + INT_STS, sts,
> > + sts & INT_RDY_PIN, 0, USEC_PER_SEC);
>
Hi Boris,
> > +
> > +struct mxic_nand_ctlr {
> > + struct clk *ps_clk;
> > + struct clk *send_clk;
> > + struct clk *send_dly_clk;
> > + void __iomem *regs;
> > + struct nand_controller controller;
> > + struct device *dev;
> > + void *priv;
>
> Looks like this priv field point to
Hi Sergei,
> > Add a driver for Renesas R-Car Gen3 RPC-IF SPI controller.
> >
> > Signed-off-by: Mason Yang
> > Signed-off-by: Sergei Shtylyov
> [...]
> > diff --git a/drivers/spi/spi-renesas-rpc.c
b/drivers/spi/spi-renesas-rpc.c
> > new file mode 100644
> > index 000..648d14e
> > --- /
Hi Miquel,
> > Document the bindings used by the Macronix raw NAND controller.
> >
> > Signed-off-by: Mason Yang
> > ---
> > Documentation/devicetree/bindings/mtd/mxic-nand.txt | 19
+++
> > 1 file changed, 19 insertions(+)
> > create mode 100644
Documentation/devicetree/bi
Hi Boris,
> On Thu, 1 Aug 2019 11:55:10 +0800
> Mason Yang wrote:
>
> > Document the bindings used by the Macronix raw NAND controller.
> >
> > Signed-off-by: Mason Yang
> > ---
> > Documentation/devicetree/bindings/mtd/mxic-nand.txt | 19
+++
> > 1 file changed, 19 insert
Hi Geert,
> On Mon, Jul 29, 2019 at 11:34 AM wrote:
> > > On Fri, Jul 26, 2019 at 4:19 AM Mason Yang
> > wrote:
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt
> > > > @@ -0,0 +1,46 @@
> > >
> > > [...]
> > >
> > > > +- flash: should be represente
Hi Geert,
> On Fri, Jul 26, 2019 at 4:19 AM Mason Yang
wrote:
> > Dcument the bindings used by the Renesas R-Car Gen3 RPC-IF controller.
>
> Document
Oops, sorry !
>
> >
> > Signed-off-by: Mason Yang
> > Reviewed-by: Rob Herring
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/b
Hi Rob,
>
> Re: [PATCH v5 2/2] dt-bindings: mtd: Document Macronix raw NAND
controller bindings
>
> On Wed, Jul 03, 2019 at 03:15:44PM +0800, Mason Yang wrote:
> > Document the bindings used by the Macronix raw NAND controller.
> >
> > Signed-off-by: Mason Yang
> > ---
> > Documentation/d
Hi Geert,
Thanks for your review!
Will fix it as
+Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
+-
+
+Required properties:
+- compatible: should be an SoC-specific compatible value, followed by
+
Hi Sergei,
> > Document the bindings used by the Macronix raw NAND controller.
> >
> > Signed-off-by: Mason Yang
> > ---
> > Documentation/devicetree/bindings/mtd/mxic-nand.txt | 20
> > 1 file changed, 20 insertions(+)
> > create mode 100644
Documentation/devicetre
Hi Miquel,
> > Add a driver for Macronix raw NAND controller.
>
> Could you pass userspace major MTD tests and can you attach/mount/edit
> a UBI/UBIFS storage?
The other userspace MTD tests are passed.
nandwrite, nanddump and nandtest.
i.e.,
zynq> ./nandtest -k /dev/mtd1
ECC corrections: 0
EC
Hi Miquel,
> > >
> > > > > > +- interrupts: interrupt line connected to this NAND
controller
> > > > > > +- clock-names: should contain "ps_clk", "send_clk" and
> > "send_dly_clk"
> > > > > > +- clocks: should contain 3 entries for the "ps_clk",
"send_clk"
> > and
> > > > > > +"send_dly
Hi Miquel,
>
> Please always Cc: Rob (robh...@kernel.org) when you send bindings
> related patches.
Understood. thanks for your remind.
> >
> > >
> > > > +- reg: should contain 1 entrie for the registers
> > >
> > >entry
> > >
> > > > +- reg-names: should con
Hi Miquel,
> >
> > > > Add a driver for Macronix raw NAND controller.
> > >
> > > Could you pass userspace major MTD tests and can you
attach/mount/edit
> > > a UBI/UBIFS storage?
> >
> > mtd_debug passed and using dd utility to read and write
> > with md5sum checking passed.
>
> Please
Hi Miquel,
> > Document the bindings used by the Macronix raw NAND controller.
> >
> > Signed-off-by: Mason Yang
> > ---
> > .../devicetree/bindings/mtd/mxic-nand.txt | 26
++
> > 1 file changed, 26 insertions(+)
> > create mode 100644
Documentation/devicetree/
Hi Miquel,
> > Add a driver for Macronix raw NAND controller.
>
> Could you pass userspace major MTD tests and can you attach/mount/edit
> a UBI/UBIFS storage?
mtd_debug passed and using dd utility to read and write
with md5sum checking passed.
UBI/UBIFS testing is not yet. will do it.
>
Hi Vignesh,
>
> Subject
>
> [PATCH v7 3/5] mtd: Add support for HyperBus memory devices
>
> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
> Bus interface between a host system master and one or more slave
> interfaces. HyperBus is used to connect microprocessor, micro
Hi Miquel,
> > > > > > > > > How to make all #CS keep high for NAND to enter
> > > > > > > > > low-power standby mode if driver don't use
> > "legacy.select_chip()"
> > > > > ?
> > > > > > > >
> > > > > > > > See commit 02b4a52604a4 ("mtd: rawnand: Make
->select_chip()
> > > > > optiona
Hi Boris,
> > > > > Re: [PATCH v3 2/4] mtd: rawnand: Add Macronix MX25F0A NAND
> > controller
> > > > >
> > > > > On Tue, 18 Jun 2019 08:14:36 +0200
> > > > > Boris Brezillon wrote:
> > > > >
> > > > > > > > > > >
> > > > > > > > > > > How to make all #CS keep high for NAND to enter
> > >
Hi Boris,
> > >
> > > Re: [PATCH v3 2/4] mtd: rawnand: Add Macronix MX25F0A NAND
controller
> > >
> > > On Tue, 18 Jun 2019 08:14:36 +0200
> > > Boris Brezillon wrote:
> > >
> > > > > > > > >
> > > > > > > > > How to make all #CS keep high for NAND to enter
> > > > > > > > > low-power sta
Hi Miquel,
> > >
> > > Re: [PATCH v3 2/4] mtd: rawnand: Add Macronix MX25F0A NAND
controller
> > >
> > > On Tue, 18 Jun 2019 08:14:36 +0200
> > > Boris Brezillon wrote:
> > >
> > > > > > > > >
> > > > > > > > > How to make all #CS keep high for NAND to enter
> > > > > > > > > low-power st
Hi Boris,
>
> Re: [PATCH v3 2/4] mtd: rawnand: Add Macronix MX25F0A NAND controller
>
> On Tue, 18 Jun 2019 08:14:36 +0200
> Boris Brezillon wrote:
>
> > > > > > >
> > > > > > > How to make all #CS keep high for NAND to enter
> > > > > > > low-power standby mode if driver don't use
"legac
Hi Marek,
> Subject
>
> Re: [PATCH v13 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF
> controller bindings
>
> On 6/6/19 9:40 AM, masonccy...@mxic.com.tw wrote:
> [...]
>
> > RPC-IF works either in SPI or HyperFlash is decided by external
hardware
> > pins
> > configuration
Hi Miquel,
>
> > > > > > > > +static void mxic_nand_select_chip(struct nand_chip *chip,
int
> >
> > > > chipnr)
> > > > > > >
> > > > > > > _select_target() is preferred now
> > > > > >
> > > > > > Do you mean I implement mxic_nand_select_target() to control
#CS ?
> > > > > >
> > > > >
Hi Jones,
> Subject
>
> Re: [PATCH v13 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF
> controller bindings
>
> Hello!
>
> On 06/03/2019 04:04 PM, Lee Jones wrote:
>
> >>> Document the bindings used by the Renesas R-Car Gen3 RPC-IF
controller.
> >>>
> >>> Signed-off-by: Mason
Hi Jones,
> > +static int rpc_mfd_probe(struct platform_device *pdev)
>
> Remove the "mfd" from the nomenclature.
okay, will fix.
>
> > + struct device_node *flash;
> > + const struct mfd_cell *cell;
> > + struct resource *res;
> > + struct rpc_mfd *rpc;
> > + void __iomem *base;
>
Hi Miquel,
> > > > > > +static void mxic_nand_select_chip(struct nand_chip *chip, int
> > chipnr)
> > > > >
> > > > > _select_target() is preferred now
> > > >
> > > > Do you mean I implement mxic_nand_select_target() to control #CS ?
> > > >
> > > > If so, I need to call mxic_nand_selec
Hi Miquel,
> > >
> > > > +
> > > > + ret = nand_get_features(chip, feature_addr, feature);
> > > > + if (ret || feature[0] != mode)
> > > > + pr_err("Failed to verify read retry moded:%d(%d)\n",
> > > > +mode, feature[0]);
> > >
> > > if ret == 0 but featur
Hi Sergei,
> On 05/21/2019 10:19 AM, Mason Yang wrote:
>
> > Document the bindings used by the Renesas R-Car Gen3 RPC-IF
controller.
> >
> > Signed-off-by: Mason Yang
> > ---
> > .../devicetree/bindings/mfd/renesas-rpc-if.txt | 65
++
> > 1 file changed, 65 insertio
Hi Miquel,
> >
> > > > +
> > > > +static void mxic_nand_select_chip(struct nand_chip *chip, int
chipnr)
> > >
> > > _select_target() is preferred now
> >
> > Do you mean I implement mxic_nand_select_target() to control #CS ?
> >
> > If so, I need to call mxic_nand_select_target( ) to cont
Hi Miquel,
> > Add support for Macronix NAND read retry.
> >
> > Macronix NANDs support specific read operation for data recovery,
> > which can be enabled/disabled with a SET/GET_FEATURE.
> > Driver checks byte 167 of Vendor Blocks in ONFI parameter page table
> > to see if this high-reliabil
Hi Geert,
>
> On Mon, May 20, 2019 at 9:24 AM wrote:
> > > >>> - clocks: should contain 1 entries for the module's clock
> > > >>> - clock-names: should contain "rpc"
> > > >>
> > > >>I suspect we'd need the RPC/RPCD2 clocks mentioned as well
(not
> > sure
> > > > yet)...
> > > >
> >
Hi Sergei,
> >>> -->
> >>>
> >>> Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> >>> -
> >>>
> >>> RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
Hi Miquel,
> > +
> > +static void mxic_nand_select_chip(struct nand_chip *chip, int chipnr)
>
> _select_target() is preferred now
Do you mean I implement mxic_nand_select_target() to control #CS ?
If so, I need to call mxic_nand_select_target( ) to control #CS ON
and then #CS OFF in _exec_op(
Hi Miquel,
Sorry, previous email missed this mxic_nand_data_xfer() reply.
This Flash Memory Controller implemented the Buffer read-write data
transfer
for SPI mode and raw NAND mode.
That is each time driver write to the transmit of the TXD port and the
data
is shifted out, new data is rec
Hi Miquel,
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (C) 2019 Macronix International Co., Ltd.
> > +//
> > +// Authors:
> > +// Mason Yang
> > +// zhengxunli
>
> This is not a valid name.
>
> Also if he appears here I suppose he should be credited in the
> module
Hi Miquel,
> > +Macronix MX25F0A MultiFunction Device Tree Bindings
> > +
> > +
> > +MX25F0A is a MultiFunction Device with SPI and raw NAND, which
> > +supports either spi host controller or raw nand controller.
>
> Acronyms in plain English
Hi Miquel,
> > Add a driver for Macronix MX25F0A multifunction device controller.
> >
> > Signed-off-by: Mason Yang
> > ---
> > drivers/mfd/Kconfig | 9 ++
> > drivers/mfd/Makefile | 1 +
> > drivers/mfd/mxic-mx25f0a.c | 84 +++
> > includ
Hi Jones,
> > +
> > +struct rpc_spi {
> > + struct rpc_mfd *mfd;
>
> The term MFD isn't a real thing. What you're obtaining below is
> driver data and is normally articulated as 'ddata' in drivers.
yes, it's just imply that data is from MFD.
Should I rename "mfd" ?
>
> > + u32 cur_speed
Hi Thomas,
>
> > > >
---
> > > > static void macronix_nand_onfi_init(struct nand_chip *chip)
> > > > {
> > > > struct nand_parameters *p = &chip->parameters;
> > > > struct nand_onfi_vendor_macronix *mxic = (
Hi Sergei,
> >
> >Could you please indent with 1 or 2 tabs where you used 8 or 16
spaces?
Sorry, I just copy this new DTS from git to my Notes email system,
therefore, the "tabs space" is not alignment with original file.
>
> Patch new DTS to
> =
Hello,
> >> There's precedence for such constructs being an MFD: please see
> >> drivers/mfd/at91-usart.c, which registers a single MFD cell for
either
> >> serial or SPI.
>
>Thanks fir your example, Geert! :-)
>
> > okay, many thanks for your information.
> >
> > How about to patch RPF
Hi Geert,
> Subject
>
> Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF
MFD bindings
>
> Hi Mason,
>
> Note that if you send multipart/text+html emails, they will be dropped
silently
> by most Linux mailing lists.
> Hence I'm quoting your last email fully, to give o
Hi Miquel,
> > > > > > +
> > > > > > + if (mxic->reliability_func & MACRONIX_READ_RETRY_BIT) {
> > > > > > + chip->read_retries = MACRONIX_READ_RETRY_MODE + 1;
> > > > >
> > > > > Why +1 here, I am missing something?
> > > >
> > > >
> > > > Without + 1, read retry mode is up t
From: Mason Yang
Make sure we flag all 1.8V broken chips as not supporting this features.
Signed-off-by: Mason Yang
---
drivers/mtd/nand/raw/nand_macronix.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_macronix.c
b/drivers/mtd/nand/raw/nand_macronix.c
i
From: Mason Yang
Hi Boris,
I patched this for Macronix all 1.8V AC chips.
Thanks for your review.
best regards,
Mason
Mason Yang (1):
mtd: rawnand: Add All 1.8V AC chips have a broken
GET_FEATURES(TIMINGS)
drivers/mtd/nand/raw/nand_macronix.c | 7 +++
1 file changed, 7 insertions(+)
From: Mason Yang
Hi Mark & Boris,
I patched v6 spi-mxic.c based on Boris's comments of v5.
Thanks for your review.
best regards,
Mason
Mason Yang (2):
spi: Add MXIC controller driver
dt-binding: spi: Document Macronix controller bindings
Documentation/devicetree/bindings/spi/spi-mxic.tx
From: Mason Yang
Add a driver for Macronix SPI controller IP.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig| 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-mxic.c | 619 +
3 files changed, 626 insertions(+)
create mode 100644 dri
From: Mason Yang
Document the bindings used by the Macronix controller.
Signed-off-by: Mason Yang
---
Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt
diff --
From: Mason Yang
Document the bindings used by the Macronix controller.
Signed-off-by: Mason Yang
---
Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt
diff --
From: Mason Yang
Add a driver for Macronix SPI controller IP.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig| 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-mxic.c | 626 +
3 files changed, 633 insertions(+)
create mode 100644 dri
From: Mason Yang
Hi Mark,
I patched v5 spi-mxic.c based on Boris's comments for v4.
Thanks for your review.
best regards,
Mason
Mason Yang (2):
spi: Add MXIC controller driver
dt-binding: spi: Document Macronix controller bindings
Documentation/devicetree/bindings/spi/spi-mxic.txt | 34
From: Mason Yang
Document the bindings used by the Macronix controller.
Signed-off-by: Mason Yang
---
Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt
diff --
From: Mason Yang
Add a driver for Macronix SPI controller IP.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig| 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-mxic.c | 639 +
3 files changed, 646 insertions(+)
create mode 100644 dri
From: Mason Yang
Hi Mark,
I patched v4 spi-mxic.c for clk_ctrl() and spi_setup() according to
your comments on v3.
Hi Boris,
I also patched clk frequency changed when the driver detects it needs
to be changed.
please help to review.
thanks & best regards,
Mason
Mason Yang (2):
spi: Add MX
From: Mason Yang
Document the bindings used by the Macronix controller.
Signed-off-by: Mason Yang
---
Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt
diff --
From: Mason Yang
Add a driver for Macronix SPI controller IP.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig| 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-mxic.c | 599 +
3 files changed, 606 insertions(+)
create mode 100644 dri
From: Mason Yang
Hi Mark, Trent and Boris,
I patched spi-mxic.c for clk_ctrl and run time PM.
please help to review.
thanks & best regards,
Mason
Mason Yang (2):
spi: Add MXIC controller driver
dt-bindings: spi: Document Macronix controller bindings
Documentation/devicetree/bindings/s
From: Mason Yang
Document the bindings used by the Macronix controller.
Signed-off-by: Mason Yang
---
Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt
diff --
From: Mason Yang
Hi Mark and Trent,
I patched spi-mxic.c and add the run time PM function.
thanks & best regards,
Mason
Mason Yang (2):
spi: Add MXIC controller driver
dt-binding: spi: Document Macronix controller bindings
Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++
driv
From: Mason Yang
Add a driver for Macronix SPI controller IP.
Support run time PM.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig| 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-mxic.c | 674 +
3 files changed, 681 insertions(+)
c
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