> -Original Message-
> From: linux-gpio-ow...@vger.kernel.org [mailto:linux-gpio-
> ow...@vger.kernel.org] On Behalf Of Andy Shevchenko
> Sent: Friday, November 11, 2016 12:07 AM
> To: Tan, Jui Nee ; mika.westerb...@linux.intel.com;
> heikki.kroge...@linux.intel.com;
> -Original Message-
> From: Andy Shevchenko [mailto:andriy.shevche...@linux.intel.com]
> Sent: Friday, November 18, 2016 7:22 PM
> To: Tan, Jui Nee ; mika.westerb...@linux.intel.com;
> heikki.kroge...@linux.intel.com; t...@linutronix.de; dvh...@infradead.org;
> m
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V11:
- No change
Changes in V10:
- No change
Changes in V9:
- No change
Changes
Adding Intel codename Apollo Lake platform device IDs for PCH.
Signed-off-by: Tan Jui Nee
Acked-for-MFD-by: Lee Jones
---
Changes in V11:
- No change
Changes in V10:
- No change
Changes in V9:
- No change
Changes in V8:
- No change
drivers/mfd/lpc_ich_core.c
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V11:
- Remove duplicated object file lpc_ich-objs in Makefile.
- Put p2sb.h header file
GPIO.
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V11:
- Select CONFIG_P2SB when CONFIG_X86_INTEL_IVI is enabled instead of
CONFIG_LPC_ICH is enabled. This is to fix kbuildbot error.
Changes in V10:
- No change
Changes in V9:
- No
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V11:
- No change
Changes in V10:
- No change
Changes in V9:
- Remove the file
add_devices() once for all gpio communities
Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
drivers/platform/x86/p2sb: New Primary to Sideband bridge support
driver for Intel SOC's
Ta
GPIO.
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V10:
- No change
Changes in V9:
- No change
Changes in V8:
- No change
arch/x86/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
nges in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
drivers/platform/x86/p2sb: New Primary to Sideband bridge support
driver for Intel SOC's
Tan Jui Nee (5):
mfd: lpc_ich: Rename lpc-ich
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V10:
- No change
Changes in V9:
- No change
Changes in V8:
- No change
driver
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V10:
- No change
Changes in V9:
- No change
Changes in V8:
- Rename source file
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".
Signed-off-by: Tan Jui Nee
Reviewed-by: Mika Westerberg
---
Changes in V10:
- No change
Changes in V9:
- Remove the filename from the header of lpc_ich_core.
Adding Intel codename Apollo Lake platform device IDs for PCH.
Signed-off-by: Tan Jui Nee
Acked-for-MFD-by: Lee Jones
---
Changes in V10:
- No change
Changes in V9:
- No change
Changes in V8:
- No change
drivers/mfd/lpc_ich_core.c | 6 ++
include/linux/mfd
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
Changes in V9:
- No change
Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).
Changes in V7
Adding Intel codename Apollo Lake platform device IDs for PCH.
Signed-off-by: Tan Jui Nee
Acked-for-MFD-by: Lee Jones
---
Changes in V9:
- No change
Changes in V8:
- No change
drivers/mfd/lpc_ich_core.c | 6 ++
include/linux/mfd/lpc_ich.h | 1 +
2 files changed, 7
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
nko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's
Tan Jui Nee (5):
mfd: lpc_ich: Rename lpc-ich driver
x86/intel-ivi: Add Intel In-Vehicle Infotainment (IVI) systems used in
cars support
mfd: move enum lpc_chipsets into lpc_ich.h
mfd: lpc_ic
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".
Signed-off-by: Tan Jui Nee
---
Changes in V9:
- Remove the filename from the header of lpc_ich_core.c (suggested by
Lee).
Changes in V8:
- Updat
GPIO.
Signed-off-by: Tan Jui Nee
---
Changes in V9:
- No change
Changes in V8:
- No change
arch/x86/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e2c1dcf..aa8928a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.
Signed-off-by: Tan Jui Nee
---
Changes in V9:
- No change
Changes in V8:
- No change
drivers/mfd/lpc_ich_core.c
Adding Intel codename Apollo Lake platform device IDs for PCH.
Signed-off-by: Tan Jui Nee
---
Changes in V8:
- No change
drivers/mfd/lpc_ich_core.c | 6 ++
include/linux/mfd/lpc_ich.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/mfd/lpc_ich_core.c b/drivers/mfd
GPIO.
Signed-off-by: Tan Jui Nee
---
Changes in V8:
- No change
arch/x86/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e2c1dcf..aa8928a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -512,6 +512,14 @@ config
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.
Signed-off-by: Tan Jui Nee
---
Changes in V8:
- No change
drivers/mfd/lpc_ich_core.c | 71 -
include/linux/mfd/lpc_ich.h
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
Changes in V8:
- Rename source file lpc_ich-apl.c to lpc_ich_apl.c (suggested by Mika).
Changes in V7:
- Add author information
add_devices() once for all gpio communities
Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's
Ta
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich_core".
Signed-off-by: Tan Jui Nee
---
Changes in V8:
- Update new file name with lpc_ich_core.c at description of source
file.
- Rework Makefile with new source fil
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Thursday, September 29, 2016 7:09 PM
> To: Tan, Jui Nee
> Cc: heikki.kroge...@linux.intel.com; andriy.shevche...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com;
> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Friday, September 30, 2016 8:33 AM
> To: Tan, Jui Nee
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de; mi.
> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Friday, September 30, 2016 8:31 AM
> To: Tan, Jui Nee
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de; mi.
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
Changes in V7:
- Add author information and rewrite description of source file
lpc_ich-apl.c and lpc_ich_apl.h.
- Sort
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich-core".
Signed-off-by: Tan Jui Nee
---
Changes in V7:
- No change
Changes in V6:
- none, just a subject line and commit message change.
drivers/mfd/Makefile
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
Adding Intel codename Apollo Lake platform device IDs for PCH.
Signed-off-by: Tan Jui Nee
---
drivers/mfd/lpc_ich-core.c | 6 ++
include/linux/mfd/lpc_ich.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/mfd/lpc_ich-core.c b/drivers/mfd/lpc_ich-core.c
index 05ed985..589155c
Move the enum's definition into a standalone header file which can be used
wherever its definition is needed.
Signed-off-by: Tan Jui Nee
---
drivers/mfd/lpc_ich-core.c | 71 -
include/linux/mfd/lpc_ich.h
GPIO.
Signed-off-by: Tan Jui Nee
---
arch/x86/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index edc0313..ce5a048 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -511,6 +511,14 @@ config X86_INTEL_CE
This option
only one
use case
- Only call mfd_add_devices() once for all gpio communities
Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideba
> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Tuesday, August 9, 2016 3:16 PM
> To: Tan, Jui Nee
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de;
>
> -Original Message-
> From: Tan, Jui Nee
> Sent: Monday, July 18, 2016 11:35 AM
> To: 'Paul Gortmaker' ;
> andriy.shevche...@linux.intel.com
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com;
> -Original Message-
> From: paul.gortma...@gmail.com [mailto:paul.gortma...@gmail.com] On
> Behalf Of Paul Gortmaker
> Sent: Friday, July 15, 2016 8:01 AM
> To: Tan, Jui Nee
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche.
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Tuesday, June 28, 2016 4:19 PM
> To: Tan, Jui Nee
> Cc: heikki.kroge...@linux.intel.com; andriy.shevche...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com;
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
Changes in V6:
- Rename CONFIG_X86_INTEL_APL to CONFIG_X86_INTEL_IVI so that it
relates to the actual product, as suggested by
This patch follows the example of mfd/wm831x to rename the driver
from "lpc_ich" to "lpc_ich-core".
Signed-off-by: Tan Jui Nee
---
Changes in V6:
- none, just a subject line and commit message change.
drivers/mfd/Makefile | 1 +
drivers/mfd/{
- Only call mfd_add_devices() once for all gpio communities
Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Tuesday, June 28, 2016 5:15 PM
> To: Andy Shevchenko
> Cc: Tan, Jui Nee ; Mika Westerberg
> ; Krogerus, Heikki
> ; Andy Shevchenko
> ; Thomas Gleixner
> ; Ingo Molnar ; H. Peter Anv
This patch follows the example of mfd/wm831x and splits it into an
interface independent core since it is growing quite fast with
many table entries.
Signed-off-by: Tan Jui Nee
---
drivers/mfd/Makefile |1 +
drivers/mfd/lpc_ich-core.c | 1126
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
Changes in V5:
- Split lpc-ich driver into two parts (lpc_ich-core and lpc_ich-apl).
The file lpc_ich-apl.c introduces gpio
ommunities
Changes in V2:
- Add new config option CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's
Tan Jui Nee (2):
mfd: lpc_ich: Prepar
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Tuesday, June 21, 2016 3:24 PM
> To: Tan, Jui Nee
> Cc: Andy Shevchenko ;
> heikki.kroge...@linux.intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@k
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
Changes in V4:
- Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
[PATCH 2/3] x86/platform/p2sb: New Primary to Sideband
r for
Intel SOC's
Tan Jui Nee (2):
pinctrl/broxton: enable platform device in the absent of ACPI
enumeration
mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system
arch/x86/Kconfig| 14
arch/x86/include/asm/p2sb
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.
Signed-off-by: Tan Jui Nee
Acked-by: Mika Westerberg
---
Changes in V4:
- added Mika's ACK
Changes in V3:
- No c
> -Original Message-
> From: Linus Walleij [mailto:linus.wall...@linaro.org]
> Sent: Tuesday, June 14, 2016 3:09 PM
> To: Tan, Jui Nee
> Cc: Mika Westerberg ; Heikki Krogerus
> ; Andy Shevchenko
> ; Thomas Gleixner
> ; Ingo Molnar ; H. Peter Anvin
> ; x...@ker
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Monday, June 13, 2016 11:59 PM
> To: Andy Shevchenko
> Cc: Tan, Jui Nee ; heikki.kroge...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel
> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Thursday, June 9, 2016 11:56 PM
> To: Tan, Jui Nee
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de;
>
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
drivers/mfd/Kconfig | 3 +-
drivers/mfd/lpc_ich.c | 153 ++
2 files changed, 155 insertions
CONFIG_X86_INTEL_NON_ACPI and "select PINCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's
Tan Jui Nee (2):
pinctrl/broxton: enable platform device in the absent of ACPI
enumeration
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.
Signed-off-by: Tan Jui Nee
---
drivers/pinctrl/intel/pinctrl-broxton.c | 43 -
1 file changed, 31
> -Original Message-
> From: Lee Jones [mailto:lee.jo...@linaro.org]
> Sent: Monday, May 9, 2016 8:25 PM
> To: Tan, Jui Nee
> Cc: mika.westerb...@linux.intel.com; heikki.kroge...@linux.intel.com;
> andriy.shevche...@linux.intel.com; t...@linutronix.de;
> mi...@redha
NCTRL"
to fix kbuildbot error
Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's
Tan Jui Nee (2):
pinctrl/broxton: enable platform device in the absent of ACPI
enumeration
mfd: lpc_ich: Add support for Intel Apollo Lake
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
drivers/mfd/Kconfig | 3 +-
drivers/mfd/lpc_ich.c | 128 ++
2 files changed, 130 insertions
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.
Signed-off-by: Tan Jui Nee
---
drivers/pinctrl/intel/pinctrl-broxton.c | 43 -
1 file changed, 31
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
> -Original Message-
> From: lkp
> Sent: Monday, April 11, 2016 12:35 PM
> To: Tan, Jui Nee
> Cc: kbuild-...@01.org; mika.westerb...@linux.intel.com;
> heikki.kroge...@linux.intel.com; andriy.shevche...@linux.intel.com;
> t...@linutronix.de; mi...@redhat.c
x27;s
Tan Jui Nee (2):
pinctrl/broxton: enable platform device in the absent of ACPI
enumeration
mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system
arch/x86/Kconfig| 4 ++
arch/x86/include/asm/p2sb.h | 27
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.
Signed-off-by: Tan Jui Nee
---
drivers/pinctrl/intel/pinctrl-broxton.c | 43 -
1 file changed, 31
From: Andy Shevchenko
There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.
Signed-off-by: Yong, Jonathan
Signed-off-by: Andy Shevchenko
This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.
Signed-off-by: Tan Jui Nee
---
drivers/mfd/Kconfig | 3 +-
drivers/mfd/lpc_ich.c | 119 ++
2 files changed, 121 insertions
From: "Tan, Jui Nee"
On Intel Baytrail, there is case when interrupt handler get called, no SPI
message is captured. The RX FIFO is indeed empty when RX timeout pending
interrupt (SSSR_TINT) happens.
Use the BIOS version where both HSUART and SPI are on the same IRQ. Both
drivers
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