On Sat, Feb 08, 2025 at 02:01:11AM +, Colton Lewis wrote:
> The ARM architecture specifies that when MDCR_EL2.HPMN is set, EL1 and
> EL0, which includes KVM guests, should read that value for PMCR.N.
>
> Signed-off-by: Colton Lewis
> ---
> arch/arm64/kvm/debug.c
Hi Colton,
On Sat, Feb 08, 2025 at 02:01:09AM +, Colton Lewis wrote:
> For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
> into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
> allowed, EL0 while counters HPMN..N are only accessible by EL2.
>
> Introduce a
On Tue, Dec 17, 2024 at 03:10:28PM +, Mark Brown wrote:
> On Tue, Dec 17, 2024 at 01:54:39PM +, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > The selftests are shipped as part of the kernel source and frequently
> > > used for testing the kernel, it's all one source base and we want t
On Mon, 16 Dec 2024 19:28:24 +, Mark Brown wrote:
> In commit 03c7527e97f7 ("KVM: arm64: Do not allow ID_AA64MMFR0_EL1.ASIDbits
> to be overridden") we made that bitfield in the ID registers unwritable
> however the change neglected to make the corresponding update to set_id_regs
> resulting in
On Wed, Sep 25, 2024 at 11:22:40PM -0400, Shaoqin Huang wrote:
> Currently FEAT_RAS is not writable, this makes migration fail between
> systems where this feature differ. Allow the FEAT_RAS writable in
> ID_AA64PFR0_EL1 to let the migration possible when the RAS is differ
> between two machines.
>
On Fri, Apr 19, 2024 at 01:57:03PM -0700, James Houghton wrote:
> On Fri, Apr 12, 2024 at 11:41 AM David Matlack wrote:
> >
> > On 2024-04-01 11:29 PM, James Houghton wrote:
> > > This patchset adds a fast path in KVM to test and clear access bits on
> > > sptes without taking the mmu_lock. It als
On Tue, Apr 02, 2024 at 12:06:56AM -0400, Yu Zhao wrote:
> On Mon, Apr 1, 2024 at 7:30 PM James Houghton wrote:
> > Suggested-by: Yu Zhao
>
> Thanks but I did not suggest this.
Entirely up to you, but I would still want to credit everyone who
contributed to a feature even if the underlying impl
On Mon, Jan 25, 2021 at 12:56 PM Marc Zyngier wrote:
> - Cherry-pick 9fd339a45be5 ("arm64: Work around broken GCC 4.9
> handling of "S" constraint"), which works around this particular GCC
> bug
>
> - Cherry-pick dca5244d2f5b ("compiler.h: Raise minimum version of GCC
> to 5.1 for arm64"), w
> That means we have two options:
> (a) define __hyp_panic_string in a different .c file in all pre-5.9 branches,
> or
> (b) revert the backported patch.
>
> The patch was needed in 5.9 and should stay there. It wasn't needed in earlier
> versions because the symbol was being kept alive by anothe
On Thu, Dec 10, 2020 at 12:05 PM Paolo Bonzini wrote:
>
> On 10/12/20 18:59, Oliver Upton wrote:
> > However, I don't believe we can assume the guest's TSCs to be synchronized,
> > even if sane guests will never touch them. In this case, I think a per-vCPU
> >
On Thu, Dec 10, 2020 at 9:16 AM Andy Lutomirski wrote:
>
>
>
> > On Dec 10, 2020, at 6:52 AM, Maxim Levitsky wrote:
> >
> > On Thu, 2020-12-10 at 12:48 +0100, Paolo Bonzini wrote:
> >>> On 08/12/20 22:20, Thomas Gleixner wrote:
> >>> So now life migration comes a long time after timekeeping had
+cc Sean's new handle
On Tue, Dec 8, 2020 at 9:57 AM Oliver Upton wrote:
>
> On Tue, Dec 8, 2020 at 5:13 AM Maxim Levitsky wrote:
> >
> > On Mon, 2020-12-07 at 11:29 -0600, Oliver Upton wrote:
> > > On Thu, Dec 3, 2020 at 11:12 AM Maxim Levitsky
> > >
On Tue, Dec 8, 2020 at 5:13 AM Maxim Levitsky wrote:
>
> On Mon, 2020-12-07 at 11:29 -0600, Oliver Upton wrote:
> > On Thu, Dec 3, 2020 at 11:12 AM Maxim Levitsky wrote:
> > > These two new ioctls allow to more precisly capture and
> > > restore guest's TSC
On Thu, Dec 3, 2020 at 11:12 AM Maxim Levitsky wrote:
>
> These two new ioctls allow to more precisly capture and
> restore guest's TSC state.
>
> Both ioctls are meant to be used to accurately migrate guest TSC
> even when there is a significant downtime during the migration.
>
> Suggested-by: Pa
On Tue, Oct 6, 2020 at 11:35 AM Sean Christopherson
wrote:
>
> On Tue, Oct 06, 2020 at 10:36:09AM -0700, Jim Mattson wrote:
> > On Wed, Aug 12, 2020 at 10:51 AM Sean Christopherson
> > wrote:
> > >
> > > On successful nested VM-Enter, check for pending interrupts and convert
> > > the highest pri
On Fri, Jul 24, 2020 at 10:35 AM Oliver Upton wrote:
>
> commit 8171cd68806b ("KVM: x86: use raw clock values consistently")
> causes KVM to accidentally write seconds to the nanoseconds field (and
> vice versa) in the KVM wall clock. Fix it by reversing this accidenta
the amount of time represented as seconds.
Fixes: 8171cd68806b ("KVM: x86: use raw clock values consistently")
Cc: sta...@vger.kernel.org
Reviewed-by: Jim Mattson
Reviewed-by: Peter Shier
Signed-off-by: Oliver Upton
---
Parent commit: c34b26b98cac ("KVM: MIPS: clean up redund
644d711aa0e1 ("KVM: nVMX: Deciding if L0 or L1 should handle an L2
> exit")
> Cc: Jim Mattson
> Cc: Xiaoyao Li
> Cc: sta...@vger.kernel.org
> Cc: Oliver Upton
> Cc: Krish Sadhukhan
> Cc: Miaohe Lin
> Signed-off-by: Sean Christopherson
Reviewed-by: Oliver U
e MTF when performing instruction
> emulation")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Paolo Bonzini
Reviewed-by: Oliver Upton
> ---
> arch/x86/kvm/x86.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kv
On Mon, May 11, 2020 at 9:05 AM Sean Christopherson
wrote:
>
> +cc a few other people that have reported this at one time or another.
>
> On Tue, May 05, 2020 at 10:12:45AM -0400, Peter Xu wrote:
> > On Mon, May 04, 2020 at 06:39:29PM -0700, Sean Christopherson wrote:
> > > On Mon, May 04, 2020 at
so
> > be addressed in a future patch.
> >
> > Fixes: b6b8a1451fc4 ("KVM: nVMX: Rework interception of IRQs and NMIs")
> > Reported-by: Jim Mattson
> > Cc: Oliver Upton
> > Cc: Peter Shier
> > Signed-off-by: Sean Christopherson
> Reviewed-by: Jim Mattson
Reviewed-by: Oliver Upton
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