On Wed, 12 Feb 2025 11:41:38 +,
Dan Carpenter wrote:
>
> On Tue, Feb 11, 2025 at 11:36:31AM +, Marc Zyngier wrote:
> > For the crash at hand, which clearly shows nVHE, can you report
> > whether the following hack fixes it for you?
> >
> > M.
>
On Tue, 11 Feb 2025 11:24:06 +,
Naresh Kamboju wrote:
>
> Regression on rk3399-rock-pi-4b while running kvm-unit-tests with
> nvhe, protected and vhe mode with virtualization enabled.
I do not buy this. RK3399 only has ARMv8.0 cores, which by definition
do not have VHE.
>
> First seen on n
On Fri, 07 Feb 2025 13:26:41 +,
Ganapatrao Kulkarni wrote:
>
> >> + if (is_vcpu_nested(vcpu)) {
> >> + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CPTR_EL2), fpen);
> >> + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL2), sctlr_el1);
> >> + vcpu_set_reg(vcpu, KVM_A
On Thu, 06 Feb 2025 16:41:19 +,
Ganapatrao Kulkarni wrote:
>
> This patch adds the required changes to init vcpu in vEL2 context.
> Also adds a KVM selftest to execute guest code as a guest hypervisor(L1).
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> tools/testing/selftests/kvm/Makefile.
On Thu, 06 Feb 2025 16:41:20 +,
Ganapatrao Kulkarni wrote:
>
> With NV2 enabled, some of the EL1/EL2/EL12 register accesses are
> transformed to memory accesses. This test code accesses all those
> registers in guest code to validate that they are not trapped to L0.
>
Traps to L0 are invisib
On Tue, 28 Jan 2025 22:08:27 +,
Colton Lewis wrote:
>
> >> + bitmap_set(cpu_pmu->cntr_mask, 0, pmcr_n);
> >> +
> >> + if (reserved_guest_counters > 0 && reserved_guest_counters < pmcr_n) {
> >> + cpu_pmu->hpmn = reserved_guest_counters;
> >> + cpu_pmu->partitioned = true;
On Mon, 27 Jan 2025 22:20:27 +,
Colton Lewis wrote:
>
> For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
> into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
> allowed, EL0 while counters HPMN..N are only accessible by EL2.
>
> Introduce a module paramet
On Tue, 17 Dec 2024 15:10:28 +,
Mark Brown wrote:
>
> [1 ]
> On Tue, Dec 17, 2024 at 01:54:39PM +0000, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > The selftests are shipped as part of the kernel source and frequently
> > > used for testing the ker
On Tue, 17 Dec 2024 13:12:12 +,
Mark Brown wrote:
>
> [1 ]
> On Tue, Dec 17, 2024 at 08:30:37AM +0000, Marc Zyngier wrote:
> > Mark Brown wrote:
>
> > > Fixes: 03c7527e97f7 ("KVM: arm64: Do not allow ID_AA64MMFR0_EL1.ASIDbits
> > > to be overridde
> - REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0),
> REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
> REG_FTR_END,
> };
>
With the Fixes: line dropped,
Acked-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Fri, 12 Apr 2024 15:54:22 +0100,
Sean Christopherson wrote:
>
> On Fri, Apr 12, 2024, Marc Zyngier wrote:
> > On Fri, 12 Apr 2024 11:44:09 +0100, Will Deacon wrote:
> > > On Fri, Apr 05, 2024 at 07:58:12AM -0400, Paolo Bonzini wrote:
> > > Also, if you're
On Fri, 12 Apr 2024 11:44:09 +0100,
Will Deacon wrote:
>
> On Fri, Apr 05, 2024 at 07:58:12AM -0400, Paolo Bonzini wrote:
> > diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
> > index dc04bc767865..ff17849be9f4 100644
> > --- a/arch/arm64/kvm/mmu.c
> > +++ b/arch/arm64/kvm/mmu.c
> > @@ -
7 +---
> mm/migrate_device.c | 8 +---
> mm/mmu_notifier.c | 17 -
> virt/kvm/kvm_main.c | 50 +
> 26 files changed, 10 insertions(+), 411 deletions(-)
>
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Tue, 02 Apr 2024 05:06:56 +0100,
Yu Zhao wrote:
>
> On Mon, Apr 1, 2024 at 7:30 PM James Houghton wrote:
> >
> > Participate in bitmap-based aging while grabbing the KVM MMU lock for
> > reading. Ideally we wouldn't need to grab this lock at all, but that
> > would require a more intrustive a
On 2021-04-20 13:34, Thomas Bogendoerfer wrote:
IDT 79rc3243x SoCs have rather simple interrupt controllers connected
to the MIPS CPU interrupt lines. Each of them has room for up to
32 interrupts.
Signed-off-by: Thomas Bogendoerfer
Is there a DT binding for this irqchip? The code looks fine,
On Tue, 20 Apr 2021 14:24:19 +0100, Jon Hunter wrote:
> Commit 300bb1fe7671 ("ptp: arm/arm64: Enable ptp_kvm for arm/arm64")
> enable ptp_kvm support for ARM platforms and for any ARM platform that
> does not support this, the following error message is displayed ...
>
> ERR KERN fail to initiali
When going into suspend, the Tegra MSI controller loses its
state. Restore the MSI allocation on resume so that PCI devices
are usable again.
Reported-by: Jon Hunter
Tested-by: Jon Hunter
Fixes: 973a28677e39 ("PCI: tegra: Convert to MSI domains")
Signed-off-by: Marc Zyngier
C
On Tue, 20 Apr 2021 10:44:02 +0100,
Pali Rohár wrote:
>
> Hello!
>
> On Tuesday 20 April 2021 14:17:21 Jianjun Wang wrote:
> > +static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
> > +{
> > + int i;
> > + u32 val;
> > +
> > + for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
> > +
On Mon, 19 Apr 2021 00:44:14 +0100,
Thomas Gleixner wrote:
>
> On Sat, Apr 10 2021 at 13:00, Marc Zyngier wrote:
> > dev_id and percpu_dev_id are mutually exclusive in struct irqaction,
> > as they conceptually represent the same thing, only in a per-cpu
> > fashion.
&
On Mon, 19 Apr 2021 20:42:45 +0100,
Robert Hancock wrote:
>
> Previously the XILINX_INTC config option was hidden and only
> auto-selected on the MicroBlaze platform. However, this IP can also be
> used on the Zynq and ZynqMP platforms as a secondary cascaded
> controller. Allow this option to be
On Sat, 17 Apr 2021 09:59:39 +0100,
Zenghui Yu wrote:
>
> On 2021/3/30 22:54, Marc Zyngier wrote:
> > +PTP_KVM support for arm/arm64
> > +=
> > +
> > +PTP_KVM is used for high precision time sync between host and guests.
> > +It r
On Sat, 17 Apr 2021 09:42:37 +0100,
Zenghui Yu wrote:
>
> On 2021/3/30 22:54, Marc Zyngier wrote:
> > +int kvm_arch_ptp_init(void)
> > +{
> > + int ret;
> > +
> > + ret = kvm_arm_hyp_service_available(ARM_SMCCC_KVM_FUNC_PTP);
> > + if (ret <= 0)
On Fri, 16 Apr 2021 17:05:49 +0100,
Robert Hancock wrote:
>
> On Fri, 2021-04-16 at 14:41 +0100, Marc Zyngier wrote:
> > On Fri, 16 Apr 2021 00:32:50 +0100,
> > Robert Hancock wrote:
> > > Previously the XILINX_INTC config option was hidden and only
> >
On Fri, 16 Apr 2021 02:13:38 +0100,
Kever Yang wrote:
>
> Hi Marc,
>
> On 2021/4/15 下午4:11, Marc Zyngier wrote:
> > Hi Kever,
> >
> > On Thu, 15 Apr 2021 08:24:33 +0100,
> > Kever Yang wrote:
> >> Hi Marc, Peter,
> >>
> >>
On Thu, 15 Apr 2021 15:08:09 +0100,
Keqian Zhu wrote:
>
> Hi Marc,
>
> On 2021/4/15 22:03, Keqian Zhu wrote:
> > The MMIO region of a device maybe huge (GB level), try to use
> > block mapping in stage2 to speedup both map and unmap.
> >
> > Compared to normal memory mapping, we should consider
[+ Mark]
On Fri, 16 Apr 2021 07:22:17 +0100,
He Ying wrote:
>
> We found this problem in our kernel src tree:
>
> [ 14.816231] [ cut here ]
> [ 14.816231] kernel BUG at irq.c:99!
> [ 14.816232] Internal error: Oops - BUG: 0 [#1] SMP
> [ 14.816232] Process swapper
On Fri, 16 Apr 2021 00:32:50 +0100,
Robert Hancock wrote:
>
> Previously the XILINX_INTC config option was hidden and only
> auto-selected on the MicroBlaze platform. However, this IP can also be
> used on other platforms. Allow this option to be user-enabled.
>
> Signed-off-by: Robert Hancock
On Thu, 15 Apr 2021 12:26:26 +0100,
Keqian Zhu wrote:
>
> Hi Marc,
>
> On 2021/4/15 18:23, Marc Zyngier wrote:
> > On Thu, 15 Apr 2021 03:20:52 +0100,
> > Keqian Zhu wrote:
> >>
> >> Hi Marc,
> >>
> >> On 2021/4/14 17:05, Marc Zyngie
On Thu, 15 Apr 2021 11:38:52 +0100,
Heiko Carstens wrote:
>
> On Wed, Apr 14, 2021 at 02:44:07PM +0100, Marc Zyngier wrote:
> > perf_pmu_name() and perf_num_counters() are unused. Drop them.
> >
> > Signed-off-by: Marc Zyngier
> > ---
> >
On Thu, 15 Apr 2021 03:20:52 +0100,
Keqian Zhu wrote:
>
> Hi Marc,
>
> On 2021/4/14 17:05, Marc Zyngier wrote:
> > + Santosh, who found some interesting bugs in that area before.
> >
> > On Wed, 14 Apr 2021 07:51:09 +0100,
> > Keqian Zhu wrote:
> >>
Hi Kever,
On Thu, 15 Apr 2021 08:24:33 +0100,
Kever Yang wrote:
>
> Hi Marc, Peter,
>
> RK356x GIC has two issues:
>
> 1. GIC only support 32bit address while rk356x supports 8GB DDR SDRAM,
> so we use ZONE_DMA32 to fix this issue;
What transactions does this affect exactly? Only some ITS
perf_pmu_name() and perf_num_counters() are unused. Drop them.
Signed-off-by: Marc Zyngier
---
include/linux/perf_event.h | 2 --
kernel/events/core.c | 5 -
2 files changed, 7 deletions(-)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 3f7f89ea5e51
perf_pmu_name() and perf_num_counters() are now unused. Drop them.
Signed-off-by: Marc Zyngier
---
drivers/perf/arm_pmu.c | 30 --
1 file changed, 30 deletions(-)
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index 2d10d84fb79c..d4f7f1f9cc77 100644
perf_pmu_name() and perf_num_counters() are unused. Drop them.
Signed-off-by: Marc Zyngier
---
arch/sh/kernel/perf_event.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 445e3ece4c23..1d2507f22437 100644
perf_pmu_name() and perf_num_counters() are unused. Drop them.
Signed-off-by: Marc Zyngier
---
arch/s390/kernel/perf_event.c | 21 -
1 file changed, 21 deletions(-)
diff --git a/arch/s390/kernel/perf_event.c b/arch/s390/kernel/perf_event.c
index 1e75cc983546..ea7729bebaa0
KVM/arm64 is the sole user of perf_num_counters(), and really
could do without it. Stop using the obsolete API by relying on
the existing probing code.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/perf.c | 7 +--
arch/arm64/kvm/pmu-emul.c | 2 +-
include/kvm/arm_pmu.h | 4
3
architectures but arm64, s390
and sh (plus a bit of cruft in the core perf code). With KVM fixed,
perf_num_counters() and perf_pmu_name() are finally gone.
Thanks,
M.
[1] https://lore.kernel.org/lkml/20210215050618.hgftdmfmslbdrg3j@vireshk-i7
Marc Zyngier (5):
KVM: arm64: Divorce the perf
On Wed, 14 Apr 2021 12:41:20 +0100,
Peter Geis wrote:
>
> On Tue, Apr 13, 2021 at 11:51 AM Marc Zyngier wrote:
> >
> > On Tue, 13 Apr 2021 16:03:51 +0100,
> > Peter Geis wrote:
> > >
> > > On Tue, Apr 13, 2021 at 10:01 AM Marc Zyngier wrote:
> >
On Tue, 13 Apr 2021 21:00:57 +0100,
Nathan Chancellor wrote:
[...]
> I just ran into this again. It is not a clang specific issue, it
> reproduces quite easily with arm64 defconfig minus CONFIG_PERF_EVENTS
> and gcc 10.3.0:
>
> arch/arm64/kvm/perf.c: In function 'kvm_perf_init':
> arch/arm64/kv
+ Santosh, who found some interesting bugs in that area before.
On Wed, 14 Apr 2021 07:51:09 +0100,
Keqian Zhu wrote:
>
> The MMIO region of a device maybe huge (GB level), try to use
> block mapping in stage2 to speedup both map and unmap.
>
> Compared to normal memory mapping, we should consi
On Tue, 13 Apr 2021 20:45:00 +0100,
Mathieu Poirier wrote:
>
> On Tue, 13 Apr 2021 at 10:52, Marc Zyngier wrote:
> >
> > Hi Mathieu,
> >
> > On Tue, 13 Apr 2021 17:19:52 +0100,
> > Mathieu Poirier wrote:
> >
Hi Mathieu,
On Tue, 13 Apr 2021 17:19:52 +0100,
Mathieu Poirier wrote:
>
> The following changes since commit 4fb13790417a7bf726f3867a5d2b9723efde488b:
>
> dts: bindings: Document device tree bindings for Arm TRBE (2021-04-06
> 16:05:38 -0600)
>
> are available in the Git repository at:
>
On Tue, 13 Apr 2021 16:03:51 +0100,
Peter Geis wrote:
>
> On Tue, Apr 13, 2021 at 10:01 AM Marc Zyngier wrote:
[...]
> > What happens if you hack all the allocations to happen in the low 4GB
> > of the PA space?
>
> It seems to work correctly.
> The downstream hack
On Mon, 12 Apr 2021 17:00:34 +0200, Eric Auger wrote:
> When reading the base address of the a REDIST region
> through KVM_VGIC_V3_ADDR_TYPE_REDIST we expect the
> redistributor region list to be populated with a single
> element.
>
> However list_first_entry() expects the list to be non empty.
>
On Tue, 13 Apr 2021 07:40:10 +0100,
414777...@qq.com wrote:
>
> From: Mengguang Peng
>
> - After ITS suspend, in the ATF(arm-trusted-firmware),
> gicv3_rdistif_init_restore() just restore GICR_CTLR.Enable_LPIs bit
> of boot cpu.
>
> - In its_cpu_init_lpis() of kernel, gic_data_rdist()->lpi_
Hi Peter,
On Mon, 12 Apr 2021 21:49:59 +0100,
Peter Geis wrote:
>
> Good Afternoon,
>
> I am assisting with early bringup of the rk3566 based quartz64
> development board for mainline linux.
> I've encountered a few issues with allocating ITS on their version of
> the GIC-V3.
> The first issue
On Tue, 13 Apr 2021 01:07:23 +0100,
Andrew Lunn wrote:
>
> > > > +static void
> > > > +mt7530_setup_mdio_irq(struct mt7530_priv *priv)
> > > > +{
> > > > + struct dsa_switch *ds = priv->ds;
> > > > + int p;
> > > > +
> > > > + for (p = 0; p < MT7530_NUM_PHYS; p++) {
> > > > +
22 +-
> > virt/kvm/kvm_main.c| 325 +++--
> > 16 files changed, 552 insertions(+), 662 deletions(-)
> >
>
> For MIPS, I am going to post a series that simplifies TLB flushing
> further. I applied it, and rebased this one on top, to
> kvm/mmu-notifier-queue.
>
> Architecture maintainers, please look at the branch and
> review/test/ack your parts.
I've given this a reasonably good beating on arm64 for both VHE and
nVHE HW, and nothing caught fire, although I was left with a conflict
in the x86 code after merging with linux/master.
Feel free to add a
Tested-by: Marc Zyngier
for the arm64 side.
M.
--
Without deviation from the norm, progress is not possible.
e the memslot lookups occur before
> calling into arch code.
>
> Signed-off-by: Sean Christopherson
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Mon, 12 Apr 2021 04:42:35 +0100,
DENG Qingfang wrote:
>
> Add support for MT7530 interrupt controller to handle internal PHYs.
> In order to assign an IRQ number to each PHY, the registration of MDIO bus
> is also done in this driver.
>
> Signed-off-by: DENG Qingfang
> ---
> RFC v3 -> RFC v4
dev_id and percpu_dev_id are mutually exclusive in struct irqaction,
as they conceptually represent the same thing, only in a per-cpu
fashion.
Move them into an anonymous union, saving a few bytes on the way.
Signed-off-by: Marc Zyngier
---
include/linux/interrupt.h | 6 --
1 file changed
On Fri, 09 Apr 2021 11:10:09 +0100,
414777...@qq.com wrote:
>
> From: Mengguang Peng
>
> On arm64 platform, found that the machine could not wake up after suspend,
> this patch updates the its suspend and resume handling code.
>
> - Add a variable named ctlr_save in struct rdists.
> - When susp
On Fri, 09 Apr 2021 09:08:11 +0100,
Quentin Perret wrote:
>
> Hi Yanan,
>
> On Friday 09 Apr 2021 at 11:36:51 (+0800), Yanan Wang wrote:
> > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
> > +static void stage2_invalidate_icache(void *addr, u64 size)
> > +{
> > + if
On Thu, 08 Apr 2021 15:45:18 +0100,
Pavel Tatashin wrote:
>
> On Thu, Apr 8, 2021 at 6:24 AM Marc Zyngier wrote:
> >
> > On 2021-04-08 05:05, Pavel Tatashin wrote:
> > > From: James Morse
> > >
> > > The hyp-stub's el1_sync code doesn't
On Thu, 08 Apr 2021 12:44:00 +0100,
Stephen Rothwell wrote:
>
> [1 ]
> Hi all,
>
> After merging the kvm-arm tree, today's linux-next build (htmldocs)
> produced this warning:
>
> /home/sfr/next/next/Documentation/virt/kvm/arm/ptp_kvm.rst:19: WARNING:
> Malformed table.
> Text in column margi
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 94bc94209a66f05532c065279f4a719058d447e4
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/94bc94209a66f05532c065279f4a719058d447e4
Author:Marc Zyngier
On 2021-04-08 05:05, Pavel Tatashin wrote:
From: James Morse
The hyp-stub's el1_sync code doesn't do very much, this can easily fit
in the vectors.
With this, all of the hyp-stubs behaviour is contained in its vectors.
This lets kexec and hibernate copy the hyp-stub when they need its
behaviou
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 384cf046e474b40db4773e9358241a5de11ed8a7
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/384cf046e474b40db4773e9358241a5de11ed8a7
Author:Marc Zyngier
Hi Stephen,
On 2021-04-08 07:35, Stephen Rothwell wrote:
Hi all,
After merging the irqchip tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/irqchip/irq-wpcm450-aic.c:9:10: fatal error: asm/exception.h:
No such file or directory
9 | #include
| ^
On Wed, 07 Apr 2021 16:13:34 +0100,
Richard Cochran wrote:
>
> On Wed, Apr 07, 2021 at 10:28:44AM +0100, Marc Zyngier wrote:
> > On Tue, 30 Mar 2021 15:54:26 +0100,
> > Marc Zyngier wrote:
> > >
> > > From: Jianyong Wu
> > >
> > > Curren
On Wed, 7 Apr 2021 15:59:37 +0200, Eric Auger wrote:
> Bring some improvements/rationalization over the first version
> of the vgic_init selftests:
>
> - ucall_init is moved in run_cpu()
> - vcpu_args_set is not called as not needed
> - whenever a helper is supposed to succeed, call the non "_" ve
On Tue, 16 Mar 2021 12:11:23 +0800, Gavin Shan wrote:
> The series includes several minior improvements to stage-2 page fault
> handler: PATCH[1/2] are cleaning up the code. PATCH[3] don't retrieve
> the memory slot again in the page fault handler to save a bit CPU cycles.
>
> Changelog
>
On Tue, 16 Mar 2021 13:43:38 +,
Keqian Zhu wrote:
>
> The MMIO region of a device maybe huge (GB level), try to use
> block mapping in stage2 to speedup both map and unmap.
>
> Compared to normal memory mapping, we should consider two more
> points when try block mapping for MMIO region:
>
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: eef56c3a0492e4c1bc2a081da8f402a26d882489
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/eef56c3a0492e4c1bc2a081da8f402a26d882489
Author:Marc Zyngier
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 4a35d6a03744ded782c9301f5f5d78ad68ce680f
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/4a35d6a03744ded782c9301f5f5d78ad68ce680f
Author:Marc Zyngier
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: bd781ae53fac31acea9dec594d62a1424952dd4c
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/bd781ae53fac31acea9dec594d62a1424952dd4c
Author:Marc Zyngier
On Mon, 15 Mar 2021 11:29:06 +0530, Rajendra Nayak wrote:
> Add the compatible string for sc7280 SoC from Qualcomm
Applied to irq/irqchip-next, thanks!
[1/1] dt-bindings: qcom,pdc: Add compatible for sc7280
commit: 5deaa1d7c49151988b0bf919eeea6ad5535a29a2
Cheers,
M.
--
Without de
On Mon, 15 Mar 2021 21:18:48 +0800, Mark-PK Tsai wrote:
> Support irq polarity configuration and save and restore the config
> when system suspend and resume.
Applied to irq/irqchip-next, thanks!
[1/1] irqchip/irq-mst: Support polarity configuration
commit: ea4aeaa5c88906eb3ca3d7d3d17a45605
On Fri, 19 Mar 2021 19:42:48 +0100, Erwan Le Ray wrote:
> This series reworks stm32 usart wakeup management.
>
> Alexandre Torgue (1):
> serial: stm32: update wakeup IRQ management
>
> Erwan Le Ray (4):
> serial: stm32: rework wakeup management
> serial: stm32: clean wakeup handling in seri
On Tue, 23 Mar 2021 14:18:35 +0100, Arnd Bergmann wrote:
> When building with extra warnings enabled, clang points out a
> mistake in the error handling:
>
> drivers/irqchip/irq-gic-v3-mbi.c:306:21: error: result of comparison of
> constant 18446744073709551615 with expression of type 'phys_addr_
On Tue, 30 Mar 2021 02:09:11 +0800, Jisheng Zhang wrote:
> All of these two are never modified after init, so they can be
> __ro_after_init.
Applied to irq/irqchip-next, thanks!
[1/1] irqchip/sifive-plic: Mark two global variables __ro_after_init
commit: e03b7c1bcbfad6f27b4682f638b98627c4e
On Tue, 30 Mar 2021 14:46:20 +0800, Hao Fang wrote:
> s/Hisilicon/HiSilicon/
> It should use capital S, according to
> https://www.hisilicon.com/en/terms-of-use.
Applied to irq/irqchip-next, thanks!
[1/1] irqchip/hisi: Use the correct HiSilicon copyright
commit: 64ec2ad3b84d43926e618bb515f2
On Tue, 6 Apr 2021 14:09:11 +0200, Jonathan Neuschäfer wrote:
> This series adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older
> SoC but still commonly found on eBay, mostly in Supermicro X9 server boards.
>
> Third-party documentation is available at:
> https://github.com/neuschae
On Mon, 15 Mar 2021 13:18:48 +,
Mark-PK Tsai wrote:
>
> Support irq polarity configuration and save and restore the config
> when system suspend and resume.
>
> Signed-off-by: Mark-PK Tsai
> ---
> drivers/irqchip/irq-mst-intc.c | 94 --
> 1 file changed, 91
On Tue, 06 Apr 2021 13:09:17 +0100,
Jonathan Neuschäfer wrote:
>
> The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
> controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
> SoCs.
>
> The list of registers if based on the AMI vendor kernel and the
> Nuvoton W90N
On Tue, 30 Mar 2021 15:54:26 +0100,
Marc Zyngier wrote:
>
> From: Jianyong Wu
>
> Currently, the ptp_kvm module contains a lot of x86-specific code.
> Let's move this code into a new arch-specific file in the same directory,
> and rename the arch-independent f
a
different set of irq_chip callbacks. In this particular case, this
would leave mask/unmask as empty stubs. Or you could move the FIQ
handling to use handle_simple_irq(), because there isn't any callback
that is actually applicable.
It isn't a big deal for now, but that's something we should consider
addressing in the future. With that in mind:
Reviewed-by: Marc Zyngier
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
On Tue, 06 Apr 2021 16:09:16 +0100,
Andrew Jones wrote:
>
>
> Hi Eric,
>
> It looks like Marc already picked this patch up, but, FWIW, here's
> a few more comments you may consider.
FWIW, I'm happy to drop this patch from the queue (the series is on
its own branch for this reason), or take rew
On Mon, 5 Apr 2021 18:39:32 +0200, Eric Auger wrote:
> While writting vgic v3 init sequence KVM selftests I noticed some
> relatively minor issues. This was also the opportunity to try to
> fix the issue laterly reported by Zenghui, related to the RDIST_TYPER
> last bit emulation. The final patch i
On Tue, 6 Apr 2021 12:17:59 +, Wang Wensheng wrote:
> Fix to return a negative error code from the error handling
> case instead of 0, as done elsewhere in this function.
Applied to kvm-arm64/misc-5.13, thanks!
[1/1] KVM: arm64: Fix error return code in init_hyp_mode()
commit: 52b9e265d
On Tue, 06 Apr 2021 11:32:13 +0100,
Geert Uytterhoeven wrote:
>
> Hi Marc,
>
> On Tue, Apr 6, 2021 at 11:44 AM Marc Zyngier wrote:
> > Instead of playing games with using irq_create_identity_mapping()
> > and irq_domain_associate(), drop the use of the former and
Christophe,
On Tue, 06 Apr 2021 12:21:33 +0100,
Christophe Leroy wrote:
>
>
>
> Le 06/04/2021 à 11:35, Marc Zyngier a écrit :
> > irq_linear_revmap() is supposed to be a fast path for domain
> > lookups, but it only exposes low-level details of the irqdomain
> >
This helper doesn't have a user anymore, let's remove it.
Signed-off-by: Marc Zyngier
---
Documentation/core-api/irq/irq-domain.rst | 1 -
include/linux/irqdomain.h | 11 ---
2 files changed, 12 deletions(-)
diff --git a/Documentation/core-api/irq/irq-dom
tting NR_IRQS_LEGACY.
The dependency cannot be broken yet as there is a lot of PPC-related
code that depends on it, but that's the first step towards it.
A followup patch will remove irq_domain_add_legacy_isa.
Signed-off-by: Marc Zyngier
---
arch/powerpc/include/asm/irq.h | 4 ++--
ar
No user of these APIs are left, remove them.
Signed-off-by: Marc Zyngier
---
include/linux/irqdomain.h | 9 -
kernel/irq/irqdomain.c| 35 ---
2 files changed, 44 deletions(-)
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index
Instead of playing games with using irq_create_identity_mapping()
and irq_domain_associate(), drop the use of the former and only
use the latter, together with the allocation of the irq_desc
as needed.
It doesn't make the code less awful, but at least the intent
is clearer.
Signed-off-by:
It was never completely implemented, and was removed a long time
ago. Adjust the documentation to reflect this.
Signed-off-by: Marc Zyngier
---
kernel/irq/irqdomain.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
Use the generic irq_domain_simple_ops structure instead of
a home-grown one.
Signed-off-by: Marc Zyngier
---
arch/mips/netlogic/common/irq.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index
irq_create_strict_mappings() is a poor way to allow the use of
a linear IRQ domain as a legacy one. Let's be upfront about it.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-jcore-aic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-jcore-
irq_create_strict_mappings() is a poor way to allow the use of
a linear IRQ domain as a legacy one. Let's be upfront about
it and use a legacy domain when appropriate.
Signed-off-by: Marc Zyngier
---
arch/arm/mach-pxa/pxa_cplds_irqs.c | 24 +++-
1 file changed, 11 inser
changes in the way irqdomains work.
M.
Marc Zyngier (9):
irqdomain: Reimplement irq_linear_revmap() with irq_find_mapping()
ARM: PXA: Kill use of irq_create_strict_mappings()
irqchip/jcore-aic: Kill use of irq_create_strict_mappings()
sh: intc: Drop the use of irq_create_i
meaningful difference compared to the cost of taking an
interrupt.
Reimplement irq_linear_revmap() with irq_find_mapping()
in order to preserve source code compatibility, and
rename the internal field for a measure.
Signed-off-by: Marc Zyngier
---
include/linux/irqdomain.h | 22
appy with that, and the git merge makes it traceable.
However, some of the patches (the KVM ones) do not carry your own SoB,
which is a problem (if you are picking stuff off the list, you need to
add your own SoB). So for the couple of KVM patches, please add my
Acked-by: Marc Zyngier
t
Hi Eric,
On Sun, 04 Apr 2021 18:22:35 +0100,
Eric Auger wrote:
>
> While writting vgic v3 init sequence KVM selftests I noticed some
> relatively minor issues. This was also the opportunity to try to
> fix the issue laterly reported by Zenghui, related to the RDIST_TYPER
> last bit emulation. Th
On Sun, 04 Apr 2021 18:22:42 +0100,
Eric Auger wrote:
>
> Commit 23bde34771f1 ("KVM: arm64: vgic-v3: Drop the
> reporting of GICR_TYPER.Last for userspace") temporarily fixed
> a bug identified when attempting to access the GICR_TYPER
> register before the redistributor region setting, but droppe
On Thu, 25 Mar 2021 09:09:35 +,
Kishon Vijay Abraham I wrote:
>
> J7200 has the same PCIe IP as in J721E with minor changes in the
> wrapper. Add PCIe support for j7200 accounting for the wrapper
> changes in pci-j721e.c
> Changes from J721E:
> *) Allows byte access of bridge configuration s
On Thu, 25 Mar 2021 09:00:25 +,
Kishon Vijay Abraham I wrote:
>
> Add PCI legacy interrupt support for AM654. AM654 has a single HW
> interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
> The HW interrupt line connected to GIC is a pulse interrupt whereas
> the legacy inter
Hi Eric,
On Thu, 01 Apr 2021 20:16:53 +0100,
Auger Eric wrote:
>
> Hi Marc,
>
> On 4/1/21 7:30 PM, Marc Zyngier wrote:
> > On Thu, 01 Apr 2021 18:03:25 +0100,
> > Auger Eric wrote:
> >>
> >> Hi Marc,
> >>
> >> On 4/1/21 3:42 PM, M
Hi Eric,
On Thu, 01 Apr 2021 09:52:37 +0100,
Eric Auger wrote:
>
> Commit 23bde34771f1 ("KVM: arm64: vgic-v3: Drop the
> reporting of GICR_TYPER.Last for userspace") temporarily fixed
> a bug identified when attempting to access the GICR_TYPER
> register before the redistributor region setting,
On Thu, 01 Apr 2021 12:27:42 +0100,
Lorenzo Pieralisi wrote:
>
> On Tue, 30 Mar 2021 16:11:31 +0100, Marc Zyngier wrote:
> > This is a respin of the series described at [1].
> >
> > * From v2 [2]:
> > - Fixed the Xilinx driver, thanks to Bharat for testing
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