>-Original Message-
>From: Arnd Bergmann
>Sent: Friday, December 4, 2020 12:37 AM
[...]
>Subject: [PATCH] enetc: fix build warning
>
>From: Arnd Bergmann
>
>When CONFIG_OF is disabled, there is a harmless warning about
>an unused variable:
>
>enetc_pf.c: In function 'enetc_phylink_create'
>-Original Message-
>From: Qinglang Miao
>Sent: Monday, September 21, 2020 4:10 PM
>To: Claudiu Manoil
>Cc: David S. Miller ; Jakub Kicinski
>; net...@vger.kernel.org; linux-kernel@vger.kernel.org;
>Qinglang Miao
>Subject: [PATCH -next] enetc: simplify
>-Original Message-
>From: Stephen Rothwell
>Sent: Friday, July 24, 2020 5:24 AM
[...]
>Subject: linux-next: manual merge of the net-next tree with the net tree
>
>Hi all,
>
>Today's linux-next merge of the net-next tree got a conflict in:
>
> drivers/net/ethernet/freescale/enetc/enetc_pf
the common enetc_mdio.h header which has already the macros
>for the SGMII PCS.
>
>Signed-off-by: Michael Walle
Reviewed-by: Claudiu Manoil
gt;Signed-off-by: Michael Walle
Reviewed-by: Claudiu Manoil
tential type mistakes.
>
>This code was detected with the help of Coccinelle and, audited and
>fixed manually.
>
>Signed-off-by: Gustavo A. R. Silva
Reviewed-by: Claudiu Manoil
for centralized access
to the MDIO bus. Add the corresponding devicetree node and set it to be
the MDIO bus parent.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
Reviewed-by: Andrew Lunn
---
v1-v5 - none
.../boot/dts/freescale/fsl-ls1028a-qds.dts| 40
module build, provided separate kbuild module
for the driver
Claudiu Manoil (5):
enetc: Clean up local mdio bus allocation
enetc: Clean up makefile
enetc: Add mdio bus driver for the PCIe MDIO endpoint
dt-bindings: net: fsl: enetc: Add bindings for the central MDIO PCIe
endpoint
ff-by: Claudiu Manoil
---
v5 - added this patch
drivers/net/ethernet/freescale/enetc/Makefile | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/Makefile
b/drivers/net/ethernet/freescale/enetc/Makefile
index 7139e41
warning:
warning: incorrect type in assignment (different address spaces)
expected void *priv
got struct enetc_mdio_regs [noderef] *[assigned] regs
Fixes: ebfcb23d62ab ("enetc: Add ENETC PF level external MDIO support")
Signed-off-by: Claudiu Manoil
Reviewed-by: Andrew Lunn
-
a
separate MDIO bus and provides a driver for it by re-using
the code used for local MDIO access. It also allows the
ENETC port PHYs to be managed by this driver if the local
"mdio" node is missing from the ENETC port node.
Signed-off-by: Claudiu Manoil
Reviewed-by: Andrew Lunn
---
The on-chip PCIe root complex that integrates the ENETC ethernet
controllers also integrates a PCIe endpoint for the MDIO controller
providing for centralized control of the ENETC mdio bus.
Add bindings for this "central" MDIO Integrated PCIe Endpoint.
Signed-off-by: Claudiu Manoil
R
>-Original Message-
>From: YueHaibing
>Sent: Tuesday, July 30, 2019 5:30 PM
>To: Claudiu Manoil ; da...@davemloft.net
>Cc: linux-kernel@vger.kernel.org; net...@vger.kernel.org; YueHaibing
>
>Subject: [PATCH] enetc: Fix build error without PHYLIB
>
>If PHYLIB i
a
separate MDIO bus and provides a driver for it by re-using
the code used for local MDIO access. It also allows the
ENETC port PHYs to be managed by this driver if the local
"mdio" node is missing from the ENETC port node.
Signed-off-by: Claudiu Manoil
---
v1 - fixed mdio bus allocation
warning:
warning: incorrect type in assignment (different address spaces)
expected void *priv
got struct enetc_mdio_regs [noderef] *[assigned] regs
Fixes: ebfcb23d62ab ("enetc: Add ENETC PF level external MDIO support")
Signed-off-by: Claudiu Manoil
Reviewed-by: Andrew Lunn
-
support provided in the first patch.
Changes since v0:
v1 - fixed mdio bus allocation
v2 - cleaned up accessors to avoid casting
v3 - fixed spelling (mostly commit message)
v4 - fixed err path check blunder
Claudiu Manoil (4):
enetc: Clean up local mdio bus allocation
enetc: Add mdio bus driver for
The on-chip PCIe root complex that integrates the ENETC ethernet
controllers also integrates a PCIe endpoint for the MDIO controller
providing for centralized control of the ENETC mdio bus.
Add bindings for this "central" MDIO Integrated PCIe Endpoint.
Signed-off-by: Claudiu Manoil
R
for centralized access
to the MDIO bus. Add the corresponding devicetree node and set it to be
the MDIO bus parent.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
Reviewed-by: Andrew Lunn
---
v1-v4 - none
.../boot/dts/freescale/fsl-ls1028a-qds.dts| 40
>-Original Message-
>From: netdev-ow...@vger.kernel.org On
>Behalf Of Claudiu Manoil
>Sent: Monday, July 29, 2019 6:40 PM
>To: Andrew Lunn
>Cc: David S . Miller ; Rob Herring
>; Leo Li ; Alexandru Marginean
>; net...@vger.kernel.org;
>devicet...@vge
>-Original Message-
>From: Andrew Lunn
>Sent: Monday, July 29, 2019 6:35 PM
>To: Claudiu Manoil
>Cc: David S . Miller ; Rob Herring
>; Leo Li ; Alexandru Marginean
>; net...@vger.kernel.org;
>devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
The on-chip PCIe root complex that integrates the ENETC ethernet
controllers also integrates a PCIe endpoint for the MDIO controller
providing for centralized control of the ENETC mdio bus.
Add bindings for this "central" MDIO Integrated PCIe Endpoint.
Signed-off-by: Claudiu Manoil
---
support provided in the first patch.
Changes since v0:
v1 - fixed mdio bus allocation
v2 - cleaned up accessors to avoid casting
v3 - fixed spelling (mostly commit message)
Claudiu Manoil (4):
enetc: Clean up local mdio bus allocation
enetc: Add mdio bus driver for the PCIe MDIO endpoint
dt
for centralized access
to the MDIO bus. Add the corresponding devicetree node and set it to be
the MDIO bus parent.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v1 - none
v2 - none
v3 - none
.../boot/dts/freescale/fsl-ls1028a-qds.dts| 40 +++
.../arm64
warning:
warning: incorrect type in assignment (different address spaces)
expected void *priv
got struct enetc_mdio_regs [noderef] *[assigned] regs
Fixes: ebfcb23d62ab ("enetc: Add ENETC PF level external MDIO support")
Signed-off-by: Claudiu Manoil
---
v1 - added this p
a
separate MDIO bus and provides a driver for it by re-using
the code used for local MDIO access. It also allows the
ENETC port PHYs to be managed by this driver if the local
"mdio" node is missing from the ENETC port node.
Signed-off-by: Claudiu Manoil
---
v1 - fixed mdio bus allocation
for centralized access
to the MDIO bus. Add the corresponding devicetree node and set it to be
the MDIO bus parent.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v1 - none
v2 - none
.../boot/dts/freescale/fsl-ls1028a-qds.dts| 40 +++
.../arm64/boot/dts
.
Fixes following sparse warning:
warning: incorrect type in assignment (different address spaces)
expected void *priv
got struct enetc_mdio_regs [noderef] *[assigned] regs
Fixes: ebfcb23d62ab ("enetc: Add ENETC PF level external MDIO support")
CC: Andrew Lunn
Signed-off-by: Clau
a
separate MDIO bus and provides a driver for it by re-using
the code used for local MDIO access. It also allows the
ENETC port PHYs to be managed by this driver if the local
"mdio" node is missing from the ENETC port node.
Signed-off-by: Claudiu Manoil
---
v1 - fixed mdio bus allocation
The on-chip PCIe root complex that integrates the ENETC ethernet
controllers also integrates a PCIe enpoint for the MDIO controller
provinding for cetralized control of the ENETC mdio bus.
Add bindings for this "central" MDIO Integrated PCIe Endpoit.
Signed-off-by: Claudiu Manoil
---
provided for the new MDIO node, similarly to ENETC
port nodes bindings.
Last patch enables the ENETC port 1 and its RGMII PHY on the
LS1028A QDS board, where the MDIO muxing configuration relies
on the MDIO support provided in the first patch.
Claudiu Manoil (4):
enetc: Clean up local mdio bus
>-Original Message-
>From: Andrew Lunn
>Sent: Wednesday, July 24, 2019 6:18 PM
>To: Claudiu Manoil
>Cc: David S . Miller ; Rob Herring
>; Leo Li ; Alexandru Marginean
>; net...@vger.kernel.org;
>devicet...@vger.kernel.org; linux-arm-ker...@lists.in
a
separate MDIO bus and provides a driver for it by re-using
the code used for local MDIO access. It also allows the
ENETC port PHYs to be managed by this driver if the local
"mdio" node is missing from the ENETC port node.
Signed-off-by: Claudiu Manoil
---
v1 - fixed mdio bus allocation
The on-chip PCIe root complex that integrates the ENETC ethernet
controllers also integrates a PCIe enpoint for the MDIO controller
provinding for cetralized control of the ENETC mdio bus.
Add bindings for this "central" MDIO Integrated PCIe Endpoit.
Signed-off-by: Claudiu Manoil
---
signment (different address spaces)
expected void *priv
got struct enetc_mdio_regs [noderef] *[assigned] regs
Fixes: ebfcb23d62ab ("enetc: Add ENETC PF level external MDIO support")
Signed-off-by: Claudiu Manoil
---
v1 - added this patch
.../net/ethernet/freescale/enetc
for centralized access
to the MDIO bus. Add the corresponding devicetree node and set it to be
the MDIO bus parent.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v1 - none
.../boot/dts/freescale/fsl-ls1028a-qds.dts| 40 +++
.../arm64/boot/dts/freescale/fsl
provided for the new MDIO node, similarly to ENETC
port nodes bindings.
Last patch enables the ENETC port 1 and its RGMII PHY on the
LS1028A QDS board, where the MDIO muxing configuration relies
on the MDIO support provided in the first patch.
Claudiu Manoil (4):
enetc: Clean up local mdio bus
>-Original Message-
>From: netdev-ow...@vger.kernel.org On
>Behalf Of Claudiu Manoil
>Sent: Wednesday, July 24, 2019 12:53 PM
>To: Andrew Lunn
>Cc: David S . Miller ; devicet...@vger.kernel.org;
>net...@vger.kernel.org; Alexandru Marginean
>; linux-kernel
>-Original Message-
>From: Saeed Mahameed
[...]
>
>mdiobus_free(bus) is missing here and in every error path.
>
[...]
>
>this should come last to be symmetrical with probe flow.
>
Will clean these up too. Thanks.
>-Original Message-
>From: Andrew Lunn
>Sent: Wednesday, July 24, 2019 1:25 AM
>To: Claudiu Manoil
>Cc: David S . Miller ; devicet...@vger.kernel.org;
>net...@vger.kernel.org; Alexandru Marginean
>; linux-kernel@vger.kernel.org; Leo Li
>; Rob H
The on-chip PCIe root complex that integrates the ENETC ethernet
controllers also integrates a PCIe enpoint for the MDIO controller
provinding for cetralized control of the ENETC mdio bus.
Add bindings for this "central" MDIO Integrated PCIe Endpoit.
Signed-off-by: Clau
a
separate MDIO bus and provides a driver for it by re-using
the code used for local MDIO access. It also allows the
ENETC port PHYs to be managed by this driver if the local
"mdio" node is missing from the ENETC port node.
Signed-off-by: Claudiu Manoil
---
.../net/ethernet/freescale/ene
provided for the new MDIO node, similarly to ENETC
port nodes bindings.
Last patch enables the ENETC port 1 and its RGMII PHY on the
LS1028A QDS board, where the MDIO muxing configuration relies
on the MDIO support provided in the first patch.
Claudiu Manoil (3):
enetc: Add mdio bus driver for
for centralized access
to the MDIO bus. Add the corresponding devicetree node and set it to be
the MDIO bus parent.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
.../boot/dts/freescale/fsl-ls1028a-qds.dts| 40 +++
.../arm64/boot/dts/freescale/fsl
>-Original Message-
>From: Andrew Lunn
>Sent: Friday, July 5, 2019 7:50 AM
>To: Vladimir Oltean
>Cc: Alexandre Belloni ; Allan W. Nielsen
>; Claudiu Manoil ;
>David S . Miller ; devicet...@vger.kernel.org;
>net...@vger.kernel.org; Alexandru Marginean
>; l
>-Original Message-
>From: Andrew Lunn
>Sent: Saturday, June 22, 2019 11:57 PM
>To: Claudiu Manoil
[...]
Ok for all, I can work more on refactoring if we agree on the basics.
For instance I can change the driver to use reg-names, same as
mscc-ocelot, and factor out the
Hi Andrew,
>-Original Message-
>From: Andrew Lunn
>Sent: Friday, June 21, 2019 7:50 PM
>To: Claudiu Manoil
>Cc: David S . Miller ; devicet...@vger.kernel.org;
>Alexandre Belloni ; net...@vger.kernel.org;
>Alexandru Marginean ; linux-
>ker...@vger.kernel.org; ungl
This is just common path code that belogs to ocelot_init,
it has nothing to do with a specific SoC/board instance.
Add allocation err check in the process.
Signed-off-by: Claudiu Manoil
---
drivers/net/ethernet/mscc/ocelot.c | 6 ++
drivers/net/ethernet/mscc/ocelot_board.c | 4
2
apped.
Signed-off-by: Claudiu Manoil
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 58 ++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 4cdf84c
DT bindings for the Felix ethernet switch, consisting of the
VSC9959 switch core integrated as a PCIe endpoint device.
Signed-off-by: Claudiu Manoil
---
.../devicetree/bindings/net/mscc-felix.txt| 77 +++
1 file changed, 77 insertions(+)
create mode 100644 Documentation
Let's make this ioremap and regmap init code common. It should not
be platform dependent as it should be usable by PCI devices too.
Use better names where necessary to avoid clashes.
Signed-off-by: Claudiu Manoil
---
drivers/net/ethernet/mscc/ocelot.h | 4 +---
drivers/net/ethernet
configuration). There are also few
particularities described by individual patch messages.
Claudiu Manoil (6):
ocelot: Filter out ocelot SoC specific PCS config from common path
ocelot: Refactor common ocelot probing code to ocelot_init
ocelot: Factor out resource ioremap and regmap init
t and init. Because for this operation Ocelot
uses some bits that are not present on Felix, the later has to
use a register from the global registers block (GCB) instead.
Signed-off-by: Catalin Horghidan
Signed-off-by: Claudiu Manoil
---
drivers/net/ethernet/mscc/Kconfig | 8 +
drivers/ne
.
Signed-off-by: Claudiu Manoil
---
drivers/net/ethernet/mscc/ocelot.c | 17 ++---
drivers/net/ethernet/mscc/ocelot.h | 2 ++
drivers/net/ethernet/mscc/ocelot_regs.c | 21 +
3 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet
>-Original Message-
>From: Pavel Machek
>Sent: Friday, May 17, 2019 11:17 AM
>To: Greg Kroah-Hartman
>Cc: linux-kernel@vger.kernel.org; sta...@vger.kernel.org; Claudiu Manoil
>; David S. Miller ; Sasha
>Levin
>Subject: Re: [PATCH 4.19 042/113] ocelot: Dont
The LS1028A RDB board features an Atheros PHY connected over
SGMII to the ENETC PF0 (or Port0). ENETC Port1 (PF1) has no
external connection on this board, so it can be disabled for now.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v2 - added a mdio node as parent for the
PFs has an external ethernet port
on the LS1028A SoC.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v2 - none
v3 - none
v4 - changed enetc node names from "pci" to "ethernet" and
added compatible string (as requested by Rob H.)
arch/arm64/boot/dts/f
Each ENETC PF has its own MDIO interface, the corresponding
MDIO registers are mapped in the ENETC's Port register block.
The current patch adds a driver for these PF level MDIO buses,
so that each PF can manage directly its own external link.
Signed-off-by: Alex Marginean
Signed-off-by: Cl
Define connection bindings (external PHY connections and internal links)
for the ENETC on-chip ethernet controllers.
Signed-off-by: Claudiu Manoil
---
v3 - added this patch to the set
v4 - documented strictly the enetc node bindings, changed node type
from "pci" to "ethe
This is the missing part to enable PCI probing of the ENETC ethernet
ports on the LS1028A SoC and external traffic on the LS1028A RDB board.
It's one of the first items on the TODO list for the recently merged
ENETC ethernet driver.
v3: Add DT bindings doc for ENETC connections
v4: none
Cl
>-Original Message-
>From: Rob Herring
>Sent: Saturday, February 23, 2019 1:38 AM
>To: Claudiu Manoil
>Cc: Shawn Guo ; Leo Li ; David S .
>Miller ; Alexandru Marginean
>; linux-arm-ker...@lists.infradead.org;
>devicet...@vger.kernel.org; net...@vger
Each ENETC PF has its own MDIO interface, the corresponding
MDIO registers are mapped in the ENETC's Port register block.
The current patch adds a driver for these PF level MDIO buses,
so that each PF can manage directly its own external link.
Signed-off-by: Alex Marginean
Signed-off-by: Cl
Define connection bindings (external PHY connections and internal links)
for the ENETC on-chip ethernet controllers.
Signed-off-by: Claudiu Manoil
---
v3 - added this patch to the set
.../devicetree/bindings/net/fsl-enetc.txt | 109 +
1 file changed, 109 insertions
PFs has an external ethernet port
on the LS1028A SoC.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v2 - none
v3 - none
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 33 ++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls
The LS1028A RDB board features an Atheros PHY connected over
SGMII to the ENETC PF0 (or Port0). ENETC Port1 (PF1) has no
external connection on this board, so it can be disabled for now.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v2 - added a mdio node as parent for the
This is the missing part to enable PCI probing of the ENETC ethernet
ports on the LS1028A SoC and external traffic on the LS1028A RDB board.
It's one of the first items on the TODO list for the recently merged
ENETC ethernet driver.
v3: Add DT bindings doc for ENETC connections
Claudiu Mano
>-Original Message-
>From: Andrew Lunn
>Sent: Friday, February 15, 2019 3:35 PM
>To: Claudiu Manoil
>Cc: Shawn Guo ; Leo Li ; David S .
>Miller ; Alexandru Marginean
>; linux-arm-ker...@lists.infradead.org;
>devicet...@vger.kernel.org; net...@vger
The LS1028A RDB board features an Atheros PHY connected over
SGMII to the ENETC PF0 (or Port0). ENETC Port1 (PF1) has no
external connection on this board, so it can be disabled for now.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v2 - added a mdio node as parent for the
PFs has an external ethernet port
on the LS1028A SoC.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
v2 - none
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 33 ++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dt
Each ENETC PF has its own MDIO interface, the corresponding
MDIO registers are mapped in the ENETC's Port register block.
The current patch adds a driver for these PF level MDIO buses,
so that each PF can manage directly its own external link.
Signed-off-by: Alex Marginean
Signed-off-by: Cl
This is the missing part to enable PCI probing of the ENETC ethernet
ports on the LS1028A SoC and external traffic on the LS1028A RDB board.
It's one of the first items on the TODO list for the recently merged
ENETC ethernet driver.
Claudiu Manoil (3):
arm64: dts: fsl: ls1028a: Add PCI
>-Original Message-
>From: Andrew Lunn
>Sent: Thursday, February 14, 2019 6:28 PM
>To: Claudiu Manoil
>Cc: Shawn Guo ; Leo Li ; David S .
>Miller ; devicet...@vger.kernel.org; Alexandru
>Marginean ; linux-kernel@vger.kernel.org;
>linux-arm-ker...@
>-Original Message-
>From: Andrew Lunn
>Sent: Wednesday, February 13, 2019 8:13 PM
>To: Claudiu Manoil
>Cc: Shawn Guo ; Leo Li ; David S .
>Miller ; devicet...@vger.kernel.org; Alexandru
>Marginean ; linux-kernel@vger.kernel.org;
>linux-arm-ker...@
>-Original Message-
>From: Andrew Lunn
>Sent: Wednesday, February 13, 2019 8:16 PM
>To: Claudiu Manoil
>Cc: Shawn Guo ; Leo Li ; David S .
>Miller ; devicet...@vger.kernel.org; Alexandru
>Marginean ; linux-kernel@vger.kernel.org;
>linux-arm-ker...@
This is the missing part to enable PCI probing of the ENETC ethernet
ports on the LS1028A SoC and external traffic on the LS1028A RDB board.
It's one of the first items on the TODO list for the recently merged
ENETC ethernet driver.
Claudiu Manoil (3):
arm64: dts: fsl: ls1028a: Add PCI
The LS1028A RDB board features an Atheros PHY connected over
SGMII to the ENETC PF0 (or Port0). ENETC Port1 (PF1) has no
external connection on this board, so it can be disabled for now.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
arch/arm64/boot/dts/freescale/fsl-ls1028a
PFs has an external ethernet port
on the LS1028A SoC.
Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 33 ++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/
Each ENETC PF has its own MDIO interface, the corresponding
MDIO registers are mapped in the ENETC's Port register block.
The current patch adds a driver for these PF level MDIO buses,
so that each PF can manage directly its own external link.
Signed-off-by: Alex Marginean
Signed-off-by: Cl
>-Original Message-
>From: David Miller
>Sent: Saturday, November 17, 2018 10:08 PM
>To: Claudiu Manoil
>Cc: net...@vger.kernel.org; linux-kernel@vger.kernel.org; Alexandru
>Marginean ; Catalin Horghidan
>
>Subject: Re: [PATCH net-next 1/4] enetc: Introdu
>-Original Message-
>From: Andrew Lunn
>Sent: Saturday, November 17, 2018 2:30 AM
>To: Claudiu Manoil
>Cc: David S . Miller ; net...@vger.kernel.org; linux-
>ker...@vger.kernel.org; Alexandru Marginean
>; Catalin Horghidan
>
>Subject: Re: [PATCH net-next 1/4
>-Original Message-
>From: Colin King [mailto:colin.k...@canonical.com]
>Sent: Wednesday, July 4, 2018 10:55 AM
>To: Claudiu Manoil ; David S . Miller
>; net...@vger.kernel.org
>Cc: kernel-janit...@vger.kernel.org; linux-kernel@vger.kernel.org
>Subject:
The freescale.com address will no longer be available.
Signed-off-by: Claudiu Manoil
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 73c0cda..274ba58 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5637,7 +5637,7 @@ S
>-Original Message-
>From: Zumeng Chen [mailto:zumeng.c...@gmail.com]
>Sent: Monday, December 04, 2017 5:22 AM
>To: net...@vger.kernel.org; linux-kernel@vger.kernel.org
>Cc: Claudiu Manoil ; da...@davemloft.net
>Subject: [PATCH 1/1] gianfar: fix a flooded alignment
>-Original Message-
>From: Thomas Graziadei [mailto:thomas.grazia...@omicronenergy.com]
>Sent: Monday, February 13, 2017 2:22 PM
>To: claudiu.man...@freescale.com; net...@vger.kernel.org; linux-
>ker...@vger.kernel.org
>Cc: Thomas Graziadei
>Subject: [PATCH 1/2] gianfar: Deal with link sta
>-Original Message-
>From: Arseny Solokha [mailto:asolo...@kb.kras.ru]
>Sent: Sunday, January 29, 2017 2:52 PM
>To: Claudiu Manoil
>Cc: net...@vger.kernel.org; linux-kernel@vger.kernel.org; Arseny Solokha
>
>Subject: [PATCH] gianfar: synchronize DMA API usage b
Add self tests for the DPAA 1.x Queue Manager driver. The tests
ensure that the driver can properly enqueue and dequeue to/from
frame queues using the QMan portal infrastructure.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
v2: none
drivers/soc/fsl/qbman/Kconfig | 23
Enable the drivers on the powerpc arch.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
v2: none
arch/powerpc/Makefile| 4 ++--
arch/powerpc/configs/dpaa.config | 1 +
drivers/soc/Kconfig | 1 +
drivers/soc/fsl/Makefile | 1 +
4 files changed, 5
Add a self test for the DPAA 1.x Buffer Manager driver. This
test ensures that the driver can properly acquire and release
buffers using the BMan portal infrastructure.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
v2: none
drivers/soc/fsl/qbman/Kconfig | 16
Add basic support for the Data Path Acceleration Architecture v1.x
(DPAA 1.x) hardware infrastructure and accelerators found on multicore
Freescale SoCs, commonly known as the QorIQ series.
CC: Roy Pledge
Claudiu Manoil (5):
soc/fsl: Introduce DPAA 1.x BMan device driver
soc/fsl: Introduce
This driver enables the Freescale DPAA 1.x Buffer Manager block.
BMan is a hardware accelerator that manages buffer pools. It allows
CPUs and other accelerators connected to the SoC datapath to acquire
and release buffers during data processing.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu
Add basic support for the Data Path Acceleration Architecture v1.x
(DPAA 1.x) hardware infrastructure and accelerators found on multicore
Freescale SoCs, commonly known as the QorIQ series.
CC: Roy Pledge
Claudiu Manoil (5):
soc/fsl: Introduce DPAA 1.x BMan device driver
soc/fsl: Introduce
This driver enables the Freescale DPAA 1.x Buffer Manager block.
BMan is a hardware accelerator that manages buffer pools. It allows
CPUs and other accelerators connected to the SoC datapath to acquire
and release buffers during data processing.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu
Add a self test for the DPAA 1.x Buffer Manager driver. This
test ensures that the driver can properly acquire and release
buffers using the BMan portal infrastructure.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
drivers/soc/fsl/qbman/Kconfig | 16
drivers/soc/fsl
Enable the drivers on the powerpc arch.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
arch/powerpc/Makefile| 4 ++--
arch/powerpc/configs/dpaa.config | 1 +
drivers/soc/Kconfig | 1 +
drivers/soc/fsl/Makefile | 1 +
4 files changed, 5 insertions
Add self tests for the DPAA 1.x Queue Manager driver. The tests
ensure that the driver can properly enqueue and dequeue to/from
frame queues using the QMan portal infrastructure.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
drivers/soc/fsl/qbman/Kconfig | 23
The "fsl,wake-on-filer" DT binding enables this capability
on certain platforms that feature the necessary power
management infrastructure, targeting mainly printing and
imaging applications.
(refer to Power Management section of the SoC Ref Man)
Cc: Li Yang
Cc: Zhao Chenhui
Signed-
Enable the "wake-on-filer" (aka. wake on user defined packet)
wake on lan capability for the eTSEC ethernet nodes.
Cc: Li Yang
Cc: Zhao Chenhui
Signed-off-by: Claudiu Manoil
---
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ar
Add the "fsl,wake-on-filer" property for eTSEC nodes to
indicate that the system has the power management
infrastructure needed to be able to wake up the system
via FGPI (filer, aka. h/w rx parser) interrupt.
Cc: Li Yang
Cc: Zhao Chenhui
Signed-off-by: Claudiu Manoil
---
Doc
Add basic support for all the eTSEC controllers on the
ls1021a SoC. Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.
Signed-off-by: Alison Wang
Signed-off-by: Claudiu Manoil
---
v2: various findings, added 2nd
This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.
Signed-off-by: Alison Wang
Signed-off-by: Claudiu Manoil
---
v2, v3 - none;
arch/arm
Update the eTSEC bindings document with missing info on
properties that are already in use for the PPC platforms:
* "tbi-phy" property;
* "fsl,etsec2" compatibility string;
Signed-off-by: Claudiu Manoil
---
v2 - none;
v3 - added "tbi-handle" documentation;
- f
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