From: Chew, Chiau Ee
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.
Signed-off-by: Chew, Chiau Ee
---
drivers/spi/spi-pxa2xx.c |8 ++--
1 files changed, 6
From: Chew, Chiau Ee
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.
Signed-off-by: Chew, Chiau Ee
Acked-by: Mika Westerberg
---
drivers/spi/spi-pxa2xx.c |2 +-
1
From: Chew, Chiau Ee
SPI PXA2XX core layer has dependency on common clock framework
to obtain information on host supported clock rate. Thus, we
setup the clock device in the PCI glue layer to enable PCI mode
host pass in the clock rate information.
Signed-off-by: Chew, Chiau Ee
---
drivers
From: Darren Hart
Allow spi-pxa2xx-pci with common clock framework support to build as a
module by exporting clk_register_clkdev.
Signed-off-by: Darren Hart
Reviewed-by: Chew, Chiau Ee
Cc: Mika Westerberg
---
drivers/clk/clkdev.c |1 +
1 files changed, 1 insertions(+), 0 deletions
From: Chew, Chiau Ee
SPI PXA2XX core layer depends on common clock framework to obtain
information on host supported clock rate. Thus, we setup and register
clock device for PCI mode host in SPI PXA2XX pci glue layer using
common clock APIs.
In addition, in order for PCI mode SPI PXA2XX with
>
> Hi,
>
> On Wed, May 14, 2014 at 07:00:59AM +, Chew, Chiau Ee wrote:
> > Heikki,
> > For ACPI mode, the clock rate information for PWM is being setup in the
> acpi_lpss.c layer.
> > Thus, only PCI mode depends on the driver_data to pass in the clock rate
> Unlike other Intel LPSS devices, the PWM does not have the clock dividers or
> the gate. All we get from the clock is the rate. Since PCI case uses the
> driver
> data to get the rate, we can drop the clk and use the same data also in case
> of
> ACPI. The frequency is the same.
>
> Signed-of
From: Alan Cox
Not all systems enumerate the PWM devices via ACPI. They can also be exposed
via the PCI interface.
Signed-off-by: Alan Cox
Signed-off-by: Chew, Chiau Ee
---
drivers/pwm/pwm-lpss.c | 161 ++-
1 files changed, 130 insertions(+), 31
From: Chew, Chiau Ee
Similar to CE4100, BayTrail LPSS SPI can be PCI enumerated
as well. Thus, the functions are renamed from ce4100_xxx
to pxa2xx_spi_pci_xxx to clarify that this is a generic
PCI glue layer. Also, added required infrastructure to
support SPI hosts with different configurations
From: Chew, Chiau Ee
Hi,
BayTrail LPSS subsystem consists of one SPI host which can be PCI
enumerated. PXA2XX PCI layer used to support only CE4100's SPI. Thus,
we convert it into a generic PCI layer to add support for LPSS
SPI as well.
Since PCI mode LPSS SPI does not rely on common
From: Chew, Chiau Ee
Intel BayTrail PCI mode LPSS devices inclusive of SPI do not rely
on common clock framework. Thus, this patch allows the PCI mode
SPI host to pass the supported clock rate info to the core layer
which eventually used for speed calculation.
Signed-off-by: Chew, Chiau Ee
From: Alan Cox
Not all systems enumerate the PWM devices via ACPI. They can also be exposed
via the PCI interface.
Signed-off-by: Alan Cox
Signed-off-by: Chew, Chiau Ee
---
drivers/pwm/pwm-lpss.c | 159 ++-
1 files changed, 128 insertions(+), 31
> On Tue, Apr 15, 2014 at 08:41:02AM +0000, Chew, Chiau Ee wrote:
> >
> >
> > > > +static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev,
> > > > + struct resource *r, struct pwm_lpss_boardinfo
> > > > *info)
&g
> On Mon, Apr 14, 2014 at 02:05:25AM +0000, Chew, Chiau Ee wrote:
> > > > MODULE_DESCRIPTION("PWM driver for Intel LPSS");
> > > >MODULE_AUTHOR("Mika Westerberg
> > > >");
> > > > MODULE_LICENSE("GPL v2");
> &g
> > +static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev,
> > + struct resource *r, struct pwm_lpss_boardinfo *info)
> > {
> > struct pwm_lpss_chip *lpwm;
> > - struct resource *r;
> > int ret;
> >
> > - lpwm = devm_kzalloc(&pdev->dev, sizeof(*lpwm), GFP_
> > MODULE_DESCRIPTION("PWM driver for Intel LPSS");
> >MODULE_AUTHOR("Mika
> > Westerberg ");
> > MODULE_LICENSE("GPL v2");
> > MODULE_ALIAS("platform:pwm-lpss");
>
> Looks a good idea to combine pci and acpi driver together.
> Since pci driver is added, here the alias need to be refined.
> Ot
From: Alan Cox
Not all systems enumerate the PWM devices via ACPI. They can also be exposed
via the PCI interface.
Signed-off-by: Alan Cox
Signed-off-by: Chew, Chiau Ee
---
drivers/pwm/pwm-lpss.c | 160 ++-
1 files changed, 129 insertions(+), 31
From: Mika Westerberg
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg
Signed-off-by: Chew, Kean Ho
Signed-off-by: Chang, Rebecca Swee Fun
Signed-off-by: Chew, Chiau Ee
---
changelog v3:
* check validity of
> On Fri, Feb 28, 2014 at 10:50:57PM +0800, Chew Chiau Ee wrote:
> > From: Mika Westerberg
> >
> > Add support for Intel Low Power I/O subsystem PWM controllers found on
> > Intel BayTrail SoC.
> >
> > Signed-off-by: Mika Westerberg
> > Signed-of
From: Chew, Chiau Ee
This is to disable/enable DW_DMAC hw during late suspend/early resume.
Since DMA is providing service to other clients (eg: SPI, HSUART),
we need to ensure DMA suspends after the clients and resume
before the clients are active.
Signed-off-by: Chew, Chiau Ee
---
v2
> Subject: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA
> hold time value
>
> From: Chew, Chiau Ee
>
> On Intel BayTrail, there was case whereby the resulting fast mode bus speed
> becomes slower (~20% slower compared to expected speed) if using the
&
From: Chew, Chiau Ee
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold
From: Chew, Chiau Ee
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold
> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: Sunday, March 09, 2014 5:04 PM
> To: Chew, Chiau Ee
> Cc: Mika Westerberg; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/2] i2c: designware-pci: set ideal
> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: Sunday, March 09, 2014 4:54 PM
> To: Chew, Chiau Ee
> Cc: Mika Westerberg; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/2] i2c: designware-pci: add 10-b
From: Chew, Chiau Ee
These two patches contains the additional changes required for BayTrail LPSS
I2C on top of the patch that Mika Westerberg has submitted previously which
is still in the pending queue:
"[PATCH v2] i2c: designware-pci: Add Baytrail PCI IDs"
http://www.spinics.net/l
From: Chew, Chiau Ee
All the I2C controllers on Intel BayTrail LPSS subsystem able
to support 10-bit addressing mode functionality.
Signed-off-by: Chew, Chiau Ee
Signed-off-by: Ong, Boon Leong
---
drivers/i2c/busses/i2c-designware-pcidrv.c | 17 +++--
1 files changed, 11
From: Chew, Chiau Ee
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold
LPSS, etc.
Signed-off-by: Chew, Kean Ho
Signed-off-by: Chew, Chiau Ee
---
drivers/pinctrl/pinctrl-baytrail.c | 42 +--
1 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-baytrail.c
b/drivers/pinctrl/pinctrl-baytrail.c
index
From: Chew, Kean ho
Add Device ID of Intel BayTrail SMBus Controller.
Signed-off-by: Chew, Kean ho
Signed-off-by: Chew, Chiau Ee
---
Documentation/i2c/busses/i2c-i801 |1 +
drivers/i2c/busses/Kconfig|1 +
drivers/i2c/busses/i2c-i801.c |3 +++
3 files changed, 5
From: Mika Westerberg
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg
Signed-off-by: Chew, Kean Ho
Signed-off-by: Chang, Rebecca Swee Fun
Signed-off-by: Chew, Chiau Ee
---
drivers/pwm/Kconfig| 10 +++
drivers
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Thursday, February 27, 2014 9:14 PM
> To: Chew, Chiau Ee
> Cc: Thierry Reding; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> Chew, Kean Ho; Chang, Rebecca Swee
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Thursday, February 27, 2014 5:02 PM
> To: Thierry Reding
> Cc: Chew, Chiau Ee; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> Chew, Kean Ho; Chang, Rebecca Swee
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: Wednesday, January 22, 2014 5:31 PM
> To: Thierry Reding
> Cc: One Thousand Gnomes; Chew, Chiau Ee; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Chew, Kean Ho; C
From: Chew, Chiau Ee
Intel BayTrail LPSS consists of two PWM controllers which can
be enumerated from ACPI namespace. This change will cause
platform device objects to be created for Intel BayTrail PWM
controllers which will allow the pwm-lpss driver to bind to them
and handle those devices
> -Original Message-
> From: Andy Shevchenko [mailto:andriy.shevche...@linux.intel.com]
> Sent: Monday, January 27, 2014 6:17 PM
> To: Koul, Vinod
> Cc: Andy Shevchenko; Chew, Chiau Ee; Viresh Kumar; Williams, Dan J;
> dmaeng...@vger.kernel.org; linux-kernel@vger.kernel
From: Chew, Chiau Ee
Intel BayTrail LPSS consists of two PWM controllers which can
be enumerated from ACPI namespace.
Signed-off-by: Chew, Chiau Ee
---
drivers/acpi/acpi_lpss.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/acpi/acpi_lpss.c b
From: Mika Westerberg
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg
Signed-off-by: Chew, Kean Ho
Signed-off-by: Chang, Rebecca Swee Fun
Signed-off-by: Chew, Chiau Ee
---
drivers/pwm/Kconfig| 10 +++
drivers
PM
To: Koul, Vinod
Cc: Chew, Chiau Ee; Viresh Kumar; Andy Shevchenko; Williams, Dan J;
dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dma: dw: Add suspend and resume handling for PCI mode
DW_DMAC.
On Tue, 2013-12-10 at 15:40 +0530, Vinod Koul wrote:
> On Tue, Dec
From: Chew, Chiau Ee
This is to disable/enable DW_DMAC hw during suspend/resume.
Signed-off-by: Chew, Chiau Ee
Acked-by: Andy Shevchenko
---
drivers/dma/dw/pci.c | 33 +
1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/dw/pci.c b
From: Chew, Chiau Ee
The Intel LPSS SPI private register bits have to be restored
when system resume from S3 suspend.
Signed-off-by: Chew, Chiau Ee
Acked-by: Mika Westerberg
---
drivers/spi/spi-pxa2xx.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi
;t be detected from hardware register, so we will always set the
IC_10BITADDR_MASTER bit in both IC_CON and IC_TAR register whenever 10-bit
addresing mode is requested by user application.
Signed-off-by: Chew, Chiau Ee
Reviewed-by: Mika Westerberg
---
drivers/i2c/busses/i2c-designware-core.c |
On Wed, Jul 03, 2013 at 10:15:11PM +0200, Wolfram Sang wrote:
>
> CCing Mika and Christian.
>
> On Fri, Jun 21, 2013 at 03:05:28PM +0800, Chew Chiau Ee wrote:
> > From: Chew, Chiau Ee
> >
> > If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1,
>
From: Chew, Chiau Ee
If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1, the
Designware I2C controller doesn't generate RESTART unless user specifically
requests it by setting RESTART bit in IC_DATA_CMD register.
Since IC_EMPTYFIFO_HOLD_MASTER_EN setting can't be det
From: Chew, Chiau Ee
Add HD Audio Device PCI ID for the Intel BayTrail platform.
Signed-off-by: Chew, Chiau Ee
Signed-off-by: Artem Bityutskiy
---
sound/pci/hda/hda_intel.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda
From: Chew, Chiau Ee
Adds IDE-mode SATA Device IDs for the Intel BayTrail platform.
Signed-off-by: Chew, Chiau Ee
Signed-off-by: Artem Bityutskiy
---
drivers/ata/ata_piix.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/drivers/ata/ata_piix.c b
From: Chew, Chiau Ee
Add HD Audio Device PCI ID for the Intel BayTrail platform.
Signed-off-by: Chew, Chiau Ee
Signed-off-by: Artem Bityutskiy
---
sound/pci/hda/hda_intel.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda
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