* Paul E. McKenney wrote:
> Nothing in the control-dependencies section of memory-barriers.txt
> says that control dependencies don't extend beyond the end of the
> if-statement containing the control dependency. Worse yet, in many
> situations, they do extend beyond that if-statement. In part
* Thomas Garnier wrote:
> arch/x86/include/asm/kaslr.h| 12 +++
Hm, what tree is this patch against? asm/kaslr.h does not exist upstream or in
the
x86 tree.
Thanks,
Ingo
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* Ingo Molnar wrote:
>
> * Thomas Garnier wrote:
>
> > arch/x86/include/asm/kaslr.h| 12 +++
>
> Hm, what tree is this patch against? asm/kaslr.h does not exist upstream or
> in the
> x86 tree.
Ah, never mind, introduced by the first patch.
Thanks,
Ingo
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* Ingo Molnar wrote:
>
> * Thomas Garnier wrote:
>
> > arch/x86/include/asm/kaslr.h| 12 +++
>
> Hm, what tree is this patch against? asm/kaslr.h does not exist upstream or
> in the
> x86 tree.
So the problem is that this file gets introduced by:
[PATCH v5 1/4] x86, boot:
On Thu, Jun 09, 2016 at 04:53:48PM +0200, Benjamin Tissoires wrote:
> SMBus Host Notify allows a slave device to act as a master on a bus to
> notify the host of an interrupt. On Intel chipsets, the functionality
> is directly implemented in the firmware. We just need to export a
> function to call
On Thu, Jun 09, 2016 at 04:53:47PM +0200, Benjamin Tissoires wrote:
> .alert() is meant to be generic, but there is currently no way
> for the device driver to know which protocol generated the alert.
> Add a parameter in .alert() to help the device driver to understand
> what is given in data.
>
On Fri, 2016-06-17 at 08:56 +0300, Alexander Shishkin wrote:
> Ben Hutchings writes:
>
> > When kernel.perf_event_open is set to 3 (or greater), disallow all
> > access to performance events by users without CAP_SYS_ADMIN.
> > Add a Kconfig symbol CONFIG_SECURITY_PERF_EVENTS_RESTRICT that
> > mak
Add resource managed version of i2c_new_dummy().
This helps in:
1. reducing the code size in error path to explicitly unregister
the new dummy client.
2. Sometime, need of the remove callback on client driver to just
unregister the new i2c dummy client.
Signed-off-by: Laxman Dewangan
i2c_new_dummy() gained their devm_ wrappers. Add the
devm_i2c_new_dummy() in managed APIs list.
Signed-off-by: Laxman Dewangan
---
Changes form V2:
- Drop the devm_i2c_unregister_device()
Documentation/driver-model/devres.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/
Hi,
[auto build test WARNING on wsa/i2c/for-next]
[also build test WARNING on next-20160617]
[cannot apply to v4.7-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Laxman-Dewangan/i2c-core
> As a debian user, is this a good place to complain? Because it does
> get
> it the way.
It would be relevant to whether or not it should be set to 3 by default
in the kernel without explicit configuration, but there's no proposal to
do that. Debian has to pick a trade-off beyond security and a t
The default reader spining threshold is current set to 4096. However,
the right reader spinning threshold may vary from one system to
another and among the different architectures. This patch adds a new
kernel boot parameter to modify the threshold value. This enables
better tailoring to the needs
This patch enables readers to optimistically spin when the
rspin_threshold is non-zero. That threshold value should only
be set when the lock owners of the rwsem are unlikely to go to
sleep. Otherwise enabling reader spinning may make the performance
worse in some cases.
On a 4-socket Haswell mach
Reader optimistic spinning will be disabled once the rspin_enabled
count reaches 0. After that, it cannot be re-enabled. This may cause
an eligible rwsem locked out of reader spinning because of a series
of unfortunate events.
This patch looks at the regular writer-on-writer spinning history. If
t
When the count value is in between 0 and RWSEM_WAITING_BIAS, there
are 2 possibilities. Either a writer is present and there is no
waiter or there are waiters and readers. There is no easy way to
know which is true unless the wait_lock is taken.
This patch changes the RWSEM_WAITING_BIAS from 0xfff
Move the rwsem_down_read_failed() function down to below the
optimistic spinning section before enabling optimistic spinning for
the readers. It is because the rwsem_down_read_failed() function will
call rwsem_optimistic_spin() in later patch.
There is no change in code.
Signed-off-by: Waiman Lon
The osq_lock() and osq_unlock() function may not provide the necessary
acquire and release barrier in some cases. This patch makes sure
that the proper barriers are provided when osq_lock() is successful
or when osq_unlock() is called.
The change on the unlock side is more for documentation purpos
Currently, when down_read() fails, the active read locking isn't undone
until the rwsem_down_read_failed() function grabs the wait_lock. If the
wait_lock is contended, it may takes a while to get the lock. During
that period, writer lock stealing will be disabled because of the
active read lock.
T
This patch modifies rwsem_spin_on_owner() to return a tri-state value
to better reflect the state of lock holder which enables us to make a
better decision of what to do next.
Signed-off-by: Waiman Long
---
kernel/locking/rwsem-xadd.c | 14 +-
1 files changed, 9 insertions(+), 5 de
v2->v3:
- Used smp_acquire__after_ctrl_dep() to provide acquire barrier.
- Added the following new patches:
1) make rwsem_spin_on_owner() return a tristate value.
2) reactivate reader spinning when there is a large number of
favorable writer-on-writer spinnings.
3) move all the rws
When the rwsem is owned by reader, writers stop optimistic spinning
simply because there is no easy way to figure out if all the readers
are actively running or not. However, there are scenarios where
the readers are unlikely to sleep and optimistic spinning can help
performance.
This patch provid
Almost all the macro definitions in the various architecture specific
rwsem.h header files are essentially the same. This patch moves all
of them into a common header asm-generic/rwsem_types.h to eliminate
the duplication.
Suggested-by: Peter Zijlstra (Intel)
Signed-off-by: Waiman Long
---
arch
On Thu, 16 Jun, at 09:38:31AM, Tom Lendacky wrote:
>
> Ok, I think this was happening before the commit to build our own
> EFI page table structures:
>
> commit 67a9108ed ("x86/efi: Build our own page table structures")
>
> Before this commit the boot services ended up mapped into the kernel
> p
On Fri, 2016-06-17 at 08:54 +0200, Peter Zijlstra wrote:
> On Thu, Jun 16, 2016 at 03:27:55PM -0700, Kees Cook wrote:
> > Hi guys,
> >
> > This patch wasn't originally CCed to you (I'm fixing that now).
> > Would
> > you consider taking this into the perf tree?
>
> No.
>
> > It's been in active
On Mon, Jun 13, 2016 at 04:19:06PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> In preparation for the Arria10 ECC modules, check the status
> of the parent in the device tree to ensure the block is enabled.
> Skip if no parent phandle is set in the device tree.
>
> Signed
On 06/17/2016 11:46 AM, Borislav Petkov wrote:
On Mon, Jun 13, 2016 at 04:19:06PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phan
On Mon, Jun 13, 2016 at 04:19:07PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> In preparation for additional memory module ECCs, the
> IRQ function will check a panic flag before doing a
> kernel panic on double bit errors. ECCs on buffers
> will not cause a kernel panic o
On Fri, Jun 17, 2016 at 11:54:04AM -0500, Thor Thayer wrote:
> Yes. Thanks! I will make the change.
No need, already did and applied. You can drop this patch from your
queue.
Thanks.
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Boris.
ECO tip #101: Trim your mails when you reply.
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On Mon, Jun 13, 2016 at 04:19:08PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> In preparation for additional memory module ECCs, the IRQ and
> check_deps() functions are being made available to all the memory
> buffers. Move them outside of the OCRAM only area.
>
> Signed
Hi Boris,
On 06/17/2016 11:51 AM, Borislav Petkov wrote:
On Mon, Jun 13, 2016 at 04:19:07PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors
On Fri, Jun 17, 2016 at 12:05:41PM -0500, Thor Thayer wrote:
> That is a good question. We have 2 important uses for OCRAM 1) to hold our
> power-down/sleep and resume functions and 2) to hold our FPGA contents
> during sleep. If either of these is corrupted, it is better to panic than to
> load so
Hi Boris,
On 06/17/2016 12:00 PM, Borislav Petkov wrote:
On Mon, Jun 13, 2016 at 04:19:08PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Mo
On 06/17/2016 12:02 PM, Borislav Petkov wrote:
On Fri, Jun 17, 2016 at 12:05:41PM -0500, Thor Thayer wrote:
That is a good question. We have 2 important uses for OCRAM 1) to hold our
power-down/sleep and resume functions and 2) to hold our FPGA contents
during sleep. If either of these is corr
On Fri, Jun 17, 2016 at 12:09:59PM -0500, Thor Thayer wrote:
> Since each peripheral's EDAC can be individually selected, the build
> generates a warning of an unused function if just L2 cache was selected.
>
> The ifdeffery is ugly but it removes that warning in the L2 only case.
You could add _
On Mon, Jun 13, 2016 at 04:19:10PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> In preparation for additional memory module ECCs, add the
> memory initialization functions and helper functions used
> for memory initialization.
>
> Signed-off-by: Thor Thayer
> ---
> v2: Sp
On Mon, Jun 13, 2016 at 04:19:11PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
> to support a common compatibility string for all ethernet
> FIFOs in the DT.
>
> Signed-off-by: Thor Thayer
> ---
> v2 Remove (v
Hi Boris,
On 06/17/2016 12:11 PM, Borislav Petkov wrote:
On Fri, Jun 17, 2016 at 12:09:59PM -0500, Thor Thayer wrote:
Since each peripheral's EDAC can be individually selected, the build
generates a warning of an unused function if just L2 cache was selected.
The ifdeffery is ugly but it remov
On 06/17/2016 12:21 PM, Borislav Petkov wrote:
On Mon, Jun 13, 2016 at 04:19:10PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Sign
Hi Boris,
On 06/17/2016 12:29 PM, Borislav Petkov wrote:
On Mon, Jun 13, 2016 at 04:19:11PM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.
Si
Em Fri, Jun 17, 2016 at 12:16:47PM -0400, Daniel Micay escreveu:
> On Fri, 2016-06-17 at 08:54 +0200, Peter Zijlstra wrote:
> > This Changelog is completely devoid of information. _WHY_ are you
> > doing this?
> Attack surface reduction. It's possible to use seccomp-bpf for some
> limited cases,
On 06/10/2016 11:44 AM, Guenter Roeck wrote:
> On Fri, Jun 10, 2016 at 10:32:33AM -0500, Andrew F. Davis wrote:
>> Add support for the the INA3221 26v capable, Triple channel,
>> Bi-Directional, Zero-Drift, Low-/High-Side, Current/Voltage Monitor
>> with I2C interface.
>>
>> Signed-off-by: Andrew F
The only difference is that non-compat version forces O_LARGEFILE,
and it should be the default behaviour for all architectures, as
we don't support 32-bit off_t. The only exception is tile32, that
continues with compat version of syscalls.
Signed-off-by: Yury Norov
Acked-by: Arnd Bergmann
Acked
Based on Andrew Pinski's patch-series.
Signed-off-by: Yury Norov
---
Documentation/arm64/ilp32.txt | 54 +++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/arm64/ilp32.txt
diff --git a/Documentation/arm64/ilp32.txt b/Documentation/arm6
From: Andrew Pinski
Add a separate syscall-table for ILP32, which dispatches either to native
LP64 system call implementation or to compat-syscalls, as appropriate.
Signed-off-by: Andrew Pinski
Signed-off-by: Yury Norov
---
arch/arm64/include/asm/unistd.h | 6 ++-
arch/arm64/kernel/Makefile
Signed-off-by: Yury Norov
---
arch/arm64/include/asm/signal32_common.h | 25 +++
arch/arm64/kernel/Makefile | 2 +-
arch/arm64/kernel/signal32.c | 85 ---
arch/arm64/kernel/signal32_common.c | 115 +++
4 files
From: Andrew Pinski
This patch adds the config option for ILP32.
Signed-off-by: Andrew Pinski
Signed-off-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Yury Norov
Reviewed-by: David Daney
---
arch/arm64/Kconfig | 10 +-
1 file changed, 9 insertions(+), 1 delet
From: Andrew Pinski
ILP32 uses AARCH32 compat structures and syscall handlers for signals.
But ILP32 struct rt_sigframe and ucontext differs from both LP64 and
AARCH32. So some specific mechanism is needed to take care of it.
Signed-off-by: Andrew Pinski
Signed-off-by: Yury Norov
---
arch/ar
From: Philipp Tomsich
ILP32 VDSO exports next symbols:
__kernel_rt_sigreturn;
__kernel_gettimeofday;
__kernel_clock_gettime;
__kernel_clock_getres;
What shared object to use, kernel selects depending on result of
is_ilp32_compat_task() in arch/arm64/kernel/vdso.c, so it substitutes
correct p
to handle ILP32 binaries
Signed-off-by: Yury Norov
---
arch/arm64/include/asm/elf.h | 6 +++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/binfmt_ilp32.c | 96
3 files changed, 103 insertions(+)
create mode 100644 arch/arm64/kernel/binf
After that, it will be possible to reuse it in ilp32.
Signed-off-by: Yury Norov
---
arch/arm64/include/asm/signal_common.h | 33
arch/arm64/kernel/signal.c | 93 +-
2 files changed, 92 insertions(+), 34 deletions(-)
create mode 100644 arc
off_t is passed in register pair just like in aarch32.
In this patch corresponding aarch32 handlers are shared to
ilp32 code.
Signed-off-by: Yury Norov
---
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/entry32.S| 65 --
arch/arm64/kernel/entry32_co
Here new aarch32 ptrace syscall handler is introsuced to avoid run-time
detection of the task type.
Signed-off-by: Yury Norov
---
arch/arm64/include/asm/unistd32.h | 2 +-
arch/arm64/kernel/ptrace.c| 50 ++-
arch/arm64/kernel/sys32.c | 1 +
i
As we support more than one compat formats, it looks more reasonable
to not use fs/compat_binfmt.c. Custom binfmt_elf32.c allows to move aarch32
specific definitions there and make code more maintainable and readable.
Signed-off-by: Yury Norov
---
arch/arm64/Kconfig | 1 -
arch/ar
ILP32 tasks are needed to be distinguished from lp64 and aarch32.
This patch adds helper functions is_ilp32_compat_{task,thread} and
thread flag TIF_32BIT_AARCH64 to address it. This is a preparation
for following patches in ilp32 patchset.
For consistency, SET_PERSONALITY is changed here accordin
Based on patch of Andrew Pinski.
This patch introduces is_a32_compat_task and is_a32_thread so it is
easier to say this is a a32 specific thread or a generic compat thread/task.
Corresponding functions are located in to avoid mess in
headers.
Some files include both and ,
and this is wrong beca
From: Andrew Pinski
The kernel needs to be compiled as a LP64 binary for ARM64, even when
using a compiler that defaults to code-generation for the ILP32 ABI.
Consequently, we need to explicitly pass '-mabi=lp64' (supported on
gcc-4.9 and newer).
Signed-off-by: Andrew Pinski
Signed-off-by: Phil
They may be accessed from low-level code, so isolating is a measure to
avoid circular dependencies in header files.
The exact reason for circular dependency is WARN_ON() macro added by Al
Viro in patch [edd63a27] "set_restore_sigmask() is never called without
SIGPENDING (and never should be)"
Sig
From: Andrew Pinski
Define __BITS_PER_LONG depending on the ABI used (i.e. check whether
__ILP32__ or __LP64__ is defined). This is necessary for glibc to
determine the appropriate type definitions for the system call interface.
Signed-off-by: Andrew Pinski
Signed-off-by: Philipp Tomsich
Sign
All new 32-bit architectures should have 64-bit off_t type, but existing
architectures has 32-bit ones.
To handle it, new config option is added to arch/Kconfig that defaults
ARCH_32BIT_OFF_T to be disabled for non-64 bit architectures. All existing
32-bit architectures enable it explicitly here.
From: Andrew Pinski
In this patchset ILP32 ABI support is added. Additionally to AARCH32,
which is binary-compatible with ARM, ILP32 is (mostly) ABI-compatible.
>From now, AARCH32_EL0 (former COMPAT) config option means the support of
AARCH32 userspace, ARM64_ILP32 - support of ILP32 ABI (see n
This series enables aarch64 with ilp32 mode, and as supporting work,
introduces ARCH_32BIT_OFF_T configuration option that is enabled for
existing 32-bit architectures but disabled for new arches (so 64-bit
off_t is is used by new userspace).
This version is based on kernel v4.7-rc3.
It works with
On Fri, Jun 17, 2016 at 09:53:50AM +0200, Ingo Molnar wrote:
>
> * Paul E. McKenney wrote:
>
> > Nothing in the control-dependencies section of memory-barriers.txt
> > says that control dependencies don't extend beyond the end of the
> > if-statement containing the control dependency. Worse yet
On Fri, 2016-06-17 at 17:00 -0300, Arnaldo Carvalho de Melo wrote:
> Em Fri, Jun 17, 2016 at 12:16:47PM -0400, Daniel Micay escreveu:
> > On Fri, 2016-06-17 at 08:54 +0200, Peter Zijlstra wrote:
> > > This Changelog is completely devoid of information. _WHY_ are you
> > > doing this?
>
> > Attack
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