based (ie ARM) arch configurations.
>
> Signed-off-by: Lorenzo Pieralisi
> Cc: Will Deacon
> Cc: Hanjun Guo
> Cc: Bjorn Helgaas
> Cc: Robin Murphy
> Cc: Tomasz Nowicki
> Cc: Joerg Roedel
> Cc: "Rafael J. Wysocki"
> Cc: Sricharan R
> ---
> Joerg,
&g
rivileged setting to unprivileged, instead
> set it to default as incoming and let it be controlled by the pagetable
> settings.
>
> Signed-off-by: Sricharan R
Acked-by: Will Deacon
I'll let you and Robin sort out what you want to do with this series :)
Will
___
Hi Rob,
On Tue, Dec 06, 2016 at 06:30:21PM -0500, Rob Clark wrote:
> On Thu, Aug 18, 2016 at 9:05 AM, Will Deacon wrote:
> > Enabling stalling faults can result in hardware deadlock on poorly
> > designed systems, particularly those with a PCI root complex upstream
Hi Nate,
Thanks for the patch.
On Mon, Dec 19, 2016 at 03:38:38PM -0500, Nate Watterson wrote:
> To ensure that the stage-1 context ptr for an ste points to the
> intended context descriptor, this patch adds code to clear away
> the stale context ptr value prior to or'ing in the new one.
>
> Sig
Hi Nate,
On Mon, Dec 19, 2016 at 03:26:40PM -0500, Nate Watterson wrote:
> Currently, all l2 stream tables are being allocated with space for
> (1< physically supports. To avoid allocating memory for inaccessible
> stes, this patch limits the span of an l2 table to be no larger
> than the sid size
On Tue, Dec 20, 2016 at 11:52:58AM +, Marc Zyngier wrote:
> On 20/12/16 11:06, Geetha sowjanya wrote:
> > From: Tirumalesh Chalamarla
> > +#ifdef CONFIG_CAVIUM_ERRATUM_28168
> > +/*
> > + * Cavium ThunderX erratum 28168
> > + *
> > + * Due to erratum #28168 PCI-inbound MSI-X store to the inter
On Mon, Dec 19, 2016 at 02:33:36PM +0530, Sricharan wrote:
> >On Tue, Dec 06, 2016 at 06:30:21PM -0500, Rob Clark wrote:
> >> On Thu, Aug 18, 2016 at 9:05 AM, Will Deacon wrote:
> >> > Enabling stalling faults can result in hardware deadlock on poorly
> >> &g
On Tue, Dec 20, 2016 at 09:29:21PM -0600, Rob Herring wrote:
> On Fri, Dec 16, 2016 at 01:19:29PM +, Robin Murphy wrote:
> > The current SMR masking support using a 2-cell iommu-specifier is
> > primarily intended to handle individual masters with large and/or
> > complex Stream ID assignments;
ter/retrieve
> IOMMU instances and remove the of_iommu_{set/get}_ops() remaining glue
> code in order to complete the interface rework.
>
> Signed-off-by: Lorenzo Pieralisi
> Cc: Matthias Brugger
> Cc: Will Deacon
> Cc: Robin Murphy
> Cc: Joerg Roedel
> Cc: Marek Szy
; Signed-off-by: Sricharan R
> ---
> arch/arm/mm/dma-mapping.c | 60
> +++
> 1 file changed, 30 insertions(+), 30 deletions(-)
Reviewed-by: Will Deacon
Russell: do you mind if I take this via the ARM SMMU tree (which goes
through Joerg&#
On Tue, Jan 03, 2017 at 04:30:54PM -0500, Rob Clark wrote:
> TODO maybe we want two options, one to enable stalling, and 2nd to punt
> handling to wq? I haven't needed to use mm APIs from fault handler yet
> (although it is something that I think we'll want some day). Perhaps
> stalling support i
On Thu, Jan 05, 2017 at 12:08:57PM +, Mark Rutland wrote:
> On Thu, Jan 05, 2017 at 11:55:29AM +0000, Will Deacon wrote:
> > On Tue, Jan 03, 2017 at 04:30:54PM -0500, Rob Clark wrote:
> > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> > >
On Thu, Jan 05, 2017 at 02:07:31PM +, Mark Rutland wrote:
> On Thu, Jan 05, 2017 at 02:00:05PM +0000, Will Deacon wrote:
> > On Thu, Jan 05, 2017 at 12:08:57PM +, Mark Rutland wrote:
> > > On Thu, Jan 05, 2017 at 11:55:29AM +, Will Deacon wrote:
> > > >
On Thu, Jan 05, 2017 at 10:27:27AM -0500, Rob Clark wrote:
> On Thu, Jan 5, 2017 at 6:55 AM, Will Deacon wrote:
> > On Tue, Jan 03, 2017 at 04:30:54PM -0500, Rob Clark wrote:
> >> TODO maybe we want two options, one to enable stalling, and 2nd to punt
> >> handling to w
On Thu, Jan 05, 2017 at 03:32:50PM +, Robin Murphy wrote:
> On 05/01/17 14:47, Will Deacon wrote:
> > On Thu, Jan 05, 2017 at 02:07:31PM +, Mark Rutland wrote:
> >> Ok. It would be good to elaborate on what "stalling is useable" means in
> >>
On Thu, Jan 05, 2017 at 05:03:30PM +, Robin Murphy wrote:
> On 05/01/17 16:07, Will Deacon wrote:
> > On Thu, Jan 05, 2017 at 03:32:50PM +, Robin Murphy wrote:
> >> I think this needs to be some kind of "arm,smmu-stall-safe" property
> >> placed on ind
On Tue, Jan 10, 2017 at 03:09:24PM +0100, Joerg Roedel wrote:
> On Mon, Jan 09, 2017 at 01:45:51PM +, Eric Auger wrote:
> > Eric Auger (17):
> > iommu: Rename iommu_dm_regions into iommu_resv_regions
> > iommu: Add a new type field in iommu_resv_region
> > iommu: iommu_alloc_resv_region
>
ers/iommu/arm-smmu.c | 28 ++++
> 1 file changed, 28 insertions(+)
Acked-by: Will Deacon
Will
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ll allow to report those info in iommu-group
> sysfs.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v4: creation
> ---
> drivers/iommu/arm-smmu-v3.c | 28
> 1 file changed, 28 insertions(+)
Acked-by: Will Deacon
Will
__
s MSI remapping capability at MSI controller
> level, let's correct this.
>
> Signed-off-by: Eric Auger
> ---
> drivers/iommu/arm-smmu-v3.c | 2 --
> drivers/iommu/arm-smmu.c| 2 --
> 2 files changed, 4 deletions(-)
Dependent on the previous two VF
Hi Rob,
On Fri, Jan 06, 2017 at 11:26:49AM -0500, Rob Clark wrote:
> On Thu, Jan 5, 2017 at 10:49 AM, Will Deacon wrote:
> > On Thu, Jan 05, 2017 at 10:27:27AM -0500, Rob Clark wrote:
> >> I'm not sure if the better solution then would be to have two fault
> >>
On Tue, Jan 10, 2017 at 02:20:13PM -0500, Rob Clark wrote:
> On Tue, Jan 10, 2017 at 12:52 PM, Will Deacon wrote:
> > On Fri, Jan 06, 2017 at 11:26:49AM -0500, Rob Clark wrote:
> >> Hmm, well we install the fault handler on the iommu_domain.. perhaps
> >> maybe
On Wed, Jan 11, 2017 at 03:59:30PM -0500, Rob Clark wrote:
> On Wed, Jan 11, 2017 at 4:36 AM, Will Deacon wrote:
> > On Tue, Jan 10, 2017 at 02:20:13PM -0500, Rob Clark wrote:
> >> On Tue, Jan 10, 2017 at 12:52 PM, Will Deacon wrote:
> >> > On Fri, Jan 06, 2017
On Tue, Jan 10, 2017 at 02:47:13PM -0500, Nate Watterson wrote:
> In the current arm-smmu-v3 driver, all smmus that support 2-level
> stream tables are being forced to use them. This is suboptimal for
> smmus that support fewer stream id bits than would fill in a single
> second level table. This p
On Thu, Jan 19, 2017 at 05:36:36PM +0300, Aleksey Makarov wrote:
> It is the time we have the real 16-bit Stream ID user, which is the
> ThunderX. Its IO topology uses 1:1 map for Requester ID to Stream ID
> translation for each root complex which allows to get full 16-bit
> Stream ID. Firmware as
On Mon, Jan 16, 2017 at 08:16:07AM +0100, Tomasz Nowicki wrote:
> The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs
> are unique across all SMMU instances on affected Cavium systems.
>
> Currently, the workaround code partitions ASIDs and VMIDs by increasing
> global cavi
d on top of ACPI IORT SMMU series]
> Signed-off-by: Sricharan R
> ---
> * No change
>
> drivers/iommu/arm-smmu-v3.c | 46 ++-
> drivers/iommu/arm-smmu.c| 58
> +++--
> 2 files changed, 10 i
not
> required. So removing the notifier's here.
>
> Signed-off-by: Sricharan R
> [rm: clean up even more]
> Signed-off-by: Robin Murphy
> ---
> * No change
>
> arch/arm64/mm/dma-mapping.c | 132
>
> 1 file ch
thing other
than DMA.
This patch series implements a command-line option to configure the
default domain type. Currently, it supports "dma" and "identity" which
is sufficient for the passthrough use-case.
Tested on an ARM fastmodel.
All feedback welcome,
Will
--->8
Will
h
the SMMU without any translation.
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a328ffb75509..0f5e42a719e5 100644
--- a/drivers/iommu/
27;re not in control of the underlying address space. This patch leaves
the DMA ops alone for masters attached to non-DMA IOMMU domains.
Signed-off-by: Will Deacon
---
arch/arm64/mm/dma-mapping.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/m
ow through
the SMMU without any translation.
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index c254325b0c7a..d33291274455 100644
--- a/drivers
-ENODEV if the domain_{get,set}_attr operations are
called on other domain types.
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 6 ++
drivers/iommu/arm-smmu.c| 6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
using "iommu.default_domain=identity" on the kernel command
line.
Signed-off-by: Will Deacon
---
drivers/iommu/iommu.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index dbe7f653bb7c..69f7f1a75
; Signed-off-by: Eric Auger
> Reviewed-by: Tomasz Nowicki
> Tested-by: Tomasz Nowicki
> Tested-by: Bharat Bhushan
>
> ---
I acked this before:
Acked-by: Will Deacon
Will
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[adding David Woodhouse, since he maintains this driver]
Will
On Thu, Jan 19, 2017 at 08:57:53PM +, Eric Auger wrote:
> This patch registers the [FEE0_h - FEF0_000h] 1MB MSI
> range as a reserved region and RMRR regions as direct regions.
>
> This will allow to report those reserved regi
ions(-)
Looks good to me, and has the added benefit of getting PCI ethernet
working on Juno when using the SMMU. Unintended side-effect, but:
Acked-by: Will Deacon
Will
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plies on top of Eric's MSI series, since
> that seems ready to go now - there is a trivial merge conflict otherwise
> around the extra argument in the __alloc_iova() call.
>
> Robin.
>
> drivers/iommu/dma-iommu.c | 23 ++-
> 1 file changed, 18 i
On Thu, Jan 26, 2017 at 06:15:55PM +0100, Joerg Roedel wrote:
> On Thu, Jan 19, 2017 at 06:19:15PM +0000, Will Deacon wrote:
> > Rather than modify each IOMMU driver to provide different semantics for
> > DMA domains, instead we introduce a command line parameter that can be
> &g
On Thu, Jan 26, 2017 at 06:03:30PM +0100, Joerg Roedel wrote:
> On Thu, Jan 19, 2017 at 06:19:11PM +0000, Will Deacon wrote:
> > The ARM SMMU drivers provide a DOMAIN_ATTR_NESTING domain attribute,
> > which allows callers of the IOMMU API to request that the page table
>
On Thu, Jan 19, 2017 at 07:00:25PM +, Robin Murphy wrote:
> On 19/01/17 18:19, Will Deacon wrote:
> > The arm64 DMA-mapping implementation sets the DMA ops to the IOMMU DMA
> > ops if we detect that an IOMMU is present for the master and the DMA
> > ranges are valid.
>
Hi Joerg,
Please pull these arm-smmu updates for 4.11. Not much this time around:
16-bit SID support on SMMUv2 and a stream table optimisation on SMMUv3.
There's also a trivial cleanup to of_iommu_{set/get}_ops() [they are
removed] which we promised to make after the IORT stuff went in last
time a
Hi Joerg,
Please pull the following IOMMU changes for 4.11. These patches from
Sricharan add support for "privileged" IOMMU mappings, which are useful
with master devices that support transactions at different privilege
levels and want to control the permissions independently.
Cheers,
Will
--->
Hi Joerg,
Please pull Eric's guest-MSI series for 4.11. This has been through
considerable review and associated rework (including a session at LPC),
but it has stabilised at last and we all seem to be happy with it. Eric's
done a great job of respinning these and remaining patient while we
pulled
On Mon, Jan 30, 2017 at 09:33:50AM -0500, Sinan Kaya wrote:
> On 1/30/2017 9:23 AM, Nate Watterson wrote:
> > On 2017-01-30 08:59, Sinan Kaya wrote:
> >> On 1/30/2017 7:22 AM, Robin Murphy wrote:
> >>> On 29/01/17 17:53, Sinan Kaya wrote:
> On 1/24/2017 7:37 AM, Lorenzo Pieralisi wrote:
>
On Thu, Feb 02, 2017 at 10:02:50AM -0500, Rob Clark wrote:
> On Thu, Jan 26, 2017 at 12:18 PM, Joerg Roedel wrote:
> > On Tue, Jan 24, 2017 at 08:42:23PM +0530, Sricharan wrote:
> >> Thanks for this series. We had a case with the GPU.
> >> The GPU's iommu was setup by kernel and the GPU
> >> also
On Thu, Feb 02, 2017 at 09:15:19PM +0530, Sricharan wrote:
> Hi Rob,
>
> >-Original Message-
> >From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org]
> >On Behalf Of Rob Clark
> >Sent: Thursday, February 02, 2017 8:33 PM
> >
On Mon, Feb 13, 2017 at 01:07:02PM +0200, Oleksandr Tyshchenko wrote:
> Any comments?
Looks fine to me, but I don't think it's urgent and I already sent my
SMMU pull for 4.11. I'll send this as a fix after the merge window.
I suspect we need something similar for io-pgtable-arm-v7s.c, too.
Will
On Mon, Feb 13, 2017 at 01:50:29PM +0200, Oleksandr Tyshchenko wrote:
> On Mon, Feb 13, 2017 at 1:27 PM, Will Deacon wrote:
> > On Mon, Feb 13, 2017 at 01:07:02PM +0200, Oleksandr Tyshchenko wrote:
> >> Any comments?
> >
> > Looks fine to me, but I don't thin
On Mon, Feb 13, 2017 at 08:54:04PM -0500, Sinan Kaya wrote:
> On 2/13/2017 8:46 PM, Alex Williamson wrote:
> >> My first goal is to support virtual function passthrough for device's that
> >> are directly
> >> connected. This will be possible with the quirk I proposed and it will be
> >> the most
On Tue, Feb 21, 2017 at 03:31:26PM +0200, Oleksandr Tyshchenko wrote:
> On Tue, Feb 21, 2017 at 2:00 PM, Robin Murphy wrote:
> > Would it not be more logical (and simpler) to just check that the thing
> > we dereference is valid to dereference when we dereference it? i.e.:
> >
> > -8<-
> >
ow through
the SMMU without any translation.
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 58 +
1 file changed, 37 insertions(+), 21 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index e1
ly
of the disable_bypass parameter.
All feedback welcome,
Will
--->8
Will Deacon (5):
iommu/arm-smmu: Restrict domain attributes to UNMANAGED domains
iommu/arm-smmu: Install bypass S2CRs for IOMMU_DOMAIN_IDENTITY domains
iommu/arm-smmu-v3: Make arm_smmu_install_ste_for_dev return void
avoid, to make it explicit that it cannot fail.
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 3d38e682071a..e18dbcd26f66 100644
--- a/drivers
using "iommu.passthrough=1" on the kernel command line.
Signed-off-by: Will Deacon
---
Documentation/admin-guide/kernel-parameters.txt | 6 ++
drivers/iommu/iommu.c | 17 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/Doc
-ENODEV if the domain_{get,set}_attr operations are
called on other domain types.
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu-v3.c | 6 ++
drivers/iommu/arm-smmu.c| 6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
h
the SMMU without any translation.
Reviewed-by: Robin Murphy
Signed-off-by: Will Deacon
---
drivers/iommu/arm-smmu.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 6426819348be..04530e968132 10
Hi Joerg,
On Tue, Mar 21, 2017 at 04:46:24PM +0100, Joerg Roedel wrote:
> On Fri, Mar 10, 2017 at 08:49:31PM +0000, Will Deacon wrote:
> > Will Deacon (5):
> > iommu/arm-smmu: Restrict domain attributes to UNMANAGED domains
> > iommu/arm-smmu: Install bypass S2CRs for
Hi Robin,
On Thu, Mar 16, 2017 at 06:19:48PM +, Robin Murphy wrote:
> On 16/03/17 16:24, Nate Watterson wrote:
> > On 2017-03-10 15:49, Will Deacon wrote:
> >> In preparation for allowing the default domain type to be overridden,
> >> this patch adds support for IO
On Tue, Mar 21, 2017 at 04:45:27PM +0100, Joerg Roedel wrote:
> On Fri, Mar 10, 2017 at 08:49:36PM +0000, Will Deacon wrote:
> > @@ -1014,8 +1027,8 @@ struct iommu_group *iommu_group_get_for_dev(struct
> > device *dev)
> > * IOMMU driver.
> > */
> &g
On Tue, Mar 21, 2017 at 05:46:29PM +, Robin Murphy wrote:
> On 21/03/17 17:21, Will Deacon wrote:
> > On Tue, Mar 21, 2017 at 04:45:27PM +0100, Joerg Roedel wrote:
> >> On Fri, Mar 10, 2017 at 08:49:36PM +, Will Deacon wrote:
> >>> @@ -1014,8
Hi Joerg,
Please pull these two ARM io-pgtable fixes from Oleksandr for 4.11. They're
not critical, but they mean that we detect misuses in the iommu_{map,unmap}
API instead of deferencing junk pointers in the kernel. I've had them queued
locally for a while, so Robin and I have given them a fair
Hi Robin,
On Tue, Mar 07, 2017 at 06:09:04PM +, Robin Murphy wrote:
> We currently warn if the firmware-described region size differs from the
> SMMU address space size reported by the hardware, but continue to use
> the former to calculate where our context bank base should be,
> effectively
Hi Robin,
This mostly looks great, but I have a couple of minor comments below.
On Tue, Mar 07, 2017 at 06:09:07PM +, Robin Murphy wrote:
> TLB synchronisation typically involves the SMMU blocking all incoming
> transactions until the TLBs report completion of all outstanding
> operations. In
On Thu, Mar 23, 2017 at 05:59:40PM +, Robin Murphy wrote:
> On relatively slow development platforms and software models, the
> inefficiency of our TLB sync loop tends not to show up - for instance on
> a Juno r1 board I typically see the TLBI has completed of its own accord
> by the time we ge
On Tue, Mar 07, 2017 at 06:09:03PM +, Robin Murphy wrote:
> The discussion around context-level access for Qualcomm SMMUs reminded
> me to dig up this patch I started ages ago and finish it off. As it's
> ended up, it's now a mini-series, with some new preparatory cleanup
> manifesting as patch
On Thu, Mar 30, 2017 at 05:56:28PM +0100, Robin Murphy wrote:
> Here's a quick v2 to address your comments and drop the needless meddling
> (whaddaya know, it makes the whole lot look simpler!)
>
> I'll put it on my list to take a look at SMMUv3 queue polling as suggested.
Thanks, I've queued thi
Hi Robin, Joerg,
On Wed, Mar 15, 2017 at 01:33:13PM +, Robin Murphy wrote:
> Here's the first bit of lock contention removal to chew on - feedback
> welcome! Note that for the current users of the io-pgtable framework,
> this is most likely to simply push more contention onto the io-pgtable
>
On Thu, Mar 09, 2017 at 09:05:43PM +0530, Sricharan R wrote:
> This series provides the support for turning on the arm-smmu's
> clocks/power domains using runtime pm. This is done using the
> recently introduced device links patches, which lets the symmu's
> runtime to follow the master's runtime p
On Fri, Mar 31, 2017 at 10:58:16PM -0400, Rob Clark wrote:
> On Fri, Mar 31, 2017 at 1:54 PM, Will Deacon wrote:
> > On Thu, Mar 09, 2017 at 09:05:43PM +0530, Sricharan R wrote:
> >> This series provides the support for turning on the arm-smmu's
> >> clocks/power d
On Mon, Apr 03, 2017 at 11:16:33PM +0530, Sunil Kovvuri wrote:
> On Tue, Mar 28, 2017 at 4:11 PM, wrote:
> > From: Sunil Goutham
> >
> > 16bit ASID should be enabled before initializing TTBR0/1,
> > otherwise only LSB 8bit ASID will be considered. Hence
> > moving configuration of TTBCR register
Add global SMR masking property
iommu/io-pgtable-arm: Avoid shift overflow in block size
Sunil Goutham (1):
iommu/arm-smmu: Fix 16-bit ASID configuration
Will Deacon (5):
iommu/arm-smmu: Restrict domain attributes to UNMANAGED domains
iommu/arm-smmu: Install bypass S2CRs
On Tue, Apr 11, 2017 at 04:54:26PM +0100, Robin Murphy wrote:
> On 11/04/17 15:42, linucher...@gmail.com wrote:
> > From: Geetha
> >
> > Cavium 99xx SMMU implementation doesn't not support unique irq lines for
> > gerror, eventq and cmdq-sync. USE_SHARED_IRQS option enables to use single
> > irq
On Tue, Apr 11, 2017 at 08:12:38PM +0530, linucher...@gmail.com wrote:
> From: Linu Cherian
>
> Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
> 1. Errata ID #74
>SMMU register alias Page 1 is not implemented
> 2. Errata ID #126
>SMMU doesnt support unique IRQ lines for gerr
On Tue, Apr 11, 2017 at 05:38:21PM +0100, Robin Murphy wrote:
> On 11/04/17 17:21, Will Deacon wrote:
> > On Tue, Apr 11, 2017 at 04:54:26PM +0100, Robin Murphy wrote:
> >> On 11/04/17 15:42, linucher...@gmail.com wrote:
> >>> From: Geetha
> >>>
> &g
On Mon, Apr 17, 2017 at 05:27:26PM +0530, sunil.kovv...@gmail.com wrote:
> From: Sunil Goutham
>
> For software initiated address translation, when domain type is
> IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior
> i.e return the same IOVA as translated address.
>
> This patch is a
On Fri, Apr 21, 2017 at 05:03:36PM +0800, Peng Fan wrote:
> From code "SMR mask 0x%x out of range for SMMU",
> so, we need to use mask, not sid.
>
> Signed-off-by: Peng Fan
> Cc: Will Deacon
> Cc: Robin Murphy
> ---
> drivers/iommu/arm-smmu.c | 2 +-
&g
On Mon, Apr 24, 2017 at 09:23:16PM +0530, Sunil Kovvuri wrote:
> On Mon, Apr 24, 2017 at 8:14 PM, Will Deacon wrote:
> > On Mon, Apr 17, 2017 at 05:27:26PM +0530, sunil.kovv...@gmail.com wrote:
> >> From: Sunil Goutham
> >>
> >> For software initiated addr
On Mon, Apr 24, 2017 at 05:29:36PM +0530, Geetha sowjanya wrote:
> From: Geetha
>
> When large memory is being unmapped, huge no of tlb invalidation cmds are
> submitted followed by a SYNC command. This sometimes hits CMD queue full and
> poll on queue drain is being timedout throwing error messa
On Mon, Apr 24, 2017 at 10:26:53PM +0530, Sunil Kovvuri wrote:
> On Mon, Apr 24, 2017 at 9:38 PM, Will Deacon wrote:
> > On Mon, Apr 24, 2017 at 05:29:36PM +0530, Geetha sowjanya wrote:
> >> From: Geetha
> >>
> >> When large memory is being unmapped,
On Wed, Apr 26, 2017 at 02:50:04PM +0530, Sunil Kovvuri wrote:
> On Mon, Apr 24, 2017 at 10:35 PM, Will Deacon wrote:
> > On Mon, Apr 24, 2017 at 10:26:53PM +0530, Sunil Kovvuri wrote:
> >> On Mon, Apr 24, 2017 at 9:38 PM, Will Deacon wrote:
> >> > On Mon, Ap
nslated address.
>
> This patch is an extension to Will Deacon's patchset
> "Implement SMMU passthrough using the default domain".
>
> Signed-off-by: Sunil Goutham
> ---
>
> V2
> - As per Will's suggestion applied fix to SMMUv3 driver as well.
This follow
On Wed, Apr 26, 2017 at 04:13:29PM +0530, Sunil Kovvuri wrote:
> On Wed, Apr 26, 2017 at 3:31 PM, Will Deacon wrote:
> > Hi Sunil,
> >
> > On Tue, Apr 25, 2017 at 03:27:52PM +0530, sunil.kovv...@gmail.com wrote:
> >> From: Sunil Goutham
> >>
> >>
On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> > + /*
> > +* Override the size, for Cavium CN99xx implementations
> > +* which doesn't support the page 1 SMMU register space.
> > +*/
> > + cpu_model
Hi Ard,
[+ devicetree@]
On Fri, Apr 14, 2017 at 01:43:15PM +0100, Ard Biesheuvel wrote:
> DT nodes may have a status property, and if they do, such nodes should
> only be considered present if the status property is set to 'okay'.
>
> Currently, we call the init function of IOMMUs described by t
On Fri, Apr 28, 2017 at 02:14:49PM +0100, Ard Biesheuvel wrote:
> On 28 April 2017 at 14:11, Will Deacon wrote:
> > Hi Ard,
> >
> > [+ devicetree@]
> >
> > On Fri, Apr 14, 2017 at 01:43:15PM +0100, Ard Biesheuvel wrote:
> >> DT nodes may have a status p
Hi Geetha,
On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
Urgh, that's unfortunate. In what way is it broken?
> If using MIDR is not accepted, can we enable errata based on SMMU resource
> size?
> some thin
On Wed, May 03, 2017 at 06:49:09PM +0530, Sunil Kovvuri wrote:
> On Thu, Apr 27, 2017 at 4:43 PM, wrote:
> > From: Sunil Goutham
> >
> > Modified polling on CMDQ consumer similar to how polling is done for TLB
> > SYNC
> > completion in SMMUv2 driver. Code changes are done with reference to
> >
On Wed, May 03, 2017 at 04:33:57PM +0100, Robin Murphy wrote:
> On 27/04/17 12:13, sunil.kovv...@gmail.com wrote:
> > From: Sunil Goutham
> >
> > Modified polling on CMDQ consumer similar to how polling is done for TLB
> > SYNC
> > completion in SMMUv2 driver. Code changes are done with referenc
On Wed, May 03, 2017 at 09:24:13PM +0530, Sunil Kovvuri wrote:
> On Wed, May 3, 2017 at 9:07 PM, Will Deacon wrote:
> > On Wed, May 03, 2017 at 06:49:09PM +0530, Sunil Kovvuri wrote:
> >> On Thu, Apr 27, 2017 at 4:43 PM, wrote:
> >> > From: Sunil Goutham
> >
On Fri, May 05, 2017 at 07:56:17AM -0700, David Daney wrote:
> On 05/05/2017 06:53 AM, Hanjun Guo wrote:
> >On 2017/5/5 20:08, Geetha sowjanya wrote:
> >>From: Linu Cherian
> >>
> >>Add SMMUv3 model definition for ThunderX2.
> >>
> >>Signed-off-by: Linu Cherian
> >>Signed-off-by: Geetha Sowjanya
On Thu, May 11, 2017 at 02:26:02AM +0200, Rafael J. Wysocki wrote:
> On Wednesday, May 10, 2017 05:01:55 PM Geetha sowjanya wrote:
> > From: Linu Cherian
> >
> > Add SMMUv3 model definition for ThunderX2.
> >
> > Signed-off-by: Linu Cherian
> > Signed-off-by: Geetha Sowjanya
>
> This is an AC
On Thu, May 11, 2017 at 04:40:51PM +0200, Rafael J. Wysocki wrote:
> On Thursday, May 11, 2017 09:45:25 AM Will Deacon wrote:
> > On Thu, May 11, 2017 at 02:26:02AM +0200, Rafael J. Wysocki wrote:
> > > On Wednesday, May 10, 2017 05:01:55 PM Geetha sowjanya wrote:
> >
ool of_iommu_driver_present(struct device_node
> *np)
>
> ops = iommu_ops_from_fwnode(fwnode);
> if ((ops && !ops->of_xlate) ||
> + !of_device_is_available(iommu_spec->np) ||
> (!ops && !of_iommu_driver_present(iommu_
Hi Sunil,
On Mon, May 29, 2017 at 02:41:59PM +0530, Sunil Kovvuri wrote:
> On Fri, May 5, 2017 at 4:47 PM, wrote:
> > From: Sunil Goutham
> >
> > Processing queue full of TLB invalidation commands might
> > take more time on some platforms than current timeout
> > of 100us. So increased drain t
On Mon, May 29, 2017 at 06:18:45PM -0700, Ray Jui wrote:
> I'm writing to check with you to see if the latest arm-smmu.c driver in
> v4.12-rc Linux for smmu-500 can support mapping that is only specific to
> a particular physical address range while leave the rest still to be
> handled by the clien
On Tue, May 30, 2017 at 11:13:36PM -0700, Ray Jui wrote:
> I did a little more digging myself and I think I now understand what you
> meant by identity mapping, i.e., configuring the MMU-500 with 1:1 mapping
> between the DMA address and the IOVA address.
>
> I think that should work. In the end,
Hi Geetha,
On Tue, May 30, 2017 at 05:33:41PM +0530, Geetha sowjanya wrote:
> From: Geetha Sowjanya
>
> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
> lines for gerror, eventq and cmdq-sync.
>
> This patch addresses the issue by checking if any interrupt sources ar
On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote:
> From: Geetha Sowjanya
>
> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
> lines for gerror, eventq and cmdq-sync.
>
> SHARED_IRQ option is set as a errata workaround, which allows to share the irq
> l
On Tue, Jun 20, 2017 at 07:47:37PM +0530, Geetha sowjanya wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 implementation doesn't support second page in SMMU
> register space. Hence, resource size is set as 64k for this model.
>
> Signed-off-by: Linu Cherian
> Signed-off-by: Geetha Sowjanya
>
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