On Tue, Apr 11, 2017 at 08:12:38PM +0530, linucher...@gmail.com wrote: > From: Linu Cherian <linu.cher...@cavium.com> > > Cavium CN99xx SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 > SMMU register alias Page 1 is not implemented > 2. Errata ID #126 > SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync
Is this device in production, or just part of a test chip? Will _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
