On Mon, Jan 16, 2017 at 08:16:07AM +0100, Tomasz Nowicki wrote: > The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs > are unique across all SMMU instances on affected Cavium systems. > > Currently, the workaround code partitions ASIDs and VMIDs by increasing > global cavium_smmu_context_count which in turn becomes the base ASID and VMID > value for the given SMMU instance upon the context bank initialization. > > For systems with multiple SMMU instances this approach implies the risk > of crossing 8-bit ASID, like for 1-socket CN88xx capable of 4 SMMUv2, > 128 context banks each: > SMMU_0 (0-127 ASID RANGE) > SMMU_1 (127-255 ASID RANGE) > SMMU_2 (256-383 ASID RANGE) <--- crossing 8-bit ASID > SMMU_3 (384-511 ASID RANGE) <--- crossing 8-bit ASID > > Since now we use 8-bit ASID (SMMU_CBn_TCR2.AS = 0) we effectively misconfigure > ASID[15:8] bits of SMMU_CBn_TTBRm register for SMMU_2/3. Moreover, we still > assume non-zero ASID[15:8] bits upon context invalidation. In the end, > except SMMU_0/1 devices all other devices under other SMMUs will fail on guest > power off/on. Since we try to invalidate TLB with 16-bit ASID but we actually > have 8-bit zero padded 16-bit entry. > > This patch adds 16-bit ASID support for stage-1 AArch64 contexts so that > we use ASIDs consistently for all SMMU instances. > > Signed-off-by: Tomasz Nowicki <t...@semihalf.com> > Reviewed-by: Robin Murphy <robin.mur...@arm.com> > Reviewed-by: Tirumalesh Chalamarla <tirumalesh.chalama...@cavium.com> > --- > drivers/iommu/arm-smmu.c | 3 +++ > 1 file changed, 3 insertions(+)
Thanks, queued for 4.11. Will _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
