Re: [Intel-gfx] [PATCH v4 1/4] drm/crtc: Add property for aspect ratio

On Jul-15-2014 12:18 PM, Daniel Vetter wrote: [...] > > I've pulled all 4 patches. Please double-check that I've picked up the > right ones since the series is a bit spread out. > > Thanks, Daniel > Hi Daniel, I checked the 4 patches in -next-queued. They are the correct version. Thanks, Vanda

[Intel-gfx] [PATCH 1/2] drm/i915: Get CZ clock for VLV

CZ clock is related to data flow from memory to display plane. This is required for comparison with CD clock before programming PFI credits. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/2] drm/i915: Program PFI credits for VLV

lower log level instead of DRM_ERROR - Change function name to valleyview_program_pfi_credits - Move program PFI credits to modeset_init instead of intel_set_mode - Change magic numbers to logical constants Signed-off-by: Vidya Srinivas Signed-off-by: Gajanan Bhat Signed-off-by: V

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Get CZ clock for VLV

On Aug-05-2014 6:39 PM, Ville Syrjälä wrote: > On Mon, Aug 04, 2014 at 10:44:04PM +0530, Vandana Kannan wrote: >> CZ clock is related to data flow from memory to display plane. This is >> required for comparison with CD clock before programming PFI credits. >> >> Si

[Intel-gfx] [PATCH v2 2/3] drm/i915: Get CZ clock for VLV

CZ clock is related to data flow from memory to display plane. This is required for comparison with CD clock before programming PFI credits. v2: Ville's review comments - Re-ordered CCK_CZ_CONTROL - Refactored get_clock_speed Signed-off-by: Vandana Kannan --- drivers/gp

[Intel-gfx] [PATCH 1/3] drm/i915: Renaming CCK related reg definitions

Rename the DISPLAY_TRUNK_* and DISPLAY_FREQUENCY_* bits to CCK_... instead of DISPLAY_... to make it clear they apply to all CCK clock control registers. Suggested by Ville. Signed-off-by: Vandana Kannan Cc: Ville Syrjä --- drivers/gpu/drm/i915/i915_reg.h | 10 +- drivers/gpu/drm

[Intel-gfx] [PATCH 3/3] drm/i915: Program PFI credits for VLV

lower log level instead of DRM_ERROR - Change function name to valleyview_program_pfi_credits - Move program PFI credits to modeset_init instead of intel_set_mode - Change magic numbers to logical constants Signed-off-by: Vidya Srinivas Signed-off-by: Gajanan Bhat Signed-off-by: V

[Intel-gfx] [PATCH] drm/i915: Idleness detection for DRRS

PSR is enable/disabled. v11: Moved DRRS not supported log to patch2. Patch rebased. Signed-off-by: Vandana Kannan Signed-off-by: Pradeep Bhat Reviewed-by: Jani Nikula Cc: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 7 ++ drivers/gpu/drm/i915/i915_params.c | 8 ++ drivers/gpu

[Intel-gfx] [PATCH v4] drm/i915/bxt: eDP Panel Power sequencing

l() is not required for BXT - correct the use of && in the print statement - drop the shift in the print statement v4: Jani's comments - modify ironlake_get_pp_control() - dont set unlock key for bxt Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil

[Intel-gfx] [PATCH v5] drm/i915/bxt: eDP Panel Power sequencing

t - move pp_ctrl_reg write (after ironlake_get_pp_control()) to !IS_BROXTON case. - check before subtracting 1 for t11_t12 Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamath --- drivers/gpu/drm/i915/i915_reg.h | 13 +++ drivers/

[Intel-gfx] [PATCH] drm/i915/bxt: Calculate port clock

bxt_calc_pll_link() has been returning 0 all this while. This patch adds calculation in bxt_calc_pll_link() based on the chv calculation used in bxt_find_best_dpll(). Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ddi.c | 38

[Intel-gfx] [PATCH] drm/i915/bxt: BUNs related to port PLL

This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_ddi.c | 7 +++ drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH v2] drm/i915/bxt: BUNs related to port PLL

, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_ddi.c | 16 ++-- drivers/gpu/drm/i915/intel_display.c | 2 +- 2 files chang

[Intel-gfx] [PATCH v3] drm/i915/bxt: BUNs related to port PLL

, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment v3: Move DCO amplitude default value to i915_reg.h. Suggested by Siva. Signed-off-by: Vandana Kannan Reviewed-by: Sonika Jindal [v2] --- drivers/gpu/drm

[Intel-gfx] [PATCH] drm/i915: Parsing LFP brightness control from VBT

VBT (version >= 191) From VBT version >= 197, default value of control pin is set to DDI, so the corresponding check during backlight setup will be made in a future patch Signed-off-by: Deepak M Signed-off-by: Vandana Kannan Cc: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [RFC] drm/i915: Render decompression support for Gen9 and above

sable stereo 3D when render decomp is enabled (bit 7:6) 2. Render decompression must not be used in VTd pass-through mode 3. Program hashing select CHICKEN_MISC1 bit 15 4. For Gen10, add support for RGB 1010102 Signed-off-by: Vandana Kannan --- drivers/gpu/drm/drm_atomic.c | 4 + drivers/gp

[Intel-gfx] [PATCH 2/3] drm/i915: eDP Panel Power sequencing PP_DIV register changes

BXT does not have PP_DIV register. Making changes to handle this. Signed-off-by: Vandana Kannan Signed-off-by: Kumar, Mahesh --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/i915_suspend.c | 8 -- drivers/gpu/drm/i915/intel_dp.c | 56

[Intel-gfx] [PATCH 3/3] drm/i915: eDP Panel Power sequencing add PPS reg set

Second set of PPS registers have been defined but will be used when VBT provides a selection between the 2 sets of registers. Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamath --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu

[Intel-gfx] [PATCH 1/3] drm/i915: eDP Panel Power sequencing modify use of HAS_PCH_SPLIT

Changes based on future platform readiness patches related to HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamath --- drivers/gpu/drm/i915/i915_suspend.c | 4 ++-- drivers/gpu/drm/i915/intel_dp.c | 8 2 files

[Intel-gfx] [PATCH] drm/i915: eDP Panel Power sequencing

2 sets of registers. v2: [Jani] Added 2nd set of PPS registers and the macro Jani's review comments - remove reference in i915_suspend.c - Use BXT PP macro Squashing all PPS related patches into one. Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamath --- driver

[Intel-gfx] [PATCH] drm/i915/bxt: Port PLL programming BUN

PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK - Calculate for HDMI - Correct values for vco = 5.4 - return in case of invalid vco range Signed-off-by: Vandana Kannan Cc: Sivakumar Thulasimani --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6

[Intel-gfx] [PATCH] drm/i915/bxt: BLC implementation

Jani Nikula Signed-off-by: Vandana Kannan Signed-off-by: Damien Lespiau Cc: Jani Nikula Cc: Shankar, Uma --- drivers/gpu/drm/i915/i915_reg.h| 12 ++ drivers/gpu/drm/i915/intel_panel.c | 87 +- 2 files changed, 98 insertions(+), 1 deletion(-) diff --

[Intel-gfx] [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation

Making lane stagger calculation common for HDMI and DP Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_ddi.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 49b9fd8

[Intel-gfx] [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN

EN to PORT_PLL_DCO_AMP_OVR_EN_H - Correct lane stagger value for 324MHz - Make coef common for HDMI and DP - remove superfluous comments Signed-off-by: Vandana Kannan Reviewed-by: Sivakumar Thulasimani Cc: Sivakumar Thulasimani --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm

[Intel-gfx] [PATCH v3] drm/i915/bxt: eDP Panel Power sequencing

l() is not required for BXT - correct the use of && in the print statement - drop the shift in the print statement Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamath --- drivers/gpu/drm/i915/i915_reg.h | 13 drivers/gpu/drm/i9

[Intel-gfx] [PATCH v3 1/2] drm/i915/bxt: Port PLL programming BUN

make them local variables. Signed-off-by: Vandana Kannan Reviewed-by: Sivakumar Thulasimani [v1] Cc: Sivakumar Thulasimani --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6 +++ drivers/gpu/drm/i915/intel_ddi.c | 79 ---

[Intel-gfx] [PATCH v2 2/2] drm/i915/bxt: Move around lane stagger calculation

Making lane stagger calculation common for HDMI and DP v2: Imre's comments addressed - Remove lane stagger from bxt_clk_div and make it a local variable in ddi_pll_select Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_ddi.c

[Intel-gfx] [PATCH v4] drm/i915/bxt: eDP Panel Power sequencing

l() is not required for BXT - correct the use of && in the print statement - drop the shift in the print statement v4: Jani's comments - modify ironlake_get_pp_control() - dont set unlock key for bxt Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamat

[Intel-gfx] [PATCH v2 0/8] eDP DRRS based on frontbuffer tracking

st in libdrm.. But i-g-t for DRRS is WIP. Durgadoss R (1): drm/i915: Enable eDP DRRS for CHV Vandana Kannan (7): drm/i915: Modifying structures related to DRRS drm/i915: Initialize DRRS delayed work drm/i915: Enable/disable DRRS drm/i915: DRRS calls based on frontbuffer drm/i915/bdw

[Intel-gfx] [PATCH 1/7] drm/i915: Modifying structures related to DRRS

, aligning with frontbuffer tracking mechanism, the new structure contains data for busy frontbuffer bits. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 32 ++--- drivers/gpu/drm/i915/intel_dp.c | 50 ++-- drivers/gpu/drm

[Intel-gfx] [PATCH 3/7] drm/i915: Enable/disable DRRS

functions, to make sure the functions go through only if DRRS will work on the platform with the attached panel. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 54 drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 4/7] drm/i915: DRRS calls based on frontbuffer

calls. The call to fb_obj_invalidate (in flip) is placed before queuing flip for this obj. drrs_invalidate() and drrs_flush() check for drrs.dp which would be NULL if it was setup in drrs_enable(). This covers for the condition when DRRS is not supported. Signed-off-by: Vandana Kannan --- drivers

[Intel-gfx] [PATCH 2/7] drm/i915: Initialize DRRS delayed work

Add DRRS work function to trigger a switch to low refresh rate when activity is detected on screen. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 36 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 6/7] drm/i915: Support for RR switching on VLV

Definition of VLV RR switch bit and corresponding toggling in set_drrs function. Signed-off-by: Vandana Kannan Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 10 -- 2 files changed, 9 insertions(+), 2

[Intel-gfx] [PATCH 7/7] drm/i915: Enable eDP DRRS for CHV

s R Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- drivers/gpu/drm/i915/intel_dp.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0239681..06bfbbb 100

[Intel-gfx] [PATCH 5/7] drm/i915/bdw: Add support for DRRS to switch RR

next frame that is output. Signed-off-by: Vandana Kannan Signed-off-by: Pradeep Bhat --- drivers/gpu/drm/i915/intel_display.c | 9 +++-- drivers/gpu/drm/i915/intel_dp.c | 15 ++- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 20 insertions(+), 7 deletions(-)

[Intel-gfx] [PATCH 2/10] drm/i915: Initialize DRRS delayed work

Add DRRS work function to trigger a switch to low refresh rate when activity is detected on screen. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 36 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/10] drm/i915: Modifying structures related to DRRS

, aligning with frontbuffer tracking mechanism, the new structure contains data for busy frontbuffer bits. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 32 ++--- drivers/gpu/drm/i915/intel_dp.c | 50 ++-- drivers/gpu/drm

[Intel-gfx] [PATCH 9/10] drm/i915: Add debugfs entry for DRRS

Adding a debugfs entry to determine if DRRS is supported or not Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_debugfs.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e515aad

[Intel-gfx] [PATCH 3/10] drm/i915: Enable/disable DRRS

functions, to make sure the functions go through only if DRRS will work on the platform with the attached panel. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 54 drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer

from page_flip. This has not been tested on Android yet, but, in case DRRS transtions do not work as expected, check by adding back this call in page_flip. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 51 drivers/gpu/drm/i915

[Intel-gfx] [PATCH 8/10] Documentation/drm: DocBook integration for DRRS

Adding an overview of DRRS in general and the implementation for eDP DRRS. Also, describing the functions related to eDP DRRS. Signed-off-by: Vandana Kannan --- Documentation/DocBook/drm.tmpl | 11 + drivers/gpu/drm/i915/intel_dp.c | 95 + 2 files

[Intel-gfx] [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV

s R Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- drivers/gpu/drm/i915/intel_dp.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 25596ca..bb44fb9 100

[Intel-gfx] [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking

i-g-t. Durgadoss R (1): drm/i915: Enable eDP DRRS for CHV Vandana Kannan (9): drm/i915: Modifying structures related to DRRS drm/i915: Initialize DRRS delayed work drm/i915: Enable/disable DRRS drm/i915: DRRS calls based on frontbuffer drm/i915/bdw: Add support for DRRS to switch RR drm

[Intel-gfx] [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR

next frame that is output. Signed-off-by: Vandana Kannan Signed-off-by: Pradeep Bhat --- drivers/gpu/drm/i915/intel_display.c | 9 +++-- drivers/gpu/drm/i915/intel_dp.c | 15 ++- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 20 insertions(+), 7 deletions(-)

[Intel-gfx] [PATCH 6/10] drm/i915: Support for RR switching on VLV

Definition of VLV RR switch bit and corresponding toggling in set_drrs function. Signed-off-by: Vandana Kannan Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 10 -- 2 files changed, 9 insertions(+), 2

[Intel-gfx] [PATCH 10/10] kms_drrs: Test DRRS entry and exit

This test just display a frame on screen, waits for 1 second to enter DRRS and displays another frame to exit DRRS. TODO:- Notify the user about which refresh rate was used at different stages. Signed-off-by: Vandana Kannan --- tests/Makefile.sources | 1 + tests/kms_drrs.c | 225

[Intel-gfx] [RFC] drm/i915: Add gen check for fb size

From gen7, the platform can support fb of size < 3x3. Adding this check for gen along with fb width & height. Note: IVB is gen7 but its not clear if it can support width < 3 and height < 3. This patch has been tested in Android environment. Signed-off-by: Vandana Kannan --- dr

Re: [Intel-gfx] [PATCH] drm/i915: Idleness detection for DRRS

, I think it'd be good to first hash out > the rough design in more detail (maybe as a patch with just > pseudo-code) before starting with codeing. > > Thanks, Daniel > > > > On Thu, Aug 7, 2014 at 3:45 PM, Vandana Kannan > wrote: >> Adding support to detect display

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Program PFI credits for VLV

on them next week.. Thanks, Vandana On Aug-08-2014 6:33 PM, Ville Syrjälä wrote: > On Thu, Aug 07, 2014 at 06:40:03PM +0530, Vandana Kannan wrote: >> From: Vidya Srinivas >> >> PFI credit programming is required when CD clock (related to data flow from >> display

[Intel-gfx] [RFC 3/6] drm/i915: Enable/disable DRRS

Adding code to enable DRRS during ddi enable and disable DRRS during ddi disable Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 48 drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed

[Intel-gfx] [RFC 5/6] drm/i915/bdw: Add support for DRRS to switch RR

next frame that is output. Signed-off-by: Vandana Kannan Signed-off-by: Pradeep Bhat --- drivers/gpu/drm/i915/intel_display.c | 9 +++-- drivers/gpu/drm/i915/intel_dp.c | 15 ++- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 20 insertions(+), 7 deletions(-)

[Intel-gfx] [RFC 4/6] drm/i915: DRRS calls based on frontbuffer

Calls to switch between high and low refresh rates based on calls made to fb_invalidate and fb_flush. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_display.c | 5 drivers/gpu/drm/i915/intel_dp.c | 51 drivers/gpu/drm/i915

[Intel-gfx] [RFC 6/6] drm/i915: Support for RR switching on VLV

Definition of VLV RR switch bit and corresponding toggling in set_drrs function. Signed-off-by: Vandana Kannan Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 10 -- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a

[Intel-gfx] [RFC 0/6] eDP DRRS based on frontbuffer tracking

param to specify delay before scheduling DRRS work, (as there was in the old patch series), a delay of 100ms is used. Additional patches including changes specific to bdw and vlv have been included. TODO:- Need more analysis into clone mode scenario Vandana Kannan (6): drm/i915: Modifying

[Intel-gfx] [RFC 2/6] drm/i915: Initialize DRRS delayed work

Initializing DRRS work to program lower refresh rate. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 36 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [RFC 1/6] drm/i915: Modifying structures related to DRRS

Moving around and changing some data related to DRRS to support DRRS based on frontbuffer tracking in the following patches Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 32 ++--- drivers/gpu/drm/i915/intel_dp.c | 51

[Intel-gfx] [RFC 3/6] drm/i915: Program PPS registers

Actually set values into PPS related registers. This implementation is equivalent to intel_dp_panel_power_sequencer_registers where the values saved intially are written into registers. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c| 4 +- drivers/gpu/drm/i915

[Intel-gfx] [RFC 2/6] drm/i915: Define PPS setup functions

Defining functions equivalent to intel_dp_panel_power_sequencer. In the setup part, the differnce between vlv and other platforms is only w.r.t registers. Other parts like reading VBT are common. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm

[Intel-gfx] [RFC 0/6] Rearranging PPS related code

delays would be required for LVDS as well. The existing file intel_lvds.c does not make use of the delays. Vandana Kannan (6): drm/i915: Create PPS related struct and func pointers drm/i915: Define PPS setup functions drm/i915: Program PPS registers drm/i915: Removing refs to

[Intel-gfx] [RFC 1/6] drm/i915: Create PPS related struct and func pointers

types to generic intel_panel. Note:- Although edp_power_seq is used as a return type in the functions, the structure can be made generic for all panels. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 15 +++ drivers/gpu/drm/i915/intel_drv.h | 9 + 2 files

[Intel-gfx] [RFC 5/6] drm/i915: Replace all refs to intel_dp delays

Replacing intel_dp PPS delays with intel_panel PPS delays. This is part of removing all refs to PPS in intel_dp and moving it to PPS in intel_panel. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions

[Intel-gfx] [RFC 4/6] drm/i915: Removing refs to intel_dp_panel_power_sequencer

here ? Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 189 +--- 1 file changed, 2 insertions(+), 187 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a40d494..79ccf5a 100644 --- a/drivers/gpu

[Intel-gfx] [RFC 6/6] drm/i915: Modify refs to intel dp timestamps

Moving timestamp values to intel_panel as part of moving all refs of PPS to intel_panel. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c| 31 --- drivers/gpu/drm/i915/intel_drv.h | 12 drivers/gpu/drm/i915/intel_panel.c | 9

[Intel-gfx] [RFC 3/7] drm/i915: Split PPS setup code based on platform

In the setup part, the differnce between vlv and other platforms is only w.r.t registers. Other parts like reading VBT are common. Removing calls to setup PPS and registers again through vlv_setup_panel_power sequencer (this would be redundant). Signed-off-by: Vandana Kannan --- drivers/gpu/drm

[Intel-gfx] [RFC 1/7] drm/i915: Move around funcs related to eDP PPS

ctor. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 31 ++- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 8 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 64c

[Intel-gfx] [RFC 6/7] drm/i915: Replace all refs to intel_dp delays

Removing delays from intel_dp. Replacing intel_dp PPS delays with intel_panel PPS delays. This is part of removing all refs to PPS in intel_dp and moving it to PPS in intel_panel. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c | 22 +++--- drivers/gpu/drm

[Intel-gfx] [RFC 2/7] drm/i915: Setup PPS in intel_panel

Moving intel_dp_setup_panel_power_sequencer code to intel_panel.c to make PPS code generic in future patches. This patches substitutes references to intel_dp_setup_panel_power_sequencer with a new function in intel_panel.c. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [RFC v2 0/7] Rearranging PPS related code

use of the delays. v2: Splitting the patches per function and then splitting the functions per platform. Vandana Kannan (7): drm/i915: Move around funcs related to eDP PPS drm/i915: Setup PPS in intel_panel drm/i915: Split PPS setup code based on platform drm/i915: Program PPS registers

[Intel-gfx] [RFC 5/7] drm/i915: Split PPS reg write func based on platform

The difference between vlv and other platforms is w.r.t registers and port selection. Splitting the function to get value to be programmed based on platform and making the part which writes into registers common. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h| 4

[Intel-gfx] [RFC 4/7] drm/i915: Program PPS registers

Actually set values into PPS related registers. This implementation is equivalent to intel_dp_panel_power_sequencer_registers where the values saved intially are written into registers. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c| 80

[Intel-gfx] [RFC 7/7] drm/i915: Modify refs to intel dp timestamps

Moving timestamp values to intel_panel as part of moving all refs of PPS to intel_panel. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/intel_dp.c| 29 ++--- drivers/gpu/drm/i915/intel_drv.h | 7 --- drivers/gpu/drm/i915/intel_panel.c | 9 + 3

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