CZ clock is related to data flow from memory to display plane. This is
required for comparison with CD clock before programming PFI credits.
v2: Ville's review comments
- Re-ordered CCK_CZ_CONTROL
- Refactored get_clock_speed
Signed-off-by: Vandana Kannan <vandana.kan...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++++++++++++++------
3 files changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dccd0a2..881e0a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2784,6 +2784,8 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv,
u32 reg, u32 val);
int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
+int valleyview_get_cz_clock_speed(struct drm_device *dev);
+
#define FORCEWAKE_RENDER (1 << 0)
#define FORCEWAKE_MEDIA (1 << 1)
#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8275b7..fb111cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -616,6 +616,7 @@ enum punit_power_well {
#define DSI_PLL_N1_DIV_MASK (3 << 16)
#define DSI_PLL_M1_DIV_SHIFT 0
#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
+#define CCK_CZ_CONTROL 0x62
#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
#define CCK_TRUNK_FORCE_ON (1 << 17)
#define CCK_TRUNK_FORCE_OFF (1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f1f1b54..2089319 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5316,30 +5316,59 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
return 0;
}
-static int valleyview_get_display_clock_speed(struct drm_device *dev)
+enum disp_clk {
+ CDCLK,
+ CZCLK
+};
+
+static int valleyview_get_cck_clock_speed(struct drm_device *dev,
+ enum disp_clk clk)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int vco = valleyview_get_vco(dev_priv);
- u32 val;
+ u32 val, reg;
int divider;
- /* FIXME: Punit isn't quite ready yet */
- if (IS_CHERRYVIEW(dev))
- return 400000;
+ switch(clk) {
+ case CDCLK:
+ default:
+ reg = CCK_DISPLAY_CLOCK_CONTROL;
+ break;
+ case CZCLK:
+ reg = CCK_CZ_CONTROL;
+ break;
+ }
+
mutex_lock(&dev_priv->dpio_lock);
- val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
+ val = vlv_cck_read(dev_priv, reg);
mutex_unlock(&dev_priv->dpio_lock);
divider = val & CCK_FREQUENCY_VALUES;
WARN((val & CCK_FREQUENCY_STATUS) !=
(divider << CCK_FREQUENCY_STATUS_SHIFT),
- "cdclk change in progress\n");
+ "%sclk change in progress\n", (clk == CDCLK) ? "cd" : "cz");
return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
}
+static int valleyview_get_display_clock_speed(struct drm_device *dev)
+{
+ /* FIXME: Punit isn't quite ready yet */
+ if (IS_CHERRYVIEW(dev))
+ return 400000;
+ else
+ return valleyview_get_cck_clock_speed(dev, CDCLK);
+}
+
+int valleyview_get_cz_clock_speed(struct drm_device *dev)
+{
+ return valleyview_get_cck_clock_speed(dev, CZCLK);
+}
+
static int i945_get_display_clock_speed(struct drm_device *dev)
{
return 400000;
--
2.0.1
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