bxt_calc_pll_link() has been returning 0 all this while.
This patch adds calculation in bxt_calc_pll_link() based on the chv calculation
used in bxt_find_best_dpll().
Signed-off-by: Vandana Kannan <vandana.kan...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 38 ++++++++++++++++++++++++++++++++++++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac985c5..1d9c5dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1171,8 +1171,10 @@ enum skl_disp_power_wells {
#define _PORT_PLL_EBB_0_B 0x6C034
#define _PORT_PLL_EBB_0_C 0x6C340
#define PORT_PLL_P1_MASK (0x07 << 13)
+#define PORT_PLL_P1_SHIFT 13
#define PORT_PLL_P1(x) ((x) << 13)
#define PORT_PLL_P2_MASK (0x1f << 8)
+#define PORT_PLL_P2_SHIFT 8
#define PORT_PLL_P2(x) ((x) << 8)
#define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \
_PORT_PLL_EBB_0_B, \
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 42c1487..a8fbcc6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -968,8 +968,42 @@ static void hsw_ddi_clock_get(struct intel_encoder
*encoder,
static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
enum intel_dpll_id dpll)
{
- /* FIXME formula not available in bspec */
- return 0;
+ enum port port = (enum port)dpll; /* 1:1 port->PLL mapping */
+ uint32_t ebb0, pll0, pll2;
+ uint32_t m2_int, m2_frac;
+ intel_clock_t clock;
+ int refclk = 100000;
+
+ /*
+ * FIXME:
+ * The below calculation needs to be revisited if/when
+ * the calculation in bxt_find_best_dpll() changes.
+ */
+ clock.n = 1;
+ clock.m1 = 2;
+
+ ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
+ clock.p1 = (ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
+ clock.p2 = (ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
+
+ pll0 = I915_READ(BXT_PORT_PLL(port, 0));
+ m2_int = (pll0 & PORT_PLL_M2_MASK) << 22;
+
+ pll2 = I915_READ(BXT_PORT_PLL(port, 2));
+ m2_frac = (pll2 & PORT_PLL_M2_FRAC_MASK);
+
+ clock.m2 = m2_int | m2_frac;
+
+ clock.m = clock.m1 * clock.m2;
+ clock.p = clock.p1 * clock.p2;
+ if (WARN_ON(clock.n == 0 || clock.p == 0))
+ return 0;
+
+ clock.vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock.m,
+ clock.n << 22);
+ clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
+
+ return (clock.dot / 5);
}
static void bxt_ddi_clock_get(struct intel_encoder *encoder,
--
2.0.1
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