read of the current request.
>
> Suggested-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 --
> 1 file changed, 2 deletions(-)
>
&g
as part of a forced-preemption.
> In which case, do not waste time in suspending the request, capturing
> the error, and just cancel it instead.
>
> Testcase: igt/gem_ctx_persistence/many-contexts
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i91
y: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index f8c79
Chris Wilson writes:
> Verify that context isolation is also preserved when accessing
> context-local registers with relative-mmio commands.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 ++
gt; +static struct hwsp_semaphore hwsp_semaphore(struct intel_engine_cs *engine)
> +{
> + struct hwsp_semaphore s;
> +
> + s.va = memset32(engine->status_page.addr + 1000, 0, 1);
> + s.ggtt = (i915_ggtt_offset(engine->status_page.vma) +
> + offset_in_pa
Chris Wilson writes:
> As soon as we mark a request as completed, it may be retired. So when
> cancelling a request and marking it complete, make sure we first keep a
> reference to the request.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
Chris Wilson writes:
> The name very often may be freed independently of the fence, with the
> only protection being RCU. To be safe as we read the names, hold RCU.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_sw_fence.
Chris Wilson writes:
> Instead of copying the whole table to each category (mocs, l3cc), use a
> single table with a pointer to it if the category is enabled.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/se
Chris Wilson writes:
> Use the defaults we store on the engine when resetting the heartbeat as
> we may have had to adjust it from the config value during initialisation.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../gpu/drm/i915/gt/selftest_
led.
> @@ -139,6 +146,8 @@ static void heartbeat(struct work_struct *wrk)
> "stopped heartbeat on %s",
> engine->name);
> }
> +
> + rq->emitted_jiffies = ji
atic void print_request(struct drm_printer *m,
> rq->fence.context, rq->fence.seqno,
> i915_request_completed(rq) ? "!" :
> i915_request_started(rq) ? "*" :
> +!i915_sw_fence_signa
> Signed-off-by: Zhang Xiaoxu
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/selftests/i915_request.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
> b/drivers/gpu/drm/i915/selftests/i915_
Reported-by: Hulk Robot
> Signed-off-by: Zhang Xiaoxu
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/selftests/i915_request.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
> b/drivers/gpu/
Chris Wilson writes:
> The old IPS interface did not match the RPS interface that we tried to
> plug it into (bool vs int return). Once repaired, our minimal
> selftesting is finally happy!
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> dr
gned-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7f25894e41d5..0c7f1e3dee5c
Chris Wilson writes:
> The GT and engine reset failures are completely invisible when looking at
> a trace for a bug, but are vital to understanding the incomplete flow.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/
ht
> requests")
> Signed-off-by: Chris Wilson
> Cc: # v5.7+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel
rce preemption")
> Signed-off-by: Chris Wilson
> Cc: # v5.5+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/
f-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 25 ++---
> 1 file changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c5
dates do not prevent
> the faults. So far the only effect has been from inducing a delay
> between reuse of the iommu on the GPU.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 11 ++-
>
Chris Wilson writes:
> Now that the only user of the uninterruptible wait was eliminated,
> remove the support.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gt_requests.c | 7 +--
> 1 file changed, 1 inse
Chris Wilson writes:
> The heartbeat runs through a few phases that we expect to complete
> within a certain number of heartbeat intervals. First we must submit the
> heartbeat to the queue, and if the queue is occupied it may take a
> couple of intervals before the heartbeat preempts the workloa
Chris Wilson writes:
> Periodically check, for example when idling and upon closing user
> contexts, whether or not some client has written into unallocated PTE in
> their ppGTT.
>
> Signed-off-by: Chris Wilson
> ---
> .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++--
> drivers/gpu/
Chris Wilson writes:
> The surface_state_base is an offset into the batch, so we need to pass
> the correct batch address for STATE_BASE_ADDRESS.
>
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson
> Cc: Mika K
Chris Wilson writes:
> Quoting Mika Kuoppala (2021-02-10 10:49:55)
>> Chris Wilson writes:
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > index d34770ae4c9a..5ac9eb4a3a92 100644
>> > --- a/d
ab.freedesktop.org/drm/intel/-/issues/2508
> Testcase: igt/core_hotunplug
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu
ck.
>
> This impacts tgl/rcs0 as we rely on the heartbeat for our healthcheck for
> the normal preemption detection mechanism is disabled by default.
>
> Testcase: igt/gem_exec_schedule/preempt-hang/rcs0 #tgl
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
Reviewed-by: Mik
; in the ring that includes an expected wa_tail. (That is if the
> ring->tail is already set to rq->wa_tail, including another 8 bytes in
> the check does not invalidate the incremental wrap detection.)
>
> Fixes: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewi
Chris Wilson writes:
> The initial breadcrumb marks the transition from context wait and setup
> into the request payload. We use the marker to determine if the request
> is merely waiting to begin, or is inside the payload and hung.
> Forgetting to include a breadcrumb before the user payload wo
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-10-07 10:40:59)
>> Chris Wilson writes:
>>
>> > The initial breadcrumb marks the transition from context wait and setup
>> > into the request payload. We use the marker to determine if the request
>> >
Chris Wilson writes:
> When allocating objects from stolen, memset() the backing store to
> POISON_INUSE (0x5a) to help identify any uninitialised use of a stolen
> object.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/i
Chris Wilson writes:
Needs a commit message like:
Add support for dummyload to be userptr.
Reviewed-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> ---
> lib/igt_dummyload.c | 87 -
> lib/igt_dummyload.h | 13 --
&
Chris Wilson writes:
> In practice, it turns out that compute likes to use userptr for
> everything, and so in turn so must we.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_exec_schedule.c | 41 +++---
>
Chris Wilson writes:
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_exec_balancer.c | 46 +++---
> 1 file changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/g
that it had a tag after reading, tho double does no harm.
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 37 +++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 12 ++--
> 2 files changed, 34 insertions(+), 15 deletions(-)
>
&g
ting a delay on the GPU
> between requests.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Bruce Chang
> Cc: Joonas Lahtinen
> Cc: sta...@vger.kernel.org
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 inse
e. The value of 128KiB was found
> by empirical measurement (and verified now with a selftest) on gen9.
>
> Signed-off-by: Chris Wilson
> Cc: sta...@vger.kernel.org
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/Kconfig.debug | 1 +
> drivers/gpu/drm
7;s not busy-spin waiting for the
> old heartbeat, but terminate it and start afresh.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deleti
a couple of orders of magnitude.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_mmap_gtt.c | 23 ---
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_g
meline_cacheline *cl;
> +
> + /* Before the request is executed, the timeline/cachline is fixed */
s/cachline/cacheline
Reviewed-by: Mika Kuoppala
> +
> + cl = rcu_dereference_protected(rq->hwsp_cacheline, 1);
> + if (cl)
> + return cl->ggt
s from the HWSP and dispatch it at different
> points around a wrap to see if the value is lost.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 378 +++-
> 1 file changed, 376 insertions(+), 2 d
will wait for all cpus to enter
> the stop_machine callback, and those cpus may be waiting for the
> critical section already held.
>
> Fixes: d7085b0faac8 ("drm/i915/gem: Poison stolen pages before use")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by:
32 flags0, u32 flags1)
Opportunity to swap the offset/value to be in line with the actual qw
write. Just an observation rather than a value add proposal.
Reviewed-by: Mika Kuoppala
> {
> - /* We're using qword write, offset should be aligned to 8 bytes. */
> - GEM_BUG_ON(
e issue from being reproduced, we can presume the post-sync op is not
> so post-sync.
>
Only thing that is mildly surpricing is that first one doesnt
need postop write.
> Testcase: igt/gem_exec_fence/parallel
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: sta...@vger
Flush TDL,L3 and EUs
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 78f879ed4aa7..e1235d504837 100644
--- a/drivers/gpu/drm/i915/gt
: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 16 +++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1235d504837..bbdb0e2a4571 100644
This reverts commit 62037229b7d94f1db5ef8d2e2ec819832ef3.
L3 ro cache invalidation is part of the dword0 of pipe
control. Also it is not relevant to this gen.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 -
drivers/gpu/drm
HDC pipeline flush is bit on the first dword of
the PIPE_CONTROL, not the second. Make it so.
v2: function naming (Chris)
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 34
drivers/gpu/drm/i915/gt
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-05-06 15:47:34)
>> Aux table invalidation can fail on update. So
>> next access may cause memory access to be into stale entry.
>>
>> Proposed workaround is to invalidate entries between
>> all batchbuffers.
&g
: Rafael Antognolli
Cc: Yang A Shi
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 16 +++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt
Wilson
Cc: Chuansheng Liu
Cc: Rafael Antognolli
Cc: Yang A Shi
Signed-off-by: Mika Kuoppala
Acked-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 16 +++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers
cibly")
References bspec#43904, hsdes#1809175790
Cc: Chris Wilson
Cc: Chuansheng Liu
Cc: Rafael Antognolli
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 84 +++--
drivers/gpu/drm/i915/i915_reg.h | 6 +++
2 files changed, 85 insertions(+), 5
idate aux table entries
forcibly")
References bspec#43904, hsdes#1809175790
Cc: Chris Wilson
Cc: Chuansheng Liu
Cc: Rafael Antognolli
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 86 +++--
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 fil
Chris Wilson writes:
> While we ordinarily do not skip submit-fences due to the accompanying
> hook that we want to callback on execution, a submit-fence on the same
> timeline is meaningless.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_request.c | 3
Chris Wilson writes:
> As a means for a small code consolidation, but primarily to start
> thinking more carefully about internal-vs-external linkage, pull the
> pair of i915_sw_fence_await_dma_fence() calls into a common routine.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i91
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-05-08 11:19:25)
>> Chris Wilson writes:
>>
>> > As a means for a small code consolidation, but primarily to start
>> > thinking more carefully about internal-vs-external linkage, pull the
>> > pair of
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-05-08 10:57:37)
>> Chris Wilson writes:
>>
>> > While we ordinarily do not skip submit-fences due to the accompanying
>> > hook that we want to callback on execution, a submit-fence on the same
>> >
Chris Wilson writes:
> The downside of using semaphores is that we lose metadata passing
> along the signaling chain. This is particularly nasty when we
> need to pass along a fatal error such as EFAULT or EDEADLK. For
> fatal errors we want to scrub the request before it is executed,
> which mea
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-05-08 16:37:15)
>> Chris Wilson writes:
>>
>> > The downside of using semaphores is that we lose metadata passing
>> > along the signaling chain. This is particularly nasty when we
>> > need to
Chris Wilson writes:
> Just tidy up the return handling for completed dma-fences. While it may
> return errors for invalid fence, we already know that we have a good
> fence and the only error will be an already signaled fence.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_s
Chris Wilson writes:
> Since we are using bitops on context_tag to allow us to reserve and
> release inflight tags concurrently, the scan for the next bit is
> intentionally racy.
Now it truely sinks in why you started with a full mask.
Reviewed-by: Mika Kuoppala
-Mika
>
>
Commit fb5970da1b42 ("drm/i915/gt: Use the kernel_context to measure the
breadcrumb size") removed the last external user for intel_timeline_init.
Mark it static.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 8
drive
Chris Wilson writes:
> The initial-breadcrumb is used to mark the end of the awaiting and the
> beginning of the user payload. We verify that we do not start the user
> payload before all signaler are completed, checking our semaphore setup
> by looking for the initial breadcrumb being written to
Chris Wilson writes:
> Just tidy up the return handling for completed dma-fences. While it may
> return errors for invalid fence, we already know that we have a good
> fence and the only error will be an already signaled fence.
>
> Signed-off-by: Chris Wilson
Reviewed-by
l writes are visible.
>
> v2: Add the unconditional wmb so we are know that we always flush the
> writes to memory/HW at that point.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 8 ++--
> dr
experimental patch from
Chris Wilson of adding wmb for coherent partners,
by adding a clflush to force the cache->memory step.
Testcase: igt/gem_exec_fence/parallel
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 14 --
1 file changed, 12 inserti
e asynchronous binds, and the
> remaining issues do not seem restricted to Cherryview [at least the ones
> seen over a few dozen CI runs, less frequent issues are sure to be
> discovered!]
>
> Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
> ---
t; Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: # v5.5+
Only thing I would change is tune up the subject line.
It fixes a possible busy loop in eviction so I feel 'watch out' is not
strong enough for my liking.
Reviewed-by: Mika Kuoppala
>
Daniele Ceraolo Spurio writes:
> On 5/7/20 7:20 AM, Mika Kuoppala wrote:
>> All engines, exception being blitter as it does not
>> care about the form, can access compressed surfaces.
>>
>> So we need to add forced aux table invalidates
>> for those engines.
&g
so rejig the register reset.
>
> Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +--
> 1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers
0 [i915]
> <4>[ 449.386797] gt_sanitize+0xd6/0x260 [i915]
>
> As part of the reset preparation, engine->reset.prepare() prevents the
> tasklet from running, so pull the sanitization inside the critical
> section for reset.
>
> Closes: https://gitlab.freedesktop.org/d
cking on the semaphore caused extremely bad scheduling with multiple
> clients utilising multiple rings. Now, there is no impact and we can
> remove the complication.
Not a small feat to accomplish.
Reviewed-by: Mika Kuoppala
>
> Signed-off-by: Chris Wilson
> ---
> .../gpu/drm/
Chris Wilson writes:
> Since there can only be one of in_fence/exec_fence, just use the single
> in_fence local.
>
> Signed-off-by: Chris Wilson
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 24 ---
> 1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/d
Chris Wilson writes:
> Since there can only be one of in_fence/exec_fence, just use the single
> in_fence local.
>
> v2: Considate lookup
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> .../gpu/drm/i915/gem/i9
eing written too early. We also
> want to ensure that we do not add semaphore waits after we have already
> closed the semaphore section, an issue for later deferred waits.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c
Chris Wilson writes:
> While this does not appear to fix any issues, the backend itself knows
> when it wants to emit a breadcrumb, so let it make the final call.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/selftests
Chris Wilson writes:
> A useful metric of the system's health is how fast we can tell the GPU
> to do various actions, so measure our latency.
>
> v2: Refactor all the instruction building into emitters.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuopp
_BIND, but for the moment this
> suffices to construct the GTT as required for arbitrary
> *user-controlled* indirect execution.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> ---
> lib/igt_core.h| 1 +
> tests/Makefile.sou
Chris Wilson writes:
> A useful metric of the system's health is how fast we can tell the GPU
> to do various actions, so measure our latency.
>
> v2: Refactor all the instruction building into emitters.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> C
nning with only the inflight request.
s/nnn/nn
Reviewed-by: Mika Kuoppala
>
> Fixes: 6cebcf746f3f ("drm/i915: Tweak scheduler's kick_submission()")
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_scheduler.c | 16
> 1 file changed
Chris Wilson writes:
> Since we temporarily disable the heartbeat and restore back to the
> default value, we can use the stored defaults on the engine and avoid
> using a local.
>
> Signed-off-by: Chris Wilson
> ---
Reviewed-by: Mika Kuoppala
> drivers/gpu/drm/i915/gt
Chris Wilson writes:
> Check for integer overflow in the priority chain, rather than against a
> type-constricted max-priority check.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 6 +++---
> 1 file change
clare that a request has
> been already submitted too early.
submittedstarted...handled_by_gpu.
I guess wait_for_submit is generic enough to cater all cases
but we actually do not wait for submit but we wait for
gpu to reach it.
>
> Signed-off-by: Chris Wilson
Revie
that the finit goes as you expect, you
could add two cancel_delayed_work_sync and assert
that the final one return false.
Reviewed-by: Mika Kuoppala
> }
>
> void intel_gt_fini_buffer_pool(struct intel_gt *gt)
> --
> 2.20.1
>
>
Chris Wilson writes:
> Leave the error propagation in place, but limit the warnings to only
> show up in CI if the unlikely errors are hit.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +--
> dri
l/-/issues/1880
> Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 11 +++
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.
eed with the reset as we
> shutdown the module. We know the next user must reinitialise the HW for
> their purpose.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/489
> Signed-off-by: Chris Wilson
> Cc: sta...@kernel.org
Reviewed-by: Mika Kuoppala
> ---
> dr
154 -15
> __execlists_submission_tasklet 46964659 -37
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
->execute_cb));
> spin_unlock_irq(&rq->lock);
>
> remove_from_client(rq);
> @@ -395,7 +394,8 @@ __await_execution(struct i915_request *rq,
> i915_sw_fence_complete(cb->fence);
> kmem_cache_free(global.slab
* ringbuffer. If one context is blocked on an
> + * external fence, not only is it not submitted,
> + * but all other contexts, including the kernel
> + * context are stuck waiting for the signal.
> +
it.
If this is last in a line, it makes sense to make sure
that we get woken up.
Reviewed-by: Mika Kuoppala
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>
Chris Wilson writes:
> Across the many users of the GGTT vma (internal objects, mmapings,
> display etc), we may end up with conflicting requirements for the
> placement. Currently, we try to resolve the conflict by unbinding the
> vma and rebinding it to match the new constraints; over time we w
l_engines_release+0x68/0xc0 [i915]
> [ 16.136680] intel_engines_release+0x49/0xc0 [i915]
> [ 16.136757] intel_gt_init+0x2f4/0x5e0 [i915]
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +++---
> 1 file c
Chris Wilson writes:
> Ever noticed that our interrupt handlers are where we spend most of our
> time on a busy system? In part this is unavoidable as each interrupt
> requires to poll and reset several registers, but we can try and so as
> efficiently as possible.
>
> Function
Chris Wilson writes:
> Sometimes an engine might need to keep forcewake active while it is busy
> submitting requests for a particular workaround. Track such nuisance
> with engine->fw_domain.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
>
pact. [So we don't do that anymore!
> Hopefully, this will spare us from still needing the mitigation of the
> timer for steady state execution.]
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
I am not a fan of having explicit put relying on ti
63 72 +9
> ilk_irq_handler 22212080-141
>
> A slight improvement in the baseline overnight as well!
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_irq.c | 59 +--
Chris Wilson writes:
> As we rewrite the batches on the fly to implement the non-preemptible
> lock, we need to tell Tigerlake to read the batch afresh each time.
> Amusingly, the disable is a part of an arb-check, so we have to be
> careful not to include the arbitration point inside our unpreem
Chris Wilson writes:
> Allow batch buffers to read their own _local_ cumulative HW runtime of
> their logical context.
>
> Fixes: 0f2f39758341 ("drm/i915: Add gen9 BCS cmdparsing")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: # v5.4+
Reviewed-by: M
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-06-01 15:56:55)
>> Chris Wilson writes:
>>
>> > As we rewrite the batches on the fly to implement the non-preemptible
>> > lock, we need to tell Tigerlake to read the batch afresh each time.
>> >
901 - 1000 of 3589 matches
Mail list logo
