[Intel-gfx] [PATCH 2/9] drm/i915: Update i915.reset to handle engine resets

From: Arun Siluvery In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 8/9] drm/i915/tdr: Enable Engine reset and recovery support

From: Arun Siluvery This feature is made available only from Gen8, for previous gen devices driver uses legacy full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Tomas Elf Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_params.c | 4

[Intel-gfx] [PATCH 0/9] Execlist based engine-reset

recovery drm/i915/tdr: Add engine reset count to error state drm/i915/tdr: Export per-engine reset count info to debugfs drm/i915/tdr: Enable Engine reset and recovery support Michel Thierry (2): drm/i915: Keep i915_handle_error kerneldoc parameters together drm/i915: Add engine reset

[Intel-gfx] [PATCH 1/9] drm/i915: Keep i915_handle_error kerneldoc parameters together

And before the function description. Tidy up from commit 14bb2c11796d70b ("drm/i915: Fix a buch of kerneldoc warnings"), all others kerneldoc blocks look ok. Cc: Tvrtko Ursulin Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_irq.c | 3 ++- 1 file changed, 2 insert

[Intel-gfx] [PATCH 6/9] drm/i915/tdr: Add engine reset count to error state

Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++ 3 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c

[Intel-gfx] [PATCH 7/9] drm/i915/tdr: Export per-engine reset count info to debugfs

: Mika Kuoppala Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_debugfs.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 54e196d9d83e..b2a3c31ba95c

[Intel-gfx] [PATCH 5/9] drm/i915: Skip reset request if there is one already

unnecessary. To avoid this we check if the engine is already prepared, if so we just exit from that point. Cc: Chris Wilson Signed-off-by: Mika Kuoppala Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_uncore.c | 9 +++-- 1 file changed, 7 insertions

[Intel-gfx] [RFC 9/9] drm/i915: Add engine reset count in get-reset-stats ioctl

it is deemed useful, it can be extended to report each engine separately. Cc: Chris Wilson Cc: Mika Kuoppala Cc: mesa-...@lists.freedesktop.org Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.c | 14 +++--- include/uapi/drm/i915_drm.h | 3 ++- 2 files

[Intel-gfx] [PATCH 4/9] drm/i915/tdr: Add support for per engine reset recovery

Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 56 +++-- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c| 12 drivers/gpu/drm/i915/intel_lrc.h

[Intel-gfx] [PATCH 3/9] drm/i915/tdr: Modify error handler for per engine hang recovery

igned-off-by: Ian Lister Signed-off-by: Tomas Elf Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 21 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_irq.c | 88 +++-- driver

Re: [Intel-gfx] [PATCH 6/9] drm/i915/tdr: Add engine reset count to error state

On 16/12/16 12:37, Chris Wilson wrote: On Fri, Dec 16, 2016 at 12:20:07PM -0800, Michel Thierry wrote: From: Arun Siluvery Driver maintains count of how many times a given engine is reset, useful to capture this in error state also. It gives an idea of how engine is coping up with the

Re: [Intel-gfx] [PATCH 4/9] drm/i915/tdr: Add support for per engine reset recovery

On 12/16/2016 12:45 PM, Chris Wilson wrote: On Fri, Dec 16, 2016 at 12:20:05PM -0800, Michel Thierry wrote: From: Arun Siluvery This change implements support for per-engine reset as an initial, less intrusive hang recovery option to be attempted before falling back to the legacy full GPU

Re: [Intel-gfx] [PATCH v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf

; } + /* WaProgramL3SqcReg1DefaultForPerf:bxt */ + if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) + I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT); + return 0; } lgtm, Reviewed-by: Michel Thierry ___ Intel-gfx

Re: [Intel-gfx] [PATCH v5] igt/gem_trtt: Exercise the TRTT hardware

iction of active/hanging objects overlapping with the TR-TT segment (Chris). - Move gen8_canonical_addr to igt_aux as its needed by other tests also, which does soft pinning, and not just gem_softpin (Michel) Cc: Chris Wilson Cc: Michel Thierry Signed-off-by: Akash Goel Test looks good

Re: [Intel-gfx] [PATCH] drm/i915/kbl: Adding missing IS_KABYLAKE checks.

working on KBL. Is the referenced commit by Michel also required? Michel had found the main error first and his fix had better details on the history and got merged already: commit 16fbc291cb87c7defcd13ad715d3e4af0d523e43 Author: Michel Thierry Date: Wed Jan 6 12

Re: [Intel-gfx] [PATCH v2] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf

On 4/20/2016 3:23 PM, tim.g...@intel.com wrote: From: Tim Gore This patch applies a performance enhancement workaround based on analysis of DX and OCL S-Curve workloads. v2: Only apply to B0 onwards Signed-off-by: Tim Gore --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH i-g-t] lib/igt_gt: Define HANG_ALLOW_* as bit flags

As that is what they are meant to be. It will prevent any confusion if we have to add other flags in the future. Signed-off-by: Michel Thierry --- lib/igt_gt.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/igt_gt.h b/lib/igt_gt.h index e44b6db1..d83e23a1 100644

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_gt: Define HANG_ALLOW_* as bit flags

On 08/02/17 04:49, Chris Wilson wrote: On Wed, Feb 08, 2017 at 02:42:03PM +0200, Joonas Lahtinen wrote: On ti, 2017-02-07 at 18:00 -0800, Michel Thierry wrote: As that is what they are meant to be. It will prevent any confusion if we have to add other flags in the future. Signed-off-by

[Intel-gfx] [PATCH i-g-t 8/8] tests: Use BIT macro instead of (1<

Mostly done with coccinelle, @@ expression x; @@ ( - (1< --- tests/drm_vma_limiter_cached.c | 2 +- tests/drv_missed_irq.c | 4 +- tests/drv_module_reload.c | 4 +- tests/eviction_common.c | 8 ++-- tests/gem_bad_address.c | 2 +- tests/gem_

[Intel-gfx] [PATCH i-g-t 1/8] lib/igt: remove duplicate igt_core include

igt_core must be really important, but no need to do it twice. Signed-off-by: Michel Thierry --- lib/igt.h | 1 - 1 file changed, 1 deletion(-) diff --git a/lib/igt.h b/lib/igt.h index a97923ec..4f54698d 100644 --- a/lib/igt.h +++ b/lib/igt.h @@ -29,7 +29,6 @@ #include "i915_pci

[Intel-gfx] [PATCH i-g-t 3/8] lib: Define a common bit operations library

Bring the test/set/clear bit functions we have into a single place. Signed-off-by: Michel Thierry --- lib/igt.h| 1 + lib/igt_bitops.h | 69 lib/igt_primes.c | 25 +--- 3 files changed, 71 insertions(+), 24

[Intel-gfx] [PATCH i-g-t 0/8] Add a bit operations library

o test are not longer bits, but normal numbers, e.g. 3 instead of BIT(3), so I decided against changing code to use it. Cc: Chris Wilson Cc: Joonas Lahtinen Michel Thierry (8): lib/igt: remove duplicate igt_core include lib/igt_draw: rename BIT macro to BIT_GET lib: Define a common bit

[Intel-gfx] [PATCH i-g-t 5/8] lib/igt_draw: Use igt_bitops

Moving bit operations to the new header file. Signed-off-by: Michel Thierry --- lib/igt_bitops.h | 1 + lib/igt_draw.c | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/igt_bitops.h b/lib/igt_bitops.h index 11e0d8b5..331946f6 100644 --- a/lib/igt_bitops.h +++ b/lib

[Intel-gfx] [PATCH i-g-t 2/8] lib/igt_draw: rename BIT macro to BIT_GET

Keeping macros names unique. We'll soon have a bit operations header file and BIT is already taken. Signed-off-by: Michel Thierry --- lib/igt_draw.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/lib/igt_draw.c b/lib/igt_draw.c index 3afb8272..2b321715 1

[Intel-gfx] [PATCH i-g-t 7/8] test/gem_create: import igt_bitops

It will make sense once we use the BIT macro. Signed-off-by: Michel Thierry --- tests/gem_create.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/gem_create.c b/tests/gem_create.c index de7b8209..4036dbe6 100644 --- a/tests/gem_create.c +++ b/tests/gem_create.c @@ -53,6 +53,7

[Intel-gfx] [PATCH i-g-t 6/8] lib/igt_gt: Define HANG_ALLOW_* as bit flags

As that is what they are meant to be. It will prevent any confusion when we have to add other flags in the future. v2: use BIT (Joonas). Reviewed-by: Joonas Lahtinen Signed-off-by: Michel Thierry --- lib/igt_gt.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib

[Intel-gfx] [PATCH i-g-t 4/8] lib/intel_device_info: Use igt_bitops

BIT macro already defined in the new bitops header. Signed-off-by: Michel Thierry --- lib/intel_device_info.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c index db4f3831..b5ad6236 100644 --- a/lib/intel_device_info.c

[Intel-gfx] [PATCH v2 5/7] lib/igt_draw: Use igt_bitops

Moving bit operations to the new header file. v2: rename the args for consistency with the other macros (Joonas) Reviewed-by: Joonas Lahtinen Signed-off-by: Michel Thierry --- lib/igt_bitops.h | 1 + lib/igt_draw.c | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib

[Intel-gfx] [PATCH i-g-t v2 7/7] tests: Use BIT macro instead of (1<

Mostly done with coccinelle, @@ expression x; @@ ( - (1< Cc: Joonas Lahtinen Signed-off-by: Michel Thierry --- tests/drv_missed_irq.c | 4 +- tests/drv_module_reload.c | 4 +- tests/eviction_common.c | 8 ++-- tests/gem_bad_address.c |

Re: [Intel-gfx] [PATCH i-g-t 7/8] test/gem_create: import igt_bitops

On 09/02/17 01:57, Joonas Lahtinen wrote: On ke, 2017-02-08 at 18:18 -0800, Michel Thierry wrote: It will make sense once we use the BIT macro. Signed-off-by: Michel Thierry Squash this to the later patch that actually uses these. Regards, Joonas OK, squashed into the amended "Us

[Intel-gfx] [PATCH i-g-t v2 5/7] lib/igt_draw: Use igt_bitops

Moving bit operations to the new header file. v2: rename the args for consistency with the other macros (Joonas) Reviewed-by: Joonas Lahtinen Signed-off-by: Michel Thierry --- lib/igt_bitops.h | 1 + lib/igt_draw.c | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib

Re: [Intel-gfx] [PATCH] drm/i915: Move the irq_barrier for reset earlier into reset_prepare

, Reviewed-by: Michel Thierry diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index ed60d5881b40..3066f94da8f0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2677,6 +2677,9 @@ int i915_gem_reset_prepare(struct drm_i915_private

[Intel-gfx] [PATCH i-g-t] gitignore: Add files starting with .

I cant be the only one that have added .tags by mistake. Cc: Marius Vlad Cc: Petri Latvala Signed-off-by: Michel Thierry --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 6204965a..e1457bf6 100644 --- a/.gitignore +++ b/.gitignore @@ -81,6 +81,7

Re: [Intel-gfx] [PATCH i-g-t] gitignore: Add files starting with .

On 15/02/17 04:24, Joonas Lahtinen wrote: On pe, 2017-02-10 at 12:37 -0800, Michel Thierry wrote: I cant be the only one that have added .tags by mistake. Cc: Marius Vlad Cc: Petri Latvala Signed-off-by: Michel Thierry +++ b/.gitignore @@ -81,6 +81,7 @@ core *.swo *.swp *.dirstamp

[Intel-gfx] [PATCH i-g-t v2] gitignore: Add files starting with .

I cant be the only one that have added .tags by mistake. v2: Do not ignore .gitignore Cc: Petri Latvala Cc: Joonas Lahtinen Signed-off-by: Michel Thierry --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 6204965a..4d5867a2 100644 --- a

[Intel-gfx] [PATCH i-g-t v3] gitignore: Add files starting with .

I cant be the only one that have added .tags by mistake. v2: Do not ignore .gitignore v3: Move !.gitignore at the end, otherwise it'll ignore new .gitignore files in another directory (Petri) Cc: Petri Latvala Cc: Joonas Lahtinen Signed-off-by: Michel Thierry --- .gitignore | 6

[Intel-gfx] [PATCH i-g-t] igt/drv_hangman: Fix clear_error_state

ilson Fixes: 79c6a84ca85b ("igt/drv_hangman: Migrate to sysfs") Signed-off-by: Michel Thierry --- tests/drv_hangman.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c index cafdf4c1..43f73661 100644 --- a/test

Re: [Intel-gfx] [PATCH i-g-t] igt/drv_hangman: Fix clear_error_state

On 22/02/17 18:04, Chris Wilson wrote: On Thu, Feb 23, 2017 at 01:52:04AM +, Chris Wilson wrote: On Wed, Feb 22, 2017 at 05:26:29PM -0800, Michel Thierry wrote: static void clear_error_state(void) { - igt_sysfs_set(sysfs, "error", ""); + igt_sys

[Intel-gfx] [PATCH i-g-t v2] igt/drv_hangman: Fix clear_error_state

s_set to catch future errors, clean-up strcasecmp logic (Chris). Cc: Chris Wilson Fixes: 79c6a84ca85b ("igt/drv_hangman: Migrate to sysfs") Signed-off-by: Michel Thierry --- lib/igt_sysfs.c | 26 ++ lib/igt_sysfs.h | 1 + tests/drv_hangman.c | 4 ++-- 3

Re: [Intel-gfx] [PATCH i-g-t v2] igt/drv_hangman: Fix clear_error_state

On 22/02/17 18:31, Michel Thierry wrote: v2: Use new igt_sysfs_write, add len > 0 assert in igt_sysfs_set to catch future errors, clean-up strcasecmp logic (Chris). Nevermind, didn't see you were faster than me... ___ Intel-gfx mailing list I

Re: [Intel-gfx] [PATCH] drm/i915: Split I915_RESET_IN_PROGRESS into two flags

. +*/ unsigned long flags; -#define I915_RESET_IN_PROGRESS 0 +#define I915_RESET_BACKOFF 0 +#define I915_RESET_HANDOFF 1 #define I915_WEDGED(BITS_PER_LONG - 1) /** I've been looking fwd this change, Acked-by: Michel Th

[Intel-gfx] [PATCH i-g-t 2/2] tests/drv_hangman: watchdog tests

Test watchdog triggered resets. Signed-off-by: Michel Thierry --- tests/drv_hangman.c | 30 +- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c index 51bdbdaa..ba230f65 100644 --- a/tests/drv_hangman.c +++ b

[Intel-gfx] [PATCH i-g-t 1/2] lib/igt_gt: Add watchdog gem_ctx_set_param ioctl interface

Set a watchdog timeout value in a given context. Signed-off-by: Michel Thierry --- lib/igt_gt.c | 7 +++ lib/igt_gt.h | 1 + 2 files changed, 8 insertions(+) diff --git a/lib/igt_gt.c b/lib/igt_gt.c index 3bfaf2e4..e30385ec 100644 --- a/lib/igt_gt.c +++ b/lib/igt_gt.c @@ -40,6 +40,7

[Intel-gfx] [RFC 1/3] drm/i915: Watchdog timeout: IRQ handler for gen8+

he counter is different between render and non-render engines. Signed-off-by: Tomas Elf Signed-off-by: Ian Lister Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h| 4 drivers/gpu/drm/i915/i915_irq.c

[Intel-gfx] [RFC 2/3] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+

Emit the required commands into the ring buffer for starting and stopping the watchdog timer before/after batch buffer start during batch buffer submission. Signed-off-by: Tomas Elf Signed-off-by: Ian Lister Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915

[Intel-gfx] [RFC 3/3] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

ned-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.c| 46 ++ drivers/gpu/drm/i915/i915_gem_context.h| 3 ++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +- include/uapi/drm/i915_drm.h| 1 + 4 files changed, 51 insert

Re: [Intel-gfx] [RFC 1/3] drm/i915: Watchdog timeout: IRQ handler for gen8+

On 23/02/17 12:57, Chris Wilson wrote: On Thu, Feb 23, 2017 at 11:44:17AM -0800, Michel Thierry wrote: *** General *** Watchdog timeout (or "media engine reset") is a feature that allows userland applications to enable hang detection on individual batch buffers. The detection

Re: [Intel-gfx] [RFC 1/3] drm/i915: Watchdog timeout: IRQ handler for gen8+

On 23/02/17 13:49, Chris Wilson wrote: On Thu, Feb 23, 2017 at 01:21:03PM -0800, Michel Thierry wrote: On 23/02/17 12:57, Chris Wilson wrote: On Thu, Feb 23, 2017 at 11:44:17AM -0800, Michel Thierry wrote: *** General *** Watchdog timeout (or "media engine reset") is a fe

[Intel-gfx] [PATCH] drm/i915: Include GuC fw version in error state

There was no way to check if the platform is running the latest firmware. Cc: Tvrtko Ursulin Cc: Arkadiusz Hiler Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b

Re: [Intel-gfx] [PATCH] drm/i915: Include GuC fw version in error state

On 2/24/2017 2:40 AM, Michal Wajdeczko wrote: On Thu, Feb 23, 2017 at 03:11:37PM -0800, Michel Thierry wrote: There was no way to check if the platform is running the latest firmware. Can we also add similar patch for the HuC ? Please don't tell me the HuC can hang the gpu too.

Re: [Intel-gfx] [PATCH] drm/i915: Include GuC fw version in error state

On 2/24/2017 8:15 AM, Michel Thierry wrote: On 2/24/2017 2:40 AM, Michal Wajdeczko wrote: On Thu, Feb 23, 2017 at 03:11:37PM -0800, Michel Thierry wrote: There was no way to check if the platform is running the latest firmware. Can we also add similar patch for the HuC ? Please don&#

Re: [Intel-gfx] [PATCH] drm/i915: Include GuC fw version in error state

:41 AM, Michel Thierry wrote: There was no way to check if the platform is running the latest firmware. Cc: Tvrtko Ursulin [2] Cc: Arkadiusz Hiler [3] Signed-off-by: Michel Thierry [4] --- drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a

Re: [Intel-gfx] [PATCH] drm/i915: Include GuC fw version in error state

On 2/24/2017 9:15 AM, Chris Wilson wrote: On Fri, Feb 24, 2017 at 08:30:43AM -0800, Michel Thierry wrote: On 2/24/2017 2:49 AM, Chris Wilson wrote: On Fri, Feb 24, 2017 at 11:43:32AM +0100, Michal Wajdeczko wrote: On Fri, Feb 24, 2017 at 09:13:29AM +, Chris Wilson wrote: On Fri, Feb 24

[Intel-gfx] [PATCH 3/3] drm/i915: Include HuC fw version in error state

HuC depends on GuC, so be it. Suggested-by: Michal Wajdeczko Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu

[Intel-gfx] [PATCH 1/3] drm/i915: Capture dmc firmware information before reset

The firmware may change between the hang and cat /sys/class/drm/card0/error Cc: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 4 drivers/gpu/drm/i915/i915_gpu_error.c | 22 -- 2 files changed, 20 insertions(+), 6 deletions

[Intel-gfx] [PATCH 2/3] drm/i915: Include GuC fw version in error state

There was no way to check if the platform is running the latest firmware. v2: use HAS_GUC and intel_guc* (Michal) capture before reset (Chris) Cc: Chris Wilson Cc: Michal Wajdeczko Cc: Tvrtko Ursulin Cc: Arkadiusz Hiler Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Capture dmc firmware information before reset

On 2/24/2017 11:22 AM, Chris Wilson wrote: On Fri, Feb 24, 2017 at 11:05:28AM -0800, Michel Thierry wrote: The firmware may change between the hang and cat /sys/class/drm/card0/error Cc: Chris Wilson Signed-off-by: Michel Thierry Looks sane... --- drivers/gpu/drm/i915/i915_drv.h

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Capture dmc firmware information before reset

On 2/24/2017 11:34 AM, Chris Wilson wrote: On Fri, Feb 24, 2017 at 11:25:29AM -0800, Michel Thierry wrote: On 2/24/2017 11:22 AM, Chris Wilson wrote: On Fri, Feb 24, 2017 at 11:05:28AM -0800, Michel Thierry wrote: The firmware may change between the hang and cat /sys/class/drm/card0/error Cc

[Intel-gfx] [PATCH v2 3/3] drm/i915: Include HuC fw version in error state

HuC depends on GuC, so be it. v2: if version is 0, the fw was not loaded. Suggested-by: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Reviewed-by: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 9

[Intel-gfx] [PATCH v2 2/3] drm/i915: Include GuC fw version in error state

Wajdeczko Reviewed-by: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 15 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index

[Intel-gfx] [PATCH v2 1/3] drm/i915: Capture dmc firmware information before reset

The firmware may change between the hang and cat /sys/class/drm/card0/error v2: if version is 0, the fw was not loaded. Cc: Chris Wilson Reviewed-by: Michal Wajdeczko Reviewed-by: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm

Re: [Intel-gfx] [PATCH] drm/i915: Remove wrong warning from i915_gem_context_clean

ned-off-by: Tvrtko Ursulin Cc: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 680b4c9f6b73..8c688a5f1589 100644 --- a/drivers/gp

[Intel-gfx] [PATCH] drm/i915: Log correct start and length in pte map trace

The PTE_map trace added in commit 4c06ec8d13d2 ("drm/i915/gen8: Add dynamic page trace events") was using the full start and length values, instead of the page directory ones. Since this is just a trace, I don't think it requires cc'ing stable. Cc: Akash Goel Signed-of

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gen8: Flip the 48b switch

On 10/1/2015 2:16 PM, Daniel Vetter wrote: On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote: Use 48b addresses if hw supports it (i915.enable_ppgtt=3). Update the sanitize_enable_ppgtt for 48 bit PPGTT mode. Note, aliasing PPGTT remains 32b only. v2: s/full_64b/full_48b/. (Akash

[Intel-gfx] [PATCH] drm/i915/kbl: Enable PW1 and Misc I/O power wells

Cc: Patrik Jakobsson Cc: Imre Deak Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index ddbdbff..4b44e68 100644

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_softpin: Use offset addresses in canonical form

On 1/6/2016 10:48 AM, Tvrtko Ursulin wrote: Hi, I've seen the RB but unfortunately I think we need another small tweak: On 11/12/15 14:14, Michel Thierry wrote: i915 validates that requested offset is in canonical form, so tests need to convert the offsets as required. Also add te

[Intel-gfx] [PATCH v2 i-g-t] tests/gem_softpin: Use offset addresses in canonical form

-by: Vinay Belgaumkar (v1) Signed-off-by: Michel Thierry --- tests/gem_softpin.c | 69 + 1 file changed, 49 insertions(+), 20 deletions(-) diff --git a/tests/gem_softpin.c b/tests/gem_softpin.c index 0919716..1cbde4e 100644 --- a/tests

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Cleanup some of the CSB handling

tus) & GEN8_CSB_WRITE_PTR_MASK) >> 0) +#define GEN8_CSB_READ_PTR(csb_status) \ + (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8) + /* Logical Rings */ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request); int intel_logical_ring_reserve_s

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Change WARN to ERROR in CSB count

events?\n"); + ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; /* Update the read pointer to the old write pointer. Manual ringbuffer And it's unlikely we'd recover without some kind of GPU reset... Reviewed-by: Michel Thierry -- 2.6.4 ___

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Extract CSB status read

% GEN8_CSB_ENTRIES)); + + get_context_status(ring, ++read_pointer % GEN8_CSB_ENTRIES, + &status, &status_id); if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) continue; -- 2.6.4 Future GENs may need a completely new lrc_irq_handl

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add basic execlist info to error state

On 1/5/2016 6:30 PM, Ben Widawsky wrote: Sample output: ... waiting: yes ring->head: 0x ring->tail: 0x0c50 ring->next_context_status_buffer: 0x5 CSB Pointer: 0x0405 Context 0 Status: 0x0001 Context 1 Status: 0x009d0018 Context 2 St

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Use CSB helper in debugfs

On 1/5/2016 6:30 PM, Ben Widawsky wrote: Since we extracted it for use in error state, we may as well use it in debugfs too. Signed-off-by: Ben Widawsky Reviewed-by: Michel Thierry (depends on patch 4/5, where I have a small request) --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +-- 1

[Intel-gfx] [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page

ation, it is not possible to address full 4GB memory region. A32 Stateless Model is used by some libraries and without this patch, the last page of 4GB address space is not accessible in 32bit processes. Reported-by: Artur Harasimiuk Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem.

Re: [Intel-gfx] [PATCH 05/20] drm/i915: Cancel reset-engine if we couldn't find an active request

On 16/05/17 00:54, Chris Wilson wrote: On Mon, May 15, 2017 at 03:25:27PM -0700, Michel Thierry wrote: On 5/15/2017 2:47 PM, Chris Wilson wrote: On Mon, May 15, 2017 at 10:31:58PM +0100, Chris Wilson wrote: On Mon, May 15, 2017 at 02:20:01PM -0700, Michel Thierry wrote: @@ -2827,21 +2830,34

[Intel-gfx] [PATCH] drm/i915: Cancel reset-engine if we couldn't find an active request

full reset. v2: Check for request completion inside _prepare_engine, don't use ECANCELED, remove unnecessary null checks (Chris). v3: Capture active requests during reset_prepare and store it the engine hangcheck obj (Chris). Suggested-by: Chris Wilson Signed-off-by: Michel Thierry --- dr

Re: [Intel-gfx] [PATCH] drm/i915: Cancel reset-engine if we couldn't find an active request

On 17/05/17 13:52, Chris Wilson wrote: On Wed, May 17, 2017 at 01:41:34PM -0700, Michel Thierry wrote: @@ -2827,21 +2829,35 @@ int i915_gem_reset_prepare_engine(struct intel_engine_cs *engine) if (engine_stalled(engine)) { request = i915_gem_find_active_request(engine

Re: [Intel-gfx] [PATCH] drm/i915: Cancel reset-engine if we couldn't find an active request

On 5/18/2017 12:56 AM, Chris Wilson wrote: On Wed, May 17, 2017 at 06:11:06PM -0700, Michel Thierry wrote: On 17/05/17 13:52, Chris Wilson wrote: On Wed, May 17, 2017 at 01:41:34PM -0700, Michel Thierry wrote: @@ -2827,21 +2829,35 @@ int i915_gem_reset_prepare_engine(struct intel_engine_cs

[Intel-gfx] [PATCH] drm/i915: Look for active requests earlier in the reset path

t the engine hangcheck obj. v4: Rename commit, change i915_gem_reset_request to just confirm the active_request is still incomplete, instead of engine_stalled (Chris). Suggested-by: Chris Wilson Signed-off-by: Michel Thierry fixes Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_

Re: [Intel-gfx] [PATCH] drm/i915: Look for active requests earlier in the reset path

On 5/18/2017 11:22 AM, Michel Thierry wrote: fixes Signed-off-by: Michel Thierry rebase mistake ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Look for active requests earlier in the reset path

Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 14 ++-- drivers/gpu/drm/i915/i915_drv.h | 6 -- drivers/gpu/drm/i915/i915_gem.c | 38 - drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 4 files change

Re: [Intel-gfx] [PATCH] drm/i915: Look for active requests earlier in the reset path

On 5/18/2017 2:16 PM, Chris Wilson wrote: On Thu, May 18, 2017 at 02:11:15PM -0700, Michel Thierry wrote: And store the active request so that we only search for it once; this applies for reset-engine and full reset. v2: Check for request completion inside _prepare_engine, don't use ECAN

[Intel-gfx] [PATCH v8 00/20] Gen8+ engine-reset

nowledge reset _readiness_. Daniele Ceraolo Spurio (1): drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder Michel Thierry (19): drm/i915: Look for active requests earlier in the reset path drm/i915: Update i915.reset to handle engine resets drm/i915: Modify error handler for p

[Intel-gfx] [PATCH v8 01/20] drm/i915: Look for active requests earlier in the reset path

ed-by: Chris Wilson Reviewed-by: Chris Wilson (v5) Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem.c | 14 +++--- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gp

[Intel-gfx] [PATCH v8 20/20] drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs

, provide a simple debugfs entry to see the number of times media reset has happened. v2: Remove unnecessary struct_mutex, _get_dirty_page and kmap_atomic; use READ_ONCE. (Chris) Cc: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_debugfs.c | 22

[Intel-gfx] [PATCH v8 19/20] drm/i915: Watchdog timeout: Include threshold value in error state

Save the watchdog threshold (in us) as part of the engine state. v2: Only do it for gen8+ (and prevent a missing-case warn). Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 12 2 files changed, 9 insertions

[Intel-gfx] [PATCH v8 06/20] drm/i915: Export per-engine reset count info to debugfs

i915_engine_info too (Chris). Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_debugfs.c | 21 + 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v8 03/20] drm/i915: Modify error handler for per engine hang recovery

. (Chris) Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Ian Lister Signed-off-by: Tomas Elf Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 13 + drivers/gpu/drm/i915/i915_drv.h | 8 drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH v8 04/20] drm/i915: Add support for per engine reset recovery

Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 48 - drivers/gpu/drm/i915/i915_drv.h | 5 +++ drivers/gpu/drm/i915/i915_gem.c | 96 + 3 files changed, 109 insertions(+), 40 deletions(-) diff --git a/drivers

[Intel-gfx] [PATCH v8 08/20] drm/i915: Enable Engine reset and recovery support

This feature is made available only from Gen8, for previous gen devices driver uses legacy full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Tomas Elf Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_params.c | 4 ++-- 1 file changed

[Intel-gfx] [PATCH v8 10/20] drm/i915/selftests: reset engine self tests

Check that we can reset specific engines, also check the fallback to full reset if something didn't work. v2: rebase. v3: use RESET_ENGINE_IN_PROGRESS flag. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 149 +++ 1 file changed

[Intel-gfx] [PATCH v8 11/20] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder

Winiarski (v2) Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_guc_submission.c | 11 +-- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 - 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gp

[Intel-gfx] [PATCH v8 14/20] drm/i915/guc: Add support for reset engine using GuC commands

regardless of submission mode. (Chris) Signed-off-by: Arun Siluvery Signed-off-by: Jeff McGee Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c| 24 +++ drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915/i915_guc_submission.c | 48

[Intel-gfx] [PATCH v8 16/20] drm/i915: Watchdog timeout: IRQ handler for gen8+

ister Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 4 ++ drivers/gpu/drm/i915/i915_irq.c | 12 +- drivers/gpu/drm/i915/i915_reg.h | 6 +++ drivers/gpu/drm/i915/intel_hangcheck.c | 13 +-- drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH v8 07/20] drm/i915: Carry on with reset even if hw engine is not ready

has been seen at least once in CI. References: https://intel-gfx-ci.01.org/CI/Trybot_831/ Reported-by: Antonio Argenziano Cc: Mika Kuoppala Cc: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_uncore.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions

[Intel-gfx] [PATCH v8 02/20] drm/i915: Update i915.reset to handle engine resets

In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_params.c | 6

[Intel-gfx] [PATCH v8 18/20] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

e for them (magic 8-ball predicts this will change again later on, so future-proof it). (Daniele) Cc: Daniele Ceraolo Spurio Signed-off-by: Tomas Elf Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 56 +++ dri

[Intel-gfx] [PATCH v8 15/20] drm/i915: Watchdog timeout: Pass GuC shared data structure during param load

/resume/reset (Daniele). Cc: Chris Wilson Cc: Daniele Ceraolo Spurio Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_guc_submission.c | 21 ++--- drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v8 05/20] drm/i915: Add engine reset count to error state

/reset_engine/ (Chris) Define count as unsigned int (Tvrtko) Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.c | 3 +++ drivers/gpu/drm/i915/i915_drv.h | 10 ++ drivers/gpu/drm/i915

[Intel-gfx] [PATCH v8 12/20] drm/i915/guc: Provide register list to be saved/restored during engine reset

_REG_WRITE/WA_REG_WR_GUC_RESTORE). v5: Only ask guc to reapply workarounds in case of render reset (Daniele). Cc: Daniele Ceraolo Spurio Signed-off-by: Arun Siluvery Signed-off-by: Jeff McGee Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h| 3 ++ drivers/gp

[Intel-gfx] [PATCH v8 09/20] drm/i915: Add engine reset count in get-reset-stats ioctl

it is deemed useful, it can be extended to report each engine separately. v2: s/engine_reset/reset_engine/, use union in uapi to not break compatibility. Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.c | 14 +++--- include

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