The bspec has been updated with new vswing programming for RKL DP. No
data is provided for HDMI or eDP, so for now we'll continue to assume
that those are the same as TGL.
Bspec: 49291
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 42 ++--
1
- Matched HPD Pin mapping for PORT C and PORT D of CML CPU.
>
> Cc : Matt Roper
> Cc : Ville Syrjälä
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
> drivers/gpu/drm/i915/display/intel_display.c | 5 +
> drivers/g
On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> The timeouts are frequent and expected. We will complain if we retry so
> often as to lose patience and give up, so the cacophony from individual
> complaints is redundant.
>
> Signed-off-by: Chris Wilson
Reviewed
rite-only in the hardware and
will usually always read out as 0's).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel
On Thu, Dec 31, 2020 at 12:48:06AM -0800, Surendrakumar Upadhyay, TejaskumarX
wrote:
>
>
> > -Original Message-
> > From: Matt Roper
> > Sent: 31 December 2020 05:31
> > To: Surendrakumar Upadhyay, TejaskumarX
> >
> > Cc: intel
to comply with specification.
> Also as for us it do not matters if it is HDMI or DP, not checking the
> port type that HTI is using.
>
> Cc: Anusha Srivatsa
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/dis
re we try to limp along without the wa_ctx, make sure we clear those
> flags!
>
> Reported-by: Matt Roper
> Fixes: 604a8f6f1e33 ("drm/i915/lrc: Only enable per-context and per-bb
> buffers if set")
> Signed-off-by: Chris Wilson
> Cc: Matt Roper
> Cc: Tvrtk
aylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Cc: Swathi Dhanavanthri
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_d
On Fri, Jan 08, 2021 at 08:51:14PM +, Chris Wilson wrote:
> Inject a fault into lrc_init_wa_ctx() to ensure that we can tolerate a
> failure to construct the workarounds.
>
> Signed-off-by: Chris Wilson
> Cc: Matt Roper
Reviewed-by: Matt Roper
> ---
> drivers/gpu/dr
etch correct display and GT stepping for application of WAs as
> suggested by Matt Roper.
So to clarify the goal is to rename "revid" -> "stepping" because the
values like "A1," "C0," etc. are't the actual PCI revision ID, but
rather descriptions
> removed from ADLS. Disable PSR2 till we enable software/
> manual tracking.
>
> v2:
> - Add support for different ADLS SOC steppings to select
> correct GT/DISP stepping based on Bspec 53655 based on
> feedback from Matt Roper.(aswarup)
>
> v3:
> - Make displ
On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
> On Mon, 11 Jan 2021, Jani Nikula wrote:
> > On Fri, 08 Jan 2021, Matt Roper wrote:
> >> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
> >>> TGL adds another level of indirection for
c pin remapping added
> > - Added dedicated HPD pin and DDC pin handling API
> > Changes since V1 :
> > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU.
> >
> > Cc: Matt Roper
> > Cc: Jani Nikula
> > Signed-off-by: Tejas Upa
_tc()
> and return false for platforms RKL,DG1 and ADLS.(mdroper)
>
> Cc: Lucas De Marchi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Aditya Swarup
Reviewed-by: Matt Roper
> --
ant 4 before 3 and that
there's no 2.
Matt
> +
> #define _DKL_PHY1_BASE 0x168000
> #define _DKL_PHY2_BASE 0x169000
> #define _DKL_PHY3_BASE 0x16A000
> --
> 2.27.0
>
--
On Fri, Dec 04, 2020 at 05:08:32PM -0800, Aditya Swarup wrote:
> Initialize display outputs for ADL-S. ADL-S has 5 display
> outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Lucas De Marc
he aux stuff is getting really messy; we're definitely going to have to
move to a table-based approach for some of this stuff soon to keep it
from getting too out of hand.
The changes here look correct for the current style though.
Reviewed-by: Matt Roper
>
> Cc: Jani Nikula
> Cc:
lation as we cannot use existing
> icl ddc pin map due to conflict with DDI B and DDI C info.
>
> Bspec:20124
>
> v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
> depends on the PCH being used rather than the platform.(mdroper)
>
> Cc: Jani Nikula
> C
On Tue, Jan 12, 2021 at 06:24:50PM +0200, Jani Nikula wrote:
> On Mon, 11 Jan 2021, Lucas De Marchi wrote:
> > On Mon, Jan 11, 2021 at 12:57:43PM -0800, Matt Roper wrote:
> >>On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
> >>So to clarify, it looks li
; translates to
> DDI A -> DDIA
> DDI B -> USBC1
> DDI I -> USBC2
>
> For DPCLKA_CFGCR1
> DDI J -> USBC3
> DDI K -> USBC4
>
> Bspec: 50287
> Bspec: 53812
> Bspec: 53723
>
> v2: Replace I915_READ() with intel_de_read().(Jani)
>
> Cc
On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
> This was done by the following semantic patch:
Is the commit message here out-of-date? The cocci doesn't appear to
match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
IS_GEN is being replaced with a direct "==" c
_state->pipe = INVALID_PIPE;
> -
> drm_dbg_kms(&dev_priv->drm,
> "Modeset required for cdclk change\n");
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b58067a873c..1d1176d1799d 1
On Tue, Jun 01, 2021 at 11:34:39PM -0700, Lucas De Marchi wrote:
> On Tue, Jun 01, 2021 at 01:39:25PM -0700, Matt Roper wrote:
> > On Tue, Jun 01, 2021 at 12:13:17PM -0700, Lucas De Marchi wrote:
> > > On Tue, Jun 01, 2021 at 10:30:55AM -0700, Matt Roper wrote:
> > > &
On Fri, Jun 04, 2021 at 03:14:25PM -0700, Nataraj Deshpande wrote:
> Helps to fixe skia test failures on adl_p platform.
>
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed-off-by: Nataraj Deshpande
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workar
On Mon, Jun 07, 2021 at 05:20:56PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Most of the context WA are already implemented.
> Adding adl_p platform tag to reflect so.
>
> BSpec: 54369
> Cc: Matt Roper
> Cc: Aditya Swarup
> Signed-off-by: Rad
406680159:icl,ehl as an engine
> workaround")
> Cc: Mika Kuoppala
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
NAK. This patch does not do what it claims (it deletes the workaround
completely rather than reverting the original patch) and also doesn't
address the real
On Thu, Jun 10, 2021 at 10:02:13AM +0300, Stanislav Lisovskiy wrote:
> Removed excessive parenthesis and placed && on
> previous line in DBUF state checker.
>
> Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Matt Roper
Minor nit: you probably want "parentheses&q
op.org/drm/intel/-/issues/1222
Cc: Tejas Upadhyay
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e3
gt;[134]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb1/igt@i915_selftest@l...@execlists.html
>[135]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb5/igt@i915_selftest@l...@execlists.html
>
> * igt@kms_psr2_sf@cursor-plane-upda
gt;
> In ADL-P's device_info we set has_psr_hw_tracking to 0 as it would
> otherwise be enabled since it is inheriting from GEN12_FEATURES.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_pci.c | 50 ++
on the RC6 flow. Because of subslice steering disturbance w/a read is
> > > failing. By using ffs we can default steering of slice/sublice to
> > > minconfig hence w/a will pass and any warns will go away.
> > >
> > > Fixes: fb899dd8ea9c ("drm/i915: Apply Wa
e extra multicast types that will be
arriving soon.
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tejas Upadhyay
Daniele Ceraolo Spurio (1):
drm/i915: extract steered reg access to common function
Matt Roper (2):
drm/i915: Add GT support for multiple types of multicast steering
drm/i
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41
'll plug L3 bank steering
into this in the next patch, and then add additional types of multicast
registers when the support for our next upcoming platform arrives.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm
no need to complicate it with what's effectively dead code.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 in
On Tue, Jun 15, 2021 at 05:11:04AM -0400, Rodrigo Vivi wrote:
> On Tue, Jun 15, 2021 at 05:08:20AM -0400, Rodrigo Vivi wrote:
> > On Mon, Jun 14, 2021 at 08:34:32PM -0700, Matt Roper wrote:
> > > Although most of our multicast registers are replicated per-subslice, we
>
On Tue, Jun 15, 2021 at 03:48:32PM -0400, Rodrigo Vivi wrote:
> On Tue, Jun 15, 2021 at 08:30:23AM -0700, Matt Roper wrote:
> > On Tue, Jun 15, 2021 at 05:11:04AM -0400, Rodrigo Vivi wrote:
> > > On Tue, Jun 15, 2021 at 05:08:20AM -0400, Rodrigo Vivi wrote:
> > > >
rab forcewake.
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tejas Upadhyay
Cc: Rodrigo Vivi
Daniele Ceraolo Spurio (1):
drm/i915: extract steered reg access to common function
Matt Roper (2):
drm/i915: Add GT support for multiple types of multicast steering
drm/i915: Add support
no need to complicate it with what's effectively dead code.
v2:
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Use {} as table terminator. (Rodrigo)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +++
cessors
that assume forcewake is already held.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
drivers
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt
cessors
that assume forcewake is already held.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
drivers
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt
grab forcewake.
v2.1:
- Rebase
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tejas Upadhyay
Cc: Rodrigo Vivi
Daniele Ceraolo Spurio (1):
drm/i915: extract steered reg access to common function
Matt Roper (2):
drm/i915: Add GT support for multiple types of multicast steering
drm/i9
no need to complicate it with what's effectively dead code.
v2:
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Use {} as table terminator. (Rodrigo)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +++
On Wed, Jun 16, 2021 at 10:24:48AM -0400, Rodrigo Vivi wrote:
> On Tue, Jun 15, 2021 at 05:42:12PM -0700, Matt Roper wrote:
> > Although most of our multicast registers are replicated per-subslice, we
> > also have a small number of multicast registers that are replicated
> >
cessors
that assume forcewake is already held.
v3:
- Fix loop condition when iterating over steering range tables.
(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i91
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 ins
- L3bank ID goes in the subslice field, not the slice field. (CI)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/
4.1:
- Rebase
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tejas Upadhyay
Cc: Rodrigo Vivi
Daniele Ceraolo Spurio (1):
drm/i915: extract steered reg access to common function
Matt Roper (2):
drm/i915: Add GT support for multiple types of multicast steering
drm/i915: Add support
cessors
that assume forcewake is already held.
v3:
- Fix loop condition when iterating over steering range tables.
(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i91
- L3bank ID goes in the subslice field, not the slice field. (CI)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt
-tip/Patchwork_20404/shard-skl5/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
>
> * igt@prime_vgem@sync@vcs0:
> - shard-skl: [INCOMPLETE][130] ([i915#409]) -> [PASS][131]
>[130]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-skl6/igt@p
DRM_10240/shard-skl10/igt@run...@aborted.html
>[142]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-skl10/igt@run...@aborted.html
>[143]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-skl6/igt@run...@aborted.html
>[144]:
> https:/
ed.html
>[139]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-kbl7/igt@run...@aborted.html
> - shard-iclb: ([FAIL][140], [FAIL][141], [FAIL][142])
> ([i915#2426] / [i915#3002] / [i915#409]) -> ([FAIL][143], [FAIL][144],
> [FAIL][145], [FAIL][146
of multi-tile is not covered by this patch
series and will show up in future work.
Daniele Ceraolo Spurio (2):
drm/i915: split general MMIO setup from per-GT uncore init
drm/i915: Initial support for per-tile uncore
Matt Roper (1):
drm/i915: Restructure probe to handle multi-tile platforms
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 9 -
drivers/gpu/drm/i915/intel_uncore.c
ded to iterate over the
GTs and will be used by upcoming patches that convert various parts of
the driver to be multi-gt aware.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 74 --
drivers/gpu/drm/i915/gt/intel_gt.h
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drive
t now we're still
passing tile 0 everywhere, but in later patches we'll start actually
passing the correct tile.
Signed-off-by: Paulo Zanoni
Co-authored-by: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/
From: Venkata Sandeep Dhanalakota
Iterate for_each_gt during release to support multi-tile
devices.
Cc: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
From: Daniele Ceraolo Spurio
Initialization and suspend/resume is replicated per-tile.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm
-tile platforms. Subsequent patches will convert other parts of
the interrupt handling flow.
Cc: Stuart Summers
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 31 ---
1 file changed, 16
From: Michal Wajdeczko
Update CT debug macros by including tile ID in all messages.
Cc: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
Bspec: 33407
Original-author: Abdiel
niele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 45
drivers/gpu/drm/i915/gt/intel_gt.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 9 -
drivers/gpu/drm/i915/gt/intel_gt_types.h
From: Paulo Zanoni
Loop through all the tiles when initializing and resetting interrupts.
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
v2:
- Include some additional refact
On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote:
> From: Paulo Zanoni
>
> The first step of interrupt handling is to read a tile0 register that
> tells us in which tile the interrupt happened; we can then we read the
> usual interrupt registers from the appropriate
MORY_FREQ_MULTIPLIER_HZ, 1000);
I'm not sure SKL_MEMORY_FREQ_MULTIPLIER_HZ is correct anymore either.
If I'm reading the register description correctly, it appears the value
is now given in units of 133.33 MHz instead of the old 266.66.
Matt
>
> if (dram_info->num_channels * mem_freq_khz == 0) {
> drm_info(&i915->drm,
> --
> 2.33.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
On Tue, Oct 12, 2021 at 02:23:27PM -0700, Souza, Jose wrote:
> On Tue, 2021-10-12 at 14:20 -0700, Matt Roper wrote:
> > On Fri, Oct 08, 2021 at 01:58:55PM -0700, José Roberto de Souza wrote:
> > > All display 9 and display 10 platforms has only 4 bits for the memory
> > &g
On Fri, Oct 08, 2021 at 12:49:57PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> > The I915_TILING_* definitions in the uapi header are intended solely for
> > tiling modes that are visible to the old de-tiling fence ioctls. Since
>
ds to represent tiling format should either
rely on framebuffer modifiers (as the display code does) or use some
kind of non-uapi enum (as the GEM blt selftest now does).
References: https://patchwork.freedesktop.org/patch/456656/?series=95308
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
include
ctive_channels, but none of those
variables are ever used for anything except a needless zero-check.
Matt
> Cc: Yakui Zhao
> Cc: Matt Roper
> Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
> Signed-off-by: José Roberto de Souza
&
the appropriate frequency multiplier while this code is stuck
> with a fixed multiplier.
>
> So here dropping it as whole.
>
> v2:
> - Also remove memory frequency calculation for gen9 LP platforms
>
> Cc: Yakui Zhao
> Cc: Matt Roper
> Fixes: f8112cb9574b ("drm/
ice
interrupt register; we always access it via tile0's MMIO . So in this
case we do want to do this outside the loop since it's not a per-tile
operation.
We could probably simplify the dev_priv->gt.uncore parameter to just
dev_priv->uncore to make this more obvious.
Matt
>
> Andi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
purio
Cc: Matthew Auld
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 46
drivers/gpu/drm/i915/gt/intel_gt.h
t now we're still
passing tile 0 everywhere, but in later patches we'll start actually
passing the correct tile.
Signed-off-by: Paulo Zanoni
Co-authored-by: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Matt Roper
Reviewed-by: Lucas De M
proper tile's master_ctl value is used.
Cc: Stuart Summers
Cc: Lucas De Marchi
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 41 ++---
1 file changed, 23 insertions(+), 18 deletions(-)
ardown.
Cc: Lucas De Marchi
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 57 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 6 +++
drivers/gpu/drm/i915/gt/intel_gt_t
From: Daniele Ceraolo Spurio
Initialization and suspend/resume is replicated per-tile.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_
setup.
- Fix handling of display and GSE interrupts (our current multi-tile
platforms don't have display, but we can't count on that being true
in the future).
Daniele Ceraolo Spurio (2):
drm/i915: split general MMIO setup from per-GT uncore init
drm/i915: Initial support for per
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c
From: Michal Wajdeczko
Update CT debug macros by including tile ID in all messages.
Cc: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers
From: Paulo Zanoni
Loop through all the tiles when initializing and resetting interrupts.
v2:
- Access tile0 registers through dev_priv->uncore rather than
dev_priv->gt.uncore for clarity.
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Revie
e).
Bspec: 33407
Original-author: Abdiel Janulgue
Signed-off-by: Tvrtko Ursulin
Co-authored-by: Matt Roper
Signed-off-by: Matt Roper
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Paulo Zanoni
Cc: Andi Shyti
Signed-off-by: Paulo Zanoni
Signed-off-by: Daniele Cera
On Mon, Sep 13, 2021 at 11:19:09AM -0700, José Roberto de Souza wrote:
> New DG1 PCI id.
>
> BSpec: 44463
> Cc: Caz Yokoyama
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> include/drm/i915_pciids.h | 3 ++-
> 1 file
32fe2f14a7 ("drm/i915/adl_p: Update memory bandwidth parameters")
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/d
he new derating value only for ADL-P(MattR)
>
> Fixes: 4d32fe2f14a7 ("drm/i915/adl_p: Update memory bandwidth parameters")
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 19 +
S][134]
>[133]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-apl7/igt@kms_flip@flip-vs-susp...@b-dp1.html
>[134]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-apl7/igt@kms_flip@flip-vs-susp...@b-dp1.html
>
> * igt@kms_flip@flip-vs-suspend@c-dp1:
> - shard-kbl: [INCOMPLETE][135] ([i915#636]) -> [PASS][136]
>[135]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-kbl2/igt@kms_flip@flip-vs-susp...@c-dp1.html
>[136]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-kbl4/igt@kms_flip@flip-vs-susp...@c-dp1.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
> - shard-skl: [FAIL][137] ([i915#2122]) -> [PASS][138]
>[137]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html
>[138]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
> - shard-iclb: [SKIP][139] -> [PASS][140]
>[139]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-iclb2/igt@kms_flip_scaled_...@flip-32bpp-ytileccs-to-64bpp-ytile.html
>[140]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-iclb6/igt@kms_flip_scaled_...@flip-32bpp-ytileccs-to-64bpp-ytile.html
>
> * igt@kms_frontbuffer_tracking@basic:
> - {shard-rkl}:[SKIP][141] ([i915#1849]) -> [PASS][142] +50
> similar issues
>[141]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-rkl-1/igt@kms_frontbuffer_track...@basic.html
>[142]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-rkl-6/igt@kms_frontbuffer_track...@basic.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
> - {shard-rkl}:[SKIP][143] ([i915#3558]) -> [PASS][144] +5 similar
> issues
>[143]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-rkl-2/igt@kms_plane@plane-panning-bottom-ri
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_gt_pm_register(gt, root);
> > + intel_gt_pm_register_debugfs(gt, root);
>
> This is one case I usually don't know what convention to follow since it
> changes in different places.
>
> I did it like _register_debugfs because of calls like
> intel_gt_init_scratch(), xxx_init_hw, etc. However here I see that just
> below we have intel_sseu_debugfs_register(), so maybe I should consider
> debugfs as part of the namespace?
I like *_debugfs_register slightly better than *_register_debugfs
because to me we're not registering debugfs itself, we're performing
debugfs' register operation on some files. But I don't really have a
strong feeling either way. Whichever way you decide,
Reviewed-by: Matt Roper
for the series.
Matt
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
> V2:
> Changed 'i915_mocs_index_gt' to anonymous structure.
>
> Cc: CQ Tang
> Reviewed-by: Matt Roper
> Signed-off-by: Ayaz A Siddiqui
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 4
> drivers/gpu/drm
[PASS][131] +10 similar issues
>[130]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-rkl-2/igt@kms_cursor_...@pipe-b-cursor-128x128-sliding.html
>[131]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-rkl-6/igt@kms_cursor_...@pipe-b-cursor-128x128-sliding.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-skl: [INCOMPLETE][132] ([i915#300]) -> [PASS][133]
>[132]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html
>[133]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html
> - shard-kbl: [DMESG-WARN][134] ([i915#180]) -> [PASS][135] +5
> similar issues
>[134]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-kbl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html
>[135]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-kbl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
> - {shard-rkl}:[SKIP][136] ([fdo#111825] / [i915#4070]) ->
> [PASS][137] +3 similar issues
>[136]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-rkl-2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
>[137]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-rkl-6/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-skl: [FAIL][138] ([i915#2346] / [i915#533]) ->
> [PASS][139]
>[138]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
>[139]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled:
> - {shard-rkl}:[SKIP][140] ([fdo#111314]) -> [PA
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
> [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
> [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
> [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
> [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
> [i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828
> [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
> [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
> [i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
> [i915#3288]: https://gitlab.freedesktop.org/drm/intel/issues/3288
> [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
> [i915#3343]: https://gitlab.freedesktop.org/drm/intel/issues/3343
> [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
> [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
> [i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648
> [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#456]: https://gitlab.freedeskt
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21051/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
On Thu, Sep 16, 2021 at 11:57:36AM +0530, Ayaz A Siddiqui wrote:
> Adding missing "intel_" prefix in set_mocs_index().
>
> Fixes: b62aa57e3c78 ("drm/i915/gt: Add support of mocs propagation")
> Cc: Matt Roper
> Signed-off-by: Ayaz A Siddiqui
Thanks for fixin
> Missing(3): fi-bdw-samus fi-bsw-cyan bat-dg1-6
>
>
> Build changes
> -
>
> * Linux: CI_DRM_10599 -> Patchwork_21077
>
> CI-20190529: 20190529
> CI_DRM_10599: 7517e1f3124126ca9f24627f9494330d155e5ff6 @
> git://anongit.freedesktop.org/gfx-
Xe_HP adds some new fuse bits to indicate whether an SFC unit is fused
off. We should utilize these when initializing VD/VE SFC access and
also when capturing/dumping SFC_DONE for the error state.
Matt Roper (2):
drm/i915/xehp: Check new fuse bits for SFC availability
drm/i915: Check SFC
On Xe_HP and beyond the SFC unit may be fused off, even if the
corresponding media engines are present. Check the SFC-specific fusing
before trying to dump the SFC_DONE instances.
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_gpu_error.c | 6 --
1 file
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