On Tue, Oct 12, 2021 at 05:24:55PM -0700, José Roberto de Souza wrote:
> This memory frequency calculated is only used to check if it is zero,
> what is not useful as it will never actually be zero.
>
> Also the calculation is wrong, we should be checking other bit to
> select the appropriate frequency multiplier while this code is stuck
> with a fixed multiplier.
>
> So here dropping it as whole.
I think we can do similar cleanup in bxt_get_dram_info() too. The value
of BXT_P_CR_MC_BIOS_REQ_0_0_0 that we read is used to obtain
mem_freq_khz and dram_channels/num_active_channels, but none of those
variables are ever used for anything except a needless zero-check.
Matt
> Cc: Yakui Zhao <yakui.z...@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> drivers/gpu/drm/i915/intel_dram.c | 12 ------------
> 2 files changed, 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c3..03b6c505249dc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11145,9 +11145,7 @@ enum skl_power_gate {
> #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
> #define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
>
> -#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
> #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB +
> 0x5E04)
> -#define SKL_REQ_DATA_MASK (0xF << 0)
> #define DG1_GEAR_TYPE REG_BIT(16)
>
> #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 30a0cab5eff46..31933b1e7277b 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -244,7 +244,6 @@ static int
> skl_get_dram_info(struct drm_i915_private *i915)
> {
> struct dram_info *dram_info = &i915->dram_info;
> - u32 mem_freq_khz, val;
> int ret;
>
> dram_info->type = skl_get_dram_type(i915);
> @@ -255,17 +254,6 @@ skl_get_dram_info(struct drm_i915_private *i915)
> if (ret)
> return ret;
>
> - val = intel_uncore_read(&i915->uncore,
> - SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
> - mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> - SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> -
> - if (dram_info->num_channels * mem_freq_khz == 0) {
> - drm_info(&i915->drm,
> - "Couldn't get system memory bandwidth\n");
> - return -EINVAL;
> - }
> -
> return 0;
> }
>
> --
> 2.33.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
