[Intel-gfx] [PATCH 1/2] drm/i915: make sure south port interrupts are enabled properly

We were apparently relying on the defaults on BDW, which resulted in no hotplug or AUX interrupts. References: https://bugs.freedesktop.org/show_bug.cgi?id=72834 References: https://bugs.freedesktop.org/show_bug.cgi?id=72833 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_irq.c | 4

[Intel-gfx] [PATCH 2/2] drm/i915: get proper hwrawclk freq on BDW

We need to read out the CDclk to calculate the DP aux divider correctly. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7df5085..4ac1da5 100644 --- a

Re: [Intel-gfx] [PATCH 1/2] drm/i915: make sure south port interrupts are enabled properly

On Fri, 10 Jan 2014 13:02:20 -0800 Jesse Barnes wrote: > We were apparently relying on the defaults on BDW, which resulted in no > hotplug or AUX interrupts. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=72834 > References: https://bugs.freedesktop.org/show_b

[Intel-gfx] [PATCH] drm/i915/bdw: make sure south port interrupts are enabled properly v2

: https://bugs.freedesktop.org/show_bug.cgi?id=72833 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_irq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 261254a..69b0b71 100644 --- a/drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/i915/bdw: make sure south port interrupts are enabled properly v2

On Fri, 10 Jan 2014 19:17:02 -0200 Paulo Zanoni wrote: > 2014/1/10 Jesse Barnes : > > We were apparently relying on the defaults on BDW, which resulted in no > > hotplug or AUX interrupts. So be sure to call the ibx_irq_preinstall to > > enable all interrupts. > > >

Re: [Intel-gfx] [PATCH] drm/i915: fastboot support for HSW and BDW

On Mon, 13 Jan 2014 17:55:27 -0200 Paulo Zanoni wrote: > 2014/1/8 Jesse Barnes : > > No idea if this is correct or not, all the WRPLL programming is new to > > me. Paulo, can you take a look? At least it doesn't complain on my BDW > > here... > > As a side

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.

f we need to bring the gfx clocks up (which makes sense) then I guess we need this. I'm not sure about the wait on the punit though; that could end up penalizing us in bursty workloads, since the punit can take quite some time to update the freq, but I don't actually see a wait here? Also, is the 500ms timeout really required for the gfx clock? That's a long time to potentially hold the mutex and delay any clock boosting or other activity... -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

> + dev_priv->rps.rp_down_masked = false; > + } I've looked at this too much and confused myself. It looks like the old logic of the delay numbers being in reverse order has changed (or maybe that was just ILK?)... so I guess the above is ok (I

[Intel-gfx] [PATCH] drm/i915/bdw: remove preliminary_hw_support flag from BDW

It ought to work ok in 3.14. We have some fun stuff coming after that, but all the basics are in place now and seem relatively stable. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers

Re: [Intel-gfx] [PATCH] i915: send D1 opregion notification

dw/vlv and > all the further stuff? Doc # would help too, even if it's CDI or internal only... I don't know where to find this info, or if I did I've forgotten. Thanks, -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: fastboot support for HSW and BDW

On Mon, 13 Jan 2014 17:55:27 -0200 Paulo Zanoni wrote: > 2014/1/8 Jesse Barnes : > > No idea if this is correct or not, all the WRPLL programming is new to > > me. Paulo, can you take a look? At least it doesn't complain on my BDW > > here... > > As a side

Re: [Intel-gfx] [PATCH] i915: send D1 opregion notification

On Tue, 14 Jan 2014 15:06:46 -0800 Kristen Carlson Accardi wrote: > On Tue, 14 Jan 2014 11:19:44 -0800 > Jesse Barnes wrote: > > > On Tue, 14 Jan 2014 10:26:02 +0100 > > Daniel Vetter wrote: > > > > > On Mon, Jan 13, 2014 at 01:32:45PM -0800, Kriste

Re: [Intel-gfx] [PATCH 3/6] drm/i915: reset eDP timestamps on resume

et_vco(struct drm_i915_private *dev_priv); > +void intel_encoder_resume(struct drm_device *dev); > > /* intel_dp.c */ > void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); > @@ -734,6 +736,7 @@ void ironlake_edp_panel_vdd_off(struct intel_dp > *in

Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove the vblank_wait hack from HSW+

vblank before returning to avoid strange things > - * happening. > - */ > - intel_wait_for_vblank(dev, intel_crtc->pipe); > } > > static void ironlake_pfit_disable(struct intel_crtc *crtc) Yeah, really seems like this is taken care of by the earlier bits... Re

Re: [Intel-gfx] [PATCH 2/3] drm/i915: don't wait for vblank after enabling pipe on HSW

false); > > if (intel_crtc->config.has_pch_encoder) > lpt_pch_enable(crtc); Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/3] drm/i915: add wait_for_vblank argument to intel_enable_pipe

/* The fixup needs to happen before cursor is enabled */ Looks fine, though I echo Jani's comment. Might be better to have an explicitly named intel_enable_pipe_wait variant to make the code more readable (likewise for DSI and PCH probably, if we don't need every combination), but that can be a separate cleanup. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 3/3] drm/i915: always check clocks when comparing pipe configs

Now that we have DDI support, we can check these all the time. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH 2/3] drm/i915: clock readout support for DDI

Read out and calculate the port and pixel clocks on DDI configs as well. This means we have to grab the DP divider values and look at the port mapping to figure out which clock select reg to read out. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 6 drivers/gpu

[Intel-gfx] [PATCH 1/3] drm/i915: get basic encoder state before reading CRTC state

In DDI configs, we need to get the encoder to CRTC mapping early on so we can read out and calculate the clock state correctly, as it depends on the port. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 59 +++- 1 file changed, 44

Re: [Intel-gfx] [PATCH 1/3] drm/i915: get basic encoder state before reading CRTC state

On Sat, 18 Jan 2014 16:01:06 +0200 Ville Syrjälä wrote: > On Fri, Jan 17, 2014 at 01:16:56PM -0800, Jesse Barnes wrote: > > In DDI configs, we need to get the encoder to CRTC mapping early on so > > we can read out and calculate the clock state correctly, as it depends

[Intel-gfx] [PATCH 2/2] drm/i915: always check clocks when comparing pipe configs

Now that we have DDI support, we can check these all the time. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index

[Intel-gfx] [PATCH 1/2] drm/i915: clock readout support for DDI v2

Read out and calculate the port and pixel clocks on DDI configs as well. This means we have to grab the DP divider values and look at the port mapping to figure out which clock select reg to read out. v2: do the work from ddi_get_config (Ville) Signed-off-by: Jesse Barnes --- drivers/gpu/drm

[Intel-gfx] [PATCH 1/2] drm: expose subpixel order name routine

Just like we have for connector type etc. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_crtc.c | 20 include/drm/drm_crtc.h | 1 + 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 266a01d..3982dd9

[Intel-gfx] [PATCH 2/2] drm/i915: add a display info file to debugfs

Can be expanded up on to include all sorts of things (HDMI infoframe data, more DP status, etc). Should be useful for bug reports to get a baseline on the display config and info. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_debugfs.c | 155

Re: [Intel-gfx] [PATCH 1/2] drm/i915: clock readout support for DDI v2

&pipe_config->dp_m_n); > > else > .crtc_clock = link_clock; // or port_clock if you take my suggestion > above Fixed. > > + intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, > > +

[Intel-gfx] [PATCH] drm/i915: clock readout support for DDI v3

additional SPLL freqs (Ville) clean up port/crtc clock calc (Ville) fix up crtc_clock conditionals (Ville) drop superfluous dp_get_m_n from get_config (Ville) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_ddi.c | 92

Re: [Intel-gfx] [PATCH 1/2] drm: expose subpixel order name routine

On Tue, 21 Jan 2014 09:05:04 + Chris Wilson wrote: > On Mon, Jan 20, 2014 at 03:54:59PM -0800, Jesse Barnes wrote: > > Just like we have for connector type etc. > > Then we might as well take a similar defensive approach if we want to > expand the number of contexts we ca

[Intel-gfx] [PATCH] drm: expose subpixel order name routine v2

Just like we have for connector type etc. v2: just return the string directly to avoid repeating the mistakes of the past (Chris) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/drm_crtc.c | 16 include/drm/drm_crtc.h | 1 + 2 files changed, 17 insertions(+) diff

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: WA for Turbo and RC6 to work together.

st code makes sense, so you'd have to port those changes from the gen6_pm_rps_work() from Chris and measure again... Thanks, -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: WA for Turbo and RC6 to work together.

On Wed, 22 Jan 2014 22:07:53 +0530 "S, Deepak" wrote: > > > On 1/22/2014 10:04 PM, Jesse Barnes wrote: > > On Tue, 21 Jan 2014 17:18:59 +0200 > > Ville Syrjälä wrote: > > > >> On Mon, Jan 20, 2014 at 06:40:26PM +0530, deepa...@intel.com wro

Re: [Intel-gfx] [PATCH] drm/i915: fix HDMI clock readout on Haswell

(p * r); > } > > static void intel_ddi_clock_get(struct intel_encoder *encoder, Yep, looks like units fail. And I failed to replace LC_FREQ with refclk when I added the WRPLL refclk fetching... I'll post an updated patch with both fixed. Thanks, -- Jesse Barnes, Intel Open Source T

[Intel-gfx] [PATCH] drm/i915: fix WRPLL clock calculation

Forgot to convert to using the refclk variable when I added refclk readout support, and Paulo noticed the resulting calculation was off due to the way p & r are stored. Reported-by: Paulo Zanoni Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_ddi.c | 3 ++- 1 file change

Re: [Intel-gfx] [PATCH] drm/i915: Always pin the default context

nter_do_call+0x12/0x28 > [ 161.003505] Code: 0f b6 4d f3 8d 51 0f 83 e1 f0 83 e2 0f 09 d1 84 d2 88 48 > 54 75 07 80 a7 91 00 00 00 7f 83 c4 04 5b 5e 5f 5d c3 8d b6 00 00 00 00 <0f> > 0b 8d b6 00 00 00 00 55 89 e5 57 56 53 83 ec 64 3e 8d 74 26 > [ 161.003586] EIP: [] i915_gem_o

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Fix the offset issue for the stolen GEM objects

t; } > > sg = st->sgl; > - sg->offset = offset; > + sg->offset = 0; > sg->length = size; > > sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset; Let's get this upstream and cc stable. Reviewed-by: Jesse Barnes -- J

Re: [Intel-gfx] [PATCH 1/2] drm/i915: move intel_hrawclk() to intel_display.c

intel_dp, > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 46aea6c..9c5e984 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -626,6 +626,7 @@ void intel_ddi_get_config(struc

Re: [Intel-gfx] [PATCH 2/2] drm/i915: add a display info file to debugfs

On Thu, 30 Jan 2014 19:58:43 -0200 Rodrigo Vivi wrote: > > + seq_printf(m, ", mode:\n"); > > + seq_printf(m, "\t\t%d:\"%s\" %d %d %d %d %d %d %d > > %d %d %d 0x%x 0x%x\n", > > + mode->base.id, mode->name, > > +

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v7

On Sat, 14 Dec 2013 12:36:30 +0100 Daniel Vetter wrote: > On Sat, Dec 14, 2013 at 12:13:45PM +0100, Daniel Vetter wrote: > > On Thu, Dec 12, 2013 at 12:41:54PM -0800, Jesse Barnes wrote: > > > + ifbdev->helper.funcs->initial_config = intel_fb_initial_config; >

Re: [Intel-gfx] [PATCH] [RFC] drm/i915: Generate a hang error code

s will actually look at) we can probably avoid some of the "me too" action we see on general GPU hangs. Having PID, comm, and some sort of hang signature are all good steps in that direction imo. Acked-by: Jesse Barnes Jesse __

Re: [Intel-gfx] [PATCH 1/7] drm/i915: vlv: don't unmask IIR[DISPLAY_PIPE_A/B_VBLANK] interrupt

32 imr; > > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > i915_disable_pipestat(dev_priv, pipe, > PIPE_START_VBLANK_INTERRUPT_ENABLE); > - imr = I915_READ(VLV_IMR); > - if (pipe == PIPE_A)

Re: [Intel-gfx] [PATCH 2/7] drm/i915: factor out valleyview_pipestat_irq_handler

e(pipe)); > - } > + valleyview_pipestat_irq_handler(dev, iir); > > /* Consume port. Then clear IIR or we'll miss events */ > if (iir & I915_DISPLAY_PORT_INTERRUPT) { > @@ -1543,8 +1553,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void

Re: [Intel-gfx] [PATCH 3/7] drm/i915: vlv: s/spin_lock_irqsave/spin_lock/ in irq handler

> - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > + spin_unlock(&dev_priv->irq_lock); > > for_each_pipe(pipe) { > if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) I guess we don't have to worry about new interr

Re: [Intel-gfx] [PATCH 4/7] drm/i915: unify FLIP_DONE macro names

5) > +#define PLANEB_FLIP_DONE_INT_EN(1<<24) > #define PIPEA_LINE_COMPARE_INT_EN (1<<21) > #define PIPEA_HLINE_INT_EN (1<<20) > #define PIPEA_VBLANK_INT_EN (1<<19) > -#define SPRITEB_FLIPDONE_INT_EN

Re: [Intel-gfx] [PATCH 5/7] drm/i915: pass status instead of enable flags to i915_enable_pipestat

PIPE_HOTPLUG_INTERRUPT_ENABLE | > - PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); > + PIPE_HOTPLUG_INTERRUPT_STATUS | > + PIPE_HOTPLUG_TV_INTERRUPT_STATUS); >

Re: [Intel-gfx] [PATCH] drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl

On Tue, 4 Feb 2014 11:56:47 +0100 Daniel Vetter wrote: > On Mon, Feb 03, 2014 at 03:28:37PM +, Tvrtko Ursulin wrote: > > > > On 01/29/2014 08:34 PM, Daniel Vetter wrote: > > >Actually I've found something else to complain about: > > > > > >On Tue, Jan 28, 2014 at 2:16 PM, Chris Wilson > >

Re: [Intel-gfx] [PATCH] [RFC] drm/i915: Generate a hang error code

On Wed, 5 Feb 2014 16:15:02 +0100 Daniel Vetter wrote: > On Wed, Feb 05, 2014 at 02:59:08PM +0000, Jesse Barnes wrote: > > On Tue, 4 Feb 2014 12:18:55 + > > Ben Widawsky wrote: > > > > > We get a large number of bugs which have a, "hey I have that too&qu

[Intel-gfx] [PATCH 5/6] drm/i915: allow re-use BIOS connector config for initial fbdev config

. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_fbdev.c | 91 1 file changed, 91 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index fb07ba6..8ce3405 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/6] drm/i915: get_plane_config for i9xx v9

: split out init ordering changes (Daniel) don't fetch config if !CONFIG_FB v8: use proper height in get_plane_config (Chris) v9: fix CONFIG_FB check for modular configs (Jani) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h |3 + drivers/gpu/drm/i915/intel_disp

[Intel-gfx] [PATCH 6/6] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v9

buffer if preallocated (Chris) alloc ifbdev up front and pass to init_bios (Chris) check for bad ifbdev in restore_mode too (Chris) v9: fix up !fastboot bpp setting (Jesse) fix up !fastboot helper alloc (Jesse) make sure BIOS fb is sufficient for biggest active pipe (Jesse) Signed-off-

Re: [Intel-gfx] [PATCH] drm/i915: Record pid/comm of hanging task

On Wed, 5 Feb 2014 16:40:41 + Chris Wilson wrote: > After finding the guilty batch and request, we can use it to find the > process that submitted the batch and then add the culprit into the error > state. > > This is a slightly different approach from Ben's in that instead of > adding the

[Intel-gfx] [PATCH 3/6] drm/i915: get_plane_config support for ILK+

This should allow BIOS fb inheritance to work on ILK+ machines too. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 92 ++ 1 file changed, 92 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/6] drm/i915: split aligned height calculation out

For use by get_plane_config. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4d4a0d9..e2f1db6 100644

[Intel-gfx] [PATCH 4/6] drm/i915: alloc intel_fb in the intel_fbdev struct

Allocate this struct instead, so we can re-use another allocated elsewhere if needed. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c |4 ++-- drivers/gpu/drm/i915/intel_drv.h |2 +- drivers/gpu/drm/i915/intel_fbdev.c | 27 +++ 3

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v9

On Wed, 5 Feb 2014 18:14:15 + Chris Wilson wrote: > On Wed, Feb 05, 2014 at 05:30:48PM +0000, Jesse Barnes wrote: > > +static bool intel_fbdev_init_bios(struct drm_device *dev, > > +struct intel_fbdev *ifbdev) > > +{ > > + struct i

Re: [Intel-gfx] [PATCH 1/3] RFM drm/i915: Boost RPS frequency for CPU stalls

6_set_rps(dev_priv->dev, dev_priv->rps.max_delay); > + mutex_unlock(&dev_priv->rps.hw_lock); > + } > + > /* Record current time in case interrupted by signal, or wedged * */ > getrawmonotonic(&before); > -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] How will Gfx driver support runtime PM on Haswell?

ver? Paulo was going to test this on top of his PC8+ patchset. AFAFIK the only thing we need to do is put the device into D3 when we enter the PC8+ mode, and the BIOS will do the right thing (when we use the OpRegion stuff Jani did anyway). Paulo, are you still out celebrating the PC8 bits or have

Re: [Intel-gfx] How will Gfx driver support runtime PM on Haswell?

On Fri, 23 Aug 2013 13:49:57 -0300 Paulo Zanoni wrote: > 2013/8/22 Jesse Barnes : > > On Wed, 21 Aug 2013 15:29:17 + > > "Lin, Mengdong" wrote: > > > >> Hi Ben, > >> > >> How will Gfx driver support runtime PM on Haswell? Will the G

Re: [Intel-gfx] [PATCH] drm/i915: Restore the preliminary HW check.

structure, and also > change the error from DRM_ERROR->DRM_INFO. I hate this param. But this looks like a better way to do it than the ID list we had in pci_probe before. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center

[Intel-gfx] [PATCH] drm/i915/vlv: re-enable hotplug detect based probing on VLV/BYT

Works nowadays. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_crt.c |3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index ea9022e..f5f89c3 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu

[Intel-gfx] [PATCH] drm/i915/vlv: disable rc6p and rc6pp residency reporting on BYT

Unsupported; we just do RC6. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_sysfs.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index c8c4112..a813905 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c

Re: [Intel-gfx] [PATCH] drm/i915/vlv: disable rc6p and rc6pp residency reporting on BYT

On Wed, 11 Sep 2013 22:54:54 +0100 Chris Wilson wrote: > On Wed, Sep 11, 2013 at 01:43:20PM -0700, Jesse Barnes wrote: > > Unsupported; we just do RC6. > > Same for Haswell, right? Dunno... didn't check. Paulo? -- Jesse Barnes, Intel Open Sour

Re: [Intel-gfx] [PATCH] drm/i915/vlv: disable rc6p and rc6pp residency reporting on BYT

On Thu, 12 Sep 2013 22:38:41 +0200 Daniel Vetter wrote: > On Wed, Sep 11, 2013 at 01:43:20PM -0700, Jesse Barnes wrote: > > Unsupported; we just do RC6. > > > > Signed-off-by: Jesse Barnes > > You only change the sysfs stuff here, so I wondered where the hunk for &

[Intel-gfx] [PATCH] Revert "drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2"

This reverts commit 65ce4bf5a15fcd4d15898be47795d0550eb2325c. --- drivers/gpu/drm/i915/intel_display.c | 20 +--- drivers/gpu/drm/i915/intel_dp.c | 10 +- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drive

Re: [Intel-gfx] [PATCH] Revert "drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2"

On Fri, 13 Sep 2013 17:27:54 -0700 Jesse Barnes wrote: > This reverts commit 65ce4bf5a15fcd4d15898be47795d0550eb2325c. Found this was breaking eDP for me with -nightly as of today on Baley Bay boards. Chris, can you verify this on your system too? I'm working on getting a new one

Re: [Intel-gfx] [PATCH] Revert "drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2"

Yeah, haven't looked too hard at the changes, hopefully the fixed numbers can work across all out BYT SKUs. I'll test more when I get my new platform next week. Jesse Barnes, Intel Open Source Technology Center Original message From: Daniel Vetter Date: 14/09/201

[Intel-gfx] [PATCH] drm/i915/vlv: honor i915_enable_rc6 boot param on VLV

Disabling it isn't really an option on these platforms, but having it available for power comparisons is useful. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c |7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_p

[Intel-gfx] [PATCH 1/2] drm/i915: only get clock for active pipes

Otherwise the pixel_multiplier may not be set, and who knows what else in the future. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/2] drm/i915/vlv: add VLV specific clock_get function

Calculation is a little different than other platforms. References: https://bugs.freedesktop.org/show_bug.cgi?id=67345 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 30 +- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a

[Intel-gfx] [PATCH] drm/i915/vlv: add VLV specific clock_get function v2

Calculation is a little different than other platforms. v2: update to use port_clock instead rebase on top of Ville's changes References: https://bugs.freedesktop.org/show_bug.cgi?id=67345 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c |

[Intel-gfx] [PATCH] drm/i915/vlv: add VLV specific clock_get function v3

ned-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 33 - 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7eecf37..e5c9c1c 100644 --- a/drivers/gp

Re: [Intel-gfx] [PATCH 17/20] drm/i915: Use adjusted_mode in the fastboot hack to disable pfit

nd pfit state, we'll end up with a big fb scanned out into the wrong sized surface. To fix this properly, we need to hoist the checks up into compute_mode_changes (or above), check the actual pfit state and whether the platform allows pfit disable with pipe active, and only then update the pipesrc and pfit state, even on the flip path. On top of that, other state like info frames and audio state needs to be tracked and preserved for fastboot as applicable. Then we can remove the parameter hacks. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/vlv: hack to init backlight regs if BIOS fails to do so

to use something (in this case the value my BIOS normally programs with just the internal display enabled). Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_panel.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu

Re: [Intel-gfx] [PATCH] drm/i915/vlv: hack to init backlight regs if BIOS fails to do so

On Wed, 25 Sep 2013 20:18:39 +0300 Jani Nikula wrote: > On Wed, 25 Sep 2013, Jesse Barnes wrote: > > Still digging up the actual VBT info for this, but wanted to get this > > out there for testing, or in case others are also bugged by this. > > I had a look at this a fe

Re: [Intel-gfx] [PATCH] drm/i915/vlv: add VLV specific clock_get function v3

On Mon, 23 Sep 2013 21:01:44 +0300 Ville Syrjälä wrote: > On Fri, Sep 20, 2013 at 11:29:32AM -0700, Jesse Barnes wrote: > > Calculation is a little different than other platforms. > > > > v2: update to use port_clock instead > > rebase on top of Ville'

Re: [Intel-gfx] [PATCH] drm/i915/vlv: hack to init backlight regs if BIOS fails to do so

On Wed, 25 Sep 2013 20:18:39 +0300 Jani Nikula wrote: > On Wed, 25 Sep 2013, Jesse Barnes wrote: > > Still digging up the actual VBT info for this, but wanted to get this > > out there for testing, or in case others are also bugged by this. > > I had a look at this a fe

[Intel-gfx] [PATCH] drm/i915/vlv: hack to init backlight regs if BIOS fails to do so v2

to use something (in this case the value my BIOS normally programs with just the internal display enabled). v2: fix masking and magic value in read_blc_pwm_ctl (Jani) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_panel.c | 17 + 1 file changed, 17 insertions(+) diff

[Intel-gfx] [PATCH] drm/i915/vlv: fix up broken precision in vlv_crtc_clock_get

From: Chris Wilson With some divider values we end up with the wrong result. So remove the intermediates (like Ville suggested in the first place) to get the right answer. Signed-off-by: Chris Wilson Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 8 +++- 1 file

[Intel-gfx] [PATCH 2/2] drm/i915/vlv: use correct units for rc6 residency

We need to use the clock control reg to figure out how many CZ clks are in 30ns and use that as the basis for our RC6 residency calculations. References: https://bugs.freedesktop.org/show_bug.cgi?id=69692 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu

[Intel-gfx] [PATCH 1/2] drm/i915/vlv: use lower precision RC6 counter

And add some reg defines while we're at it. Since the units of the RC6 residency counter are actually in CZ clocks, we want to just use the high bits or we'll overflow too frequently. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 4 drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH] drm/i915/vlv: reset DPIO on load and resume

This fixes resume on my test platform, since I think some DPIO bits need recalibration. References: https://bugs.freedesktop.org/show_bug.cgi?id=69166 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers

Re: [Intel-gfx] [PATCH] drm/i915/vlv: reset DPIO on load and resume

On Thu, 26 Sep 2013 23:51:52 +0200 Daniel Vetter wrote: > On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote: > > This fixes resume on my test platform, since I think some DPIO bits need > > recalibration. > > > > References: https://bugs.freedeskto

Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: use correct units for rc6 residency

On Thu, 26 Sep 2013 23:25:46 +0100 Chris Wilson wrote: > On Thu, Sep 26, 2013 at 12:33:21PM -0700, Jesse Barnes wrote: > > We need to use the clock control reg to figure out how many CZ clks are in > > 30ns and use that as the basis for our RC6 residency calculations. >

Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: use correct units for rc6 residency

On Fri, 27 Sep 2013 01:49:37 +0100 Chris Wilson wrote: > On Thu, Sep 26, 2013 at 03:34:33PM -0700, Jesse Barnes wrote: > > On Thu, 26 Sep 2013 23:25:46 +0100 > > Chris Wilson wrote: > > > > > > > > > > > if (!intel_e

[Intel-gfx] [PATCH 1/2] drm/i915/vlv: use lower precision RC6 counter

And add some reg defines while we're at it. Since the units of the RC6 residency counter are actually in CZ clocks, we want to just use the high bits or we'll overflow too frequently. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 4 drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 2/2] drm/i915/vlv: use correct units for rc6 residency v2

Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/i915_sysfs.c | 22 -- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cf995bb..6f8d0cf 100644

[Intel-gfx] [PATCH] drm/i915/vlv: reduce GT FIFO error info to a debug message

ff. References: https://bugs.freedesktop.org/show_bug.cgi?id=69396 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 102fc49..10054b5 100644 --- a/

[Intel-gfx] [PATCH] drm/i915/vlv: untangle integrated clock source handling

ff-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0eeba84..def2473 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 1/5] drm/i915/vlv: reduce GT FIFO error info to a debug message

ff. References: https://bugs.freedesktop.org/show_bug.cgi?id=69396 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 102fc49..10054b5 100644 --- a/

[Intel-gfx] [PATCH 5/5] drm/i915/vlv: add valleyview_crtc_disable function

To handle disabling DP after the CPU pipe is disabled, per the workaround. References: https://bugs.freedesktop.org/show_bug.cgi?id=58152 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 58 1 file changed, 53 insertions(+), 5 deletions

[Intel-gfx] [PATCH 3/5] drm/i915/vlv: warn on bad VLV PLL divider values

This avoids a divide by zero and warns appropriately on this serious bug. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8da1c96

[Intel-gfx] [PATCH 4/5] drm/i915/vlv: untangle integrated clock source handling v2

67245 References: https://bugs.freedesktop.org/show_bug.cgi?id=69693 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 26 -- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 2/5] drm/i915: use wait_event_timeout when waiting for flip completions

We're shutting the crtc off and don't want to hang forever. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c ind

Re: [Intel-gfx] [PATCH 3/5] drm/i915/vlv: warn on bad VLV PLL divider values

On Fri, 27 Sep 2013 22:11:33 +0200 Daniel Vetter wrote: > On Fri, Sep 27, 2013 at 09:05:24PM +0100, Chris Wilson wrote: > > On Fri, Sep 27, 2013 at 12:57:24PM -0700, Jesse Barnes wrote: > > > This avoids a divide by zero and warns appropriately on this serious bug. > >

Re: [Intel-gfx] [PATCH 2/5] drm/i915: use wait_event_timeout when waiting for flip completions

On Fri, 27 Sep 2013 21:45:39 +0100 Chris Wilson wrote: > On Fri, Sep 27, 2013 at 12:57:23PM -0700, Jesse Barnes wrote: > > We're shutting the crtc off and don't want to hang forever. > > That scares me ever so slightly, especially ignoring the failure. Do you &g

[Intel-gfx] [PATCH 2/2] drm/i915/vlv: use per-pipe backlight controls

With the connector and pipe passed around, we can now set the backlight on the right pipe on VLV/BYT. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h| 10 ++ drivers/gpu/drm/i915/intel_panel.c | 65 +++--- 2 files changed, 63 insertions

[Intel-gfx] [PATCH 1/2] drm/i915: make backlight functions take a connector

On VLV/BYT, backlight controls a per-pipe, so when adjusting the backlight we need to pass the correct info. So make the externally visible backlight functions take a connector argument, which can be used internally to figure out the pipe backlight to adjust. Signed-off-by: Jesse Barnes

Re: [Intel-gfx] [PATCH] drm/i915/vlv: untangle integrated clock source handling

On Fri, 27 Sep 2013 23:09:26 +0300 Ville Syrjälä wrote: > On Fri, Sep 27, 2013 at 12:22:11PM -0700, Jesse Barnes wrote: > > The global integrated clock source bit resides in DPLL B on VLV, but we > > were treating it as a per-pipe resource. It needs to be set whenever > &

[Intel-gfx] [PATCH] drm/i915/vlv: untangle integrated clock source handling v3

early (Ville) consistently set CRI clock source everywhere (Ville) References: https://bugs.freedesktop.org/show_bug.cgi?id=67245 References: https://bugs.freedesktop.org/show_bug.cgi?id=69693 Signed-off-by: Jesse Barnes int clock --- drivers/gpu/drm/i915/intel_display.c

Re: [Intel-gfx] [PATCH 2/5] drm/i915: use wait_event_timeout when waiting for flip completions

On Sat, 28 Sep 2013 11:35:11 +0200 Daniel Vetter wrote: > On Fri, Sep 27, 2013 at 9:57 PM, Jesse Barnes > wrote: > > We're shutting the crtc off and don't want to hang forever. > > Reading the source and the test-suite is advisable ;-) > - We actually don

Re: [Intel-gfx] [PATCH 2/5] drm/i915: use wait_event_timeout when waiting for flip completions

kms flip hangs here forever on ByT right now, thus this hack.  Jesse Barnes, Intel Open Source Technology Center Original message From: Daniel Vetter Date: 28/09/2013 2:35 AM (GMT-08:00) To: Jesse Barnes Cc: intel-gfx Subject: Re: [Intel-gfx] [PATCH 2/5] drm/i915: use

Re: [Intel-gfx] [PATCH] drm/i915/vlv: untangle integrated clock source handling v3

On Sat, 28 Sep 2013 11:54:21 +0200 Daniel Vetter wrote: > On Fri, Sep 27, 2013 at 04:02:29PM -0700, Jesse Barnes wrote: > > The global integrated clock source bit resides in DPLL B on VLV, but we > > were treating it as a per-pipe resource. It needs to be set whenever > >

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