On Wed, 19 May 2021, Zhenyu Wang wrote:
> Reviewed-by: Zhenyu Wang
>
> Thanks!
Thanks for the review. Please also let Greg know whether he can pick
this up via the debugfs tree; I don't care either way.
BR,
Jani.
--
Jani Nikula, Intel Open Source G
om
kernel, with the proper commit message.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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ining that
has a cost due to the inevitable conflicts. We can add the branches back
if and when there's interest in sharing the burden.
Cc: Alex Deucher
Cc: Christian König
Cc: Pan, Xinhui
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
nightly.conf | 9 -
1 file changed, 9
t/kvmgt.c | 122 +++---
> drivers/gpu/drm/i915/gvt/mpt.h | 4 +-
> 6 files changed, 118 insertions(+), 138 deletions(-)
>
--
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gem: Pin the L-shape quirked object as unshrinkable
Jani Nikula (1):
Merge tag 'gvt-fixes-2021-05-19' of https://github.com/intel/gvt-linux
into drm-intel-fixes
Simon Rettberg (1):
drm/i915/gt: Disable HiZ Raw Stall Optimization on broken gen7
Zhenyu Wang (1):
drm/i915/
On Tue, 18 May 2021, Lucas De Marchi wrote:
> On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote:
>>Rename all occurences of CSR_* with DMC_*
>>
>>Cc: Jani Nikula
>>Signed-off-by: Anusha Srivatsa
>
>
> Reviewed-by: Lucas De Marchi
We
On Thu, 20 May 2021, Anusha Srivatsa wrote:
> Use new format of debug messages across intel_csr.
>
> While at it, change some function definitions which now
> need dev_priv for drm_err and drm_info etc.
>
> v2: use container_of() (Jani)
>
> Cc: Jani Nikula
> Su
or)((major) << 16 | (minor))
> @@ -17,5 +21,6 @@ void intel_dmc_load_program(struct drm_i915_private *i915);
> void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> void intel_dmc_ucode_resume(struct drm_i915_private *i
cas De Marchi
> wrote:
>>
>> On Fri, May 21, 2021 at 10:40:47AM -0700, Anusha Srivatsa wrote:
>> >Propogate changes to macros name containing CSR_*
>> >to DMC_* from display side.
>> >
>> >Fixes: 0633cdcbaa77 ("drm/i915/dmc: Rename macro names c
appear to be missing from the GVT code. Please fix
>> ASAP.
>>
>
> Thanks, Thomas. Looks DMC rename missed gvt part. We need to ask CI to have
> at least build test with gvt.
Indeed. This is fixed now with 273895109a04 ("drm/i915/gvt: Add missing
macro name changes&q
On Wed, 19 May 2021, "Deucher, Alexander" wrote:
> [AMD Public Use]
>
>> -Original Message-
>> From: Jani Nikula
>> Sent: Wednesday, May 19, 2021 4:50 AM
>> To: dim-to...@lists.freedesktop.org
>> Cc: dri-de...@lists.freedesktop.org
On Mon, 24 May 2021, Jani Nikula wrote:
> On Wed, 19 May 2021, "Deucher, Alexander" wrote:
>> [AMD Public Use]
>>
>>> -----Original Message-
>>> From: Jani Nikula
>>> Sent: Wednesday, May 19, 2021 4:50 AM
>>> To: dim-to...@lists.f
_transcoder)) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR2 not supported in transcoder %s\n",
--
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On ADL-P, it's possible to enable the stream splitter on pipe B in
addition to pipe A.
Bspec: 50174
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/driver
On Tue, 25 May 2021, Shaokun Zhang wrote:
> Function 'intel_dbuf_init' is declared twice, remove the
> repeated declaration.
>
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Signed-off-by: Shaokun Zhang
Thanks, pushed to drm-intel-next.
BR,
Jani.
On Wed, 26 May 2021, Ville Syrjälä wrote:
> On Wed, May 26, 2021 at 11:29:03AM +0300, Jani Nikula wrote:
>> On ADL-P, it's possible to enable the stream splitter on pipe B in
>> addition to pipe A.
>>
>> Bspec: 50174
>> Cc: Uma Shankar
>> Cc: Ville S
ODE_SPLIT (3 << 0) /* ivb-bdw */
> #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
> +#define GAMMA_MODE_DITHER_AFTER_CC1 (1 << 26)
The bits are supposed to be defined in the order from highest to lowest
bit. See the big comment at the begin
>debugfs_entry, crtc,
> + &dither_state_fops);
> +
See intel_crtc_debugfs_add(), called from intel_crtc_late_register().
> for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) {
> debugfs_create_file(intel_display_debugfs_files[i].name,
> S_IRUGO | S_IWUSR,
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ign the visibility of device level and global modparams to make them
> consistent in this respect.
>
> v2:
> * Fix misplaced parentheses.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Jani Nikula
> Cc: Ville Syrjälä
Reviewed-by: Jani Nikula
I'd happily accept patches re
On Wed, 26 May 2021, "Modem, Bhanuprakash" wrote:
>> From: Jani Nikula
>> When you're sending someone else's patches, you need to add your own
>> Signed-off-by here.
>
> Patch 2/2 in this series has a dependency on this patch. And I haven't
.../gpu/drm/i915/display/intel_dp_link_training.c | 71 ++
1 file changed, 33 insertions(+), 38 deletions(-)
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is enabled (%d downstream devices)\n",
> + num_downstream);
> + goto out;
> + }
> }
>
> - drm_dbg_kms(&dev_priv->drm, "HDCP is enabled (%d downstream devices)\n",
> - num_dow
On Fri, 13 Aug 2021, Rodrigo Vivi wrote:
> On Fri, Aug 13, 2021 at 02:56:10PM +0300, Jani Nikula wrote:
>> Less is more, fewer lines to wonder about.
>>
>> Cc: Manasi Navare
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Rodrigo Vivi
Thanks!
> although
;pipe_mask. Abstract the splitter pipe mask to a single point of
>> truth while at it to avoid similar mistakes in the future.
>>
>> Fixes: 7bc188cc2c8c ("drm/i915/adl_p: enable MSO on pipe B")
>> Cc: Uma Shankar
>> Cc: Ville Syrjälä
>&
On Fri, 13 Aug 2021, Jani Nikula wrote:
> On Fri, 13 Aug 2021, Rodrigo Vivi wrote:
>> On Fri, Aug 13, 2021 at 02:56:10PM +0300, Jani Nikula wrote:
>>> Less is more, fewer lines to wonder about.
>>>
>>> Cc: Manasi Navare
>>> Signed-off-by:
On Fri, 13 Aug 2021, Matt Roper wrote:
> On Fri, Aug 13, 2021 at 02:51:50PM +0300, Jani Nikula wrote:
>> We use encoder->get_buf_trans() in many places, for example
>> intel_ddi_dp_voltage_max(), and the hook was set to some old platform's
>> function for DG2 SNPS PHY
On Fri, 13 Aug 2021, Jani Nikula wrote:
> On Fri, 13 Aug 2021, Matt Roper wrote:
>> On Fri, Aug 13, 2021 at 02:51:50PM +0300, Jani Nikula wrote:
>>> We use encoder->get_buf_trans() in many places, for example
>>> intel_ddi_dp_voltage_max(), and the hook
tel_hdmi_dsc_get_slice_height(int vactive);
> +bool intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state);
>
> #endif /* __INTEL_HDMI_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
The symbol isn't needed outside of i915.ko.
Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link
training")
Fixes: 264613b406eb ("drm/i915: Disable LTTPR support when the DPCD rev < 1.4")
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
existing patches on the list where I've attempted this, and
Ville has refuted them refuted me time and time again. :(
BR,
Jani.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 22 +
bviously you don't have to do that here,
but this need to be done so that this doesn't become impossible.
BR,
Jani.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 185 +
On Mon, 16 Aug 2021, "Sharma, Swati2" wrote:
> On 13-Aug-21 1:16 PM, Jani Nikula wrote:
>> On Thu, 12 Aug 2021, Swati Sharma wrote:
>>> drm_dp_dpcd_read/write already has debug error message.
>>> Drop redundant error messages which gives false
>&g
On Mon, 16 Aug 2021, "Sharma, Swati2" wrote:
> On 16-Aug-21 5:40 PM, Jani Nikula wrote:
>> On Mon, 16 Aug 2021, "Sharma, Swati2" wrote:
>>> On 13-Aug-21 1:16 PM, Jani Nikula wrote:
>>>> On Thu, 12 Aug 2021, Swati Sharma wrote:
>>&g
On Mon, 16 Aug 2021, Imre Deak wrote:
> On Mon, Aug 16, 2021 at 10:17:37AM +0300, Jani Nikula wrote:
>> The symbol isn't needed outside of i915.ko.
>>
>> Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link
>> training")
>&g
On Mon, 16 Aug 2021, Matt Roper wrote:
> On Fri, Aug 13, 2021 at 03:33:30PM +0300, Jani Nikula wrote:
>> DG2 has 243000 but not 648000.
>
> Am I looking in the wrong place? When I check the bspec page I still
> see:
>
> eDP/DP link bit rates: 1.62, 2.16, 2.
;
> +}
Btw, I also have WIP to completely nuke ddi_port_info. It's a silly
cache that should go away.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
I think we need to have them. (Probably should be a separate
patch to keep the code movement easier to review.)
BR,
Jani.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> Documentation/gpu/i915.rst| 14 +-
>
Some header cleanups I've had around but never posted.
Jani Nikula (5):
drm/i915/irq: reduce inlines to reduce header dependencies
drm/i915: intel_runtime_pm.h does not actually need intel_display.h
drm/i915/pm: use forward declaration to remove an include
drm/i915/panel:
Reduce includes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_runtime_pm.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h
b/drivers/gpu/drm/i915/intel_runtime_pm.h
index 183ea2b187fe..47a85fab4130 100644
--- a/drivers/gpu/drm/i915
The fewer includes the better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_pm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 91f23b7f0af2..941b3ae555c8 100644
--- a/drivers/gpu/drm/i915
Presumably if the compiler is smart, it does not generate an extra
function call to the update functions that are now static.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 50 +---
drivers/gpu/drm/i915/i915_irq.h | 51
There's no performance reason to have it as static inline; move it out
of intel_display_types.h to reduce clutter and dependency on i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h | 9 -
drivers/gpu/drm/i915/display/intel_fdi.c
There's no performance reason to have it as static inline; move it out
of intel_display_types.h to reduce clutter and dependency on i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_display_types.
On Fri, 13 Aug 2021, Lee Shawn C wrote:
> Driver has to swap the endian before send brightness level value
> to tcon.
>
> v2: Use __be16 instead of u16 to fix sparse warning.
>
> Reported-by: kernel test robot
> Cc: Ville Syrjala
> Cc: Jani Nikula
> Cc: Vandita K
Start enabling DP 2.0 features. It's not complete, but it's a good
start, and should not conflict with anything existing.
Jani Nikula (17):
drm/dp: add DP 2.0 UHBR link rate and bw code conversions
drm/dp: use more of the extended receiver cap
drm/dp: add LTTPR DP 2.0 DPCD addre
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link
rates. Handle DP 2.0 UHBR rates as special cases, though this is not
pretty.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 26 ++
1 file changed, 22
Extend the use of extended receiver cap at 0x2200 to cover
MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
the DP 2.0 128b/132b channel encoding cap.
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of
vswing and pre-emphasis.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 16 insertions(+)
diff
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
ure all the places are
covered.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 30 -
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++---
3 files changed, 21 insertions(+), 17 deletions(-)
d
See if sink supports DP 2.0 128b/132b channel encoding, and update sink
rates accordingly.
FIXME: Also take LTTPR 128b/132b into account.
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
1 file changed, 18 insertions
This register controls the DP 2.0 datapath.
Bspec: 69967
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72dd3a6d205d
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register
conflicts with FDI. Since we have to deal with both meanings in the same
code, for different platforms, clarify the macro name so we don't
forget.
Bspec: 50493
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/di
Add the registers for specifying the lower and higher 24 bits of the DP
2.0 pixel clock frequency in Hz.
Bspec: 53326
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm
DG2 supports DP 2.0 UHBR and 128b/132b channel encoding.
Bspec: 53657, 54034
Acked-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b
-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 51 ++---
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
2 files changed, 46 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10
UHBR rates and 128b/132b channel encoding go hand in hand.
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
Set the DP 2.0 128b/132b channel encoding for UHBR rates.
Bspec: 54128
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
128b/132b has a separate transcoder DDI mode, which also requires the
MST transport select to be set. Note that we'll use DP MST also for
single-stream 128b/132b.
Having the FDI and 128b/132b modes share the register mode value
complicates things a bit.
Bspec: 50493
Signed-off-by: Jani N
There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.
Bspec: 54128
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst
The 128b/132b channel coding link training uses more straightforward TX
FFE preset values.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++-
.../drm/i915/display/intel_dp_link_training.c | 86 +--
2 files changed, 70 insertions(+), 29
On Thu, 19 Aug 2021, Ville Syrjälä wrote:
> On Wed, Aug 18, 2021 at 09:10:48PM +0300, Jani Nikula wrote:
>> UHBR rates and 128b/132b channel encoding go hand in hand.
>>
>> Reviewed-by: Manasi Navare
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/dr
On Thu, 19 Aug 2021, Ville Syrjälä wrote:
> On Wed, Aug 18, 2021 at 01:11:09PM +0300, Jani Nikula wrote:
>> There's no performance reason to have it as static inline; move it out
>> of intel_display_types.h to reduce clutter and dependency on i915_drv.h.
>>
>
The unsigned doesn't help us here.
Cc: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.h | 4 +---
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gp
On Thu, 12 Aug 2021, Lee Shawn C wrote:
> DSI driver should have its own implementation to toggle
> gpio pins based on GPIO info coming from VBT sequences.
>
> v2: Remove redundant ICP_PP_CONTROL() define.
>
> Cc: Ville Syrjala
> Cc: Jani Nikula
> Cc: Vandita Kulkarni
Make some forward progress on reducing intel_display.c size.
Jani Nikula (6):
drm/i915/display: split out dpt out of intel_display.c
drm/i915: add HAS_ASYNC_FLIPS feature macro
drm/i915/fb: move intel_tile_width_bytes() to intel_fb.c
drm/i915/fb: move intel_fb_align_height() to intel_fb.c
Let's try to reduce the size of intel_display.c, not increase it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_display.c | 220 +-
drivers/gpu/drm/i915/display/intel_dpt.c
This will be needed in multiple places soon.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 9 ++---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
Split out fb related stuff from intel_display.c to intel_fb.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 54
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_fb.c | 54
Split out fb related stuff from intel_display.c to intel_fb.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 9 -
drivers/gpu/drm/i915/display/intel_display.h | 2 --
drivers/gpu/drm/i915/display/intel_fb.c | 9 +
drivers/gpu/drm/i915/display
Split out fb related stuff from intel_display.c to intel_fb.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 64
drivers/gpu/drm/i915/display/intel_display.h | 3 -
drivers/gpu/drm/i915/display/intel_fb.c | 64
Split out fb related stuff from intel_display.c to intel_fb.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 355 ---
drivers/gpu/drm/i915/display/intel_fb.c | 354 ++
drivers/gpu/drm/i915/display/intel_fb.h | 14 +-
3
funcs); i++) {
>> -err = init_funcs[i].init();
>> - if (err < 0) {
>> -while (i--) {
>> -if (init_funcs[i].exit)
>> -init_funcs[i].exit();
>> -}
>> -return err;
>> -} else if (err > 0) {
>> -/*
>> - * Early-exit success is reserved for things which
>> - * don't have an exit() function because we have no
>> - * idea how far they got or how to partially tear
>> - * them down.
>> - */
>> -WARN_ON(init_funcs[i].exit);
>> -
>> -/*
>> - * We don't want to advertise devices with an only
>> - * partially initialized driver.
>> - */
>> -WARN_ON(i915_pci_driver.driver.owner);
>> -break;
>> -}
>> -}
>> -
>> -init_progress = i;
>> -
>> -return 0;
>> -}
>> -
>> -static void __exit i915_exit(void)
>> -{
>> -int i;
>> -
>> -for (i = init_progress - 1; i >= 0; i--) {
>> -GEM_BUG_ON(i >= ARRAY_SIZE(init_funcs));
>> -if (init_funcs[i].exit)
>> -init_funcs[i].exit();
>> -}
>> -}
>> -
>> -module_init(i915_init);
>> -module_exit(i915_exit);
>> -
>> -MODULE_AUTHOR("Tungsten Graphics, Inc.");
>> -MODULE_AUTHOR("Intel Corporation");
>> -
>> -MODULE_DESCRIPTION(DRIVER_DESC);
>> -MODULE_LICENSE("GPL and additional rights");
>> diff --git a/drivers/gpu/drm/i915/i915_pci.h
>> b/drivers/gpu/drm/i915/i915_pci.h
>> new file mode 100644
>> index ..b386f319f52e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/i915_pci.h
>> @@ -0,0 +1,8 @@
>> +/*
>> + * SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2021 Intel Corporation
>> + */
>> +
>> +int i915_register_pci_driver(void);
>> +void i915_unregister_pci_driver(void);
--
Jani Nikula, Intel Open Source Graphics Center
Some review comments addressed, some helpers added for DP 2.0 and UHBR
checks.
BR,
Jani.
Jani Nikula (19):
drm/dp: add DP 2.0 UHBR link rate and bw code conversions
drm/dp: use more of the extended receiver cap
drm/dp: add LTTPR DP 2.0 DPCD addresses
drm/dp: add helper for extracting
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link
rates. Handle DP 2.0 UHBR rates as special cases, though this is not
pretty.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 26 ++
1 file changed, 22
Extend the use of extended receiver cap at 0x2200 to cover
MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
the DP 2.0 128b/132b channel encoding cap.
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of
vswing and pre-emphasis.
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++
include/drm/drm_dp_helper.h | 2 ++
2 files
ure all the places are
covered.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 30 -
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++---
3 files changed, 21 inserti
See if sink supports DP 2.0 128b/132b channel encoding, and update sink
rates accordingly.
FIXME: Also take LTTPR 128b/132b into account.
v2: Add build-time check for ->sink_rates size (Ville)
Reviewed-by: Manasi Navare
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/
This register controls the DP 2.0 datapath.
Bspec: 69967
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b7c69c70b66
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register
conflicts with FDI. Since we have to deal with both meanings in the same
code, for different platforms, clarify the macro name so we don't
forget.
Bspec: 50493
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/di
Add the registers for specifying the lower and higher 24 bits of the DP
2.0 pixel clock frequency in Hz.
Bspec: 53326
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm
DG2 supports DP 2.0 UHBR and 128b/132b channel encoding.
Bspec: 53657, 54034
Acked-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b
-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 52 ++---
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
2 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index
Helpful abstraction to avoid duplication.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.
v2: Use intel_dp_is_uhbr
Reviewed-by: Manasi Navare # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display
UHBR rates and 128b/132b channel encoding go hand in hand.
v2: Fix check for >= UHBR rates using intel_dp_is_uhbr() (Ville)
Reviewed-by: Manasi Navare # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
Set the DP 2.0 128b/132b channel encoding for UHBR rates.
v2: Fix UHBR port clock check, use intel_dp_is_uhbr()
Bspec: 54128
Reviewed-by: Manasi Navare # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 -
1 file changed, 16 insertions(+), 1
Let's abstract the DP 2.0 feature. Initially just DG2.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a2b63072ff5..fc89cf618b44 100644
--- a/driver
128b/132b mode (Ville)
- Use intel_dp_is_uhbr() helper
Bspec: 50493
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++--
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm
There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.
v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper
Bspec: 54128
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++
1 file changed, 11 insertions(+)
The 128b/132b channel coding link training uses more straightforward TX
FFE preset values.
v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++-
.../drm/i915/display/intel_dp_link_training.c | 86
typec: altmodes/displayport: Notify drm subsys of hotplug events
>
> drivers/gpu/drm/drm_connector.c | 79 +
> drivers/gpu/drm/drm_crtc_internal.h | 2 +
> drivers/gpu/drm/drm_sysfs.c | 87
> +++-
> driver
On Tue, 24 Aug 2021, Rodrigo Vivi wrote:
> On Mon, Aug 23, 2021 at 03:25:30PM +0300, Jani Nikula wrote:
>> Make some forward progress on reducing intel_display.c size.
>>
>> Jani Nikula (6):
>> drm/i915/display: split out dpt out of intel_display.c
>> drm/
One step at a time.
BR,
Jani.
Cc: José Roberto de Souza
Jani Nikula (7):
drm/i915/bios: use hdmi level shift directly from child data
drm/i915/bios: use max tmds clock directly from child data
drm/i915/bios: use dp max link rate directly from child data
drm/i915/bios: use alternate
Avoid extra caching of the data.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 26 +--
drivers/gpu/drm/i915/i915_drv.h | 4
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu
Avoid extra caching of the data.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 52 +++
drivers/gpu/drm/i915/i915_drv.h | 2 -
2 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm
Avoid extra caching of the data.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 28 ++-
drivers/gpu/drm/i915/i915_drv.h | 2 --
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm
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