On Fri, 01 Oct 2021, Jani Nikula wrote:
> If drm_modeset_lock() returns -EDEADLK, the caller is supposed to drop
> all currently held locks using drm_modeset_backoff(). Failing to do so
> will result in warnings and backtraces on the paths trying to lock a
> contended lock. Add
On Wed, 13 Oct 2021, Imre Deak wrote:
> On Thu, Oct 07, 2021 at 01:19:25PM +0530, Nautiyal, Ankit K wrote:
>>
>> On 10/5/2021 9:01 PM, Imre Deak wrote:
>> > On Tue, Oct 05, 2021 at 01:34:21PM +0300, Jani Nikula wrote:
>> > > Cc: Imre, I think you were invol
On Thu, 14 Oct 2021, Ville Syrjälä wrote:
> On Tue, Oct 12, 2021 at 05:43:20PM +0300, Jani Nikula wrote:
>> The link training delays are different and/or available in different
>> DPCD offsets depending on:
>>
>> - Clock recovery vs. channel equalization
>> - DPR
om the results
because they didn't boot?
Reviewed-by: Jani Nikula
>
> Cc: Dave Airlie
> Cc: Jani Nikula
> Fixes: cd030c7c11a4 ("drm/i915: constify hotplug function vtable.")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_hotplug.c | 3
On Thu, 14 Oct 2021, Jani Nikula wrote:
> On Thu, 14 Oct 2021, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> We don't have hpd support on i8xx/i915 which means hotplug_funcs==NULL.
>> Let's not oops when loading the driver on one those machines.
>
&
d use some cleanup.
- Slightly unrelated, all the functions in intel_display.c using
intel_sbi should be moved out of intel_display.c as a group.
BR,
Jani.
Cc: Ville Syrjälä
Jani Nikula (2):
drm/i915: split out intel_pcode.[ch] to separate file
drm/i915: rename intel_sideband.[ch] to intel_sbi.
The snb+ pcode mailbox code is not sideband, so split it out to a
separate file. As can be seen from the #include changes, very few places
use both sideband and pcode.
Code movement only.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1
Now that intel_sideband.[ch] has been decluttered, it's pure lpt/wpt
iosf sideband. Let's call it intel_sbi, following the function naming.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/display/intel_displ
On Tue, 05 Oct 2021, "Souza, Jose" wrote:
> On Tue, 2021-10-05 at 23:38 +0300, Jani Nikula wrote:
>> On Tue, 05 Oct 2021, "Souza, Jose" wrote:
>> > On Tue, 2021-10-05 at 20:56 +0300, Jani Nikula wrote:
>> > > For the time being, neither the powe
+#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
Do we want to promote this usage all over the place? Maybe keep them
internal to intel_fb.c?
Or just add both from and until members in intel_modifier_desc, and use
the regular IS_DISPLAY_VER() in intel_fb.c as well. It's not worse
considering the mask you have is u64. You could have two u8's
instead. You could consider 0 for either to mean "no limit", and skip
the initialization instead of duplicating .display_versions =
DISPLAY_VER_MASK_ALL.
I think I'd prefer that. Or do you see masks with gaps in them?
BR,
Jani.
>
> #define INTEL_REVID(dev_priv)
> (to_pci_dev((dev_priv)->drm.dev)->revision)
--
Jani Nikula, Intel Open Source Graphics Center
vers/gpu/drm/i915/gem/i915_gem_context.c | 5 -
drivers/gpu/drm/i915/gt/intel_context.c | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
On Thu, 14 Oct 2021, Jani Nikula wrote:
> On Thu, 07 Oct 2021, Imre Deak wrote:
>> +} intel_modifiers[] = {
>> +{
>> +.id = DRM_FORMAT_MOD_LINEAR,
>> +.display_versions = DISPLAY_VER_MASK_ALL,
>
> What is this going to look like whe
e way.
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_dp_link_training.c | 38 +++
1 file changed, 13 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm
d-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 30 ++
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f7ebf5974fa7..ada0a1ff262d 100644
--- a/drivers/gpu/drm/drm_dp_hel
.
v2: Remove delay_us < 0 check and the whole local var (Ville)
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 127
include/drm/drm_dp_helper.h | 21 +-
2 files changed, 146 inserti
On Thu, 14 Oct 2021, Imre Deak wrote:
> On Thu, Oct 14, 2021 at 05:07:16PM +0300, Jani Nikula wrote:
>> On Thu, 07 Oct 2021, Imre Deak wrote:
>> > Add a table describing all the framebuffer modifiers used by i915 at one
>> > place. This has the benefit of deduplicati
__drm_stack_depot_save(void)
> {
> return 0;
> }
> @@ -317,7 +317,7 @@ static inline int modeset_lock(struct drm_modeset_lock
> *lock,
> ret = 0;
> } else if (ret == -EDEADLK) {
> ctx->contended = lock;
> - ctx->stack_depot = __stack_depot_save();
> + ctx->stack_depot = __drm_stack_depot_save();
> }
>
> return ret;
> --
> 2.33.0
--
Jani Nikula, Intel Open Source Graphics Center
or =
> drm_detect_hdmi_monitor(edid);
> intel_sdvo->has_hdmi_audio =
> drm_detect_monitor_audio(edid);
> + intel_sdvo->has_hdmi_monitor =
> +
> intel_connector_is_hdmi_monitor(connector);
> }
> } else
> status = connector_status_disconnected;
--
Jani Nikula, Intel Open Source Graphics Center
On Fri, 15 Oct 2021, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 03:44:48PM +0300, Jani Nikula wrote:
>> On Fri, 15 Oct 2021, Claudio Suarez wrote:
>> > Once EDID is parsed, the monitor HDMI support information is available
>> > through drm_display_info.is_hdmi. Ret
On Thu, 14 Oct 2021, Jani Nikula wrote:
> The link training delays are different and/or available in different
> DPCD offsets depending on:
>
> - Clock recovery vs. channel equalization
> - DPRX vs. LTTPR
> - 128b/132b vs. 8b/10b
> - DPCD 1.4+ vs. earlier
>
> Add helper
On Fri, 15 Oct 2021, John Harrison wrote:
> On 10/15/2021 07:52, Tvrtko Ursulin wrote:
>> On 04/10/2021 08:36, Jani Nikula wrote:
>>> On Fri, 24 Sep 2021, Ville Syrjälä
>>> wrote:
>>>> On Tue, Sep 21, 2021 at 06:50:39PM -0700, Matthew Brost wrote:
>>
n
intel_dp_sync_state(), and it goes wrong with intel_dp->num_common_rates
being 0 and the array index being -1.
Anyway, having said that, we'll need to stop guessing and dig into the
root cause.
BR,
Jani.
>
>> +
>> /*
>> * Don't clobber DPCD if it's been already read out during output
>> * setup (eDP) or detect.
>
--
Jani Nikula, Intel Open Source Graphics Center
On Fri, 15 Oct 2021, Rodrigo Vivi wrote:
> We should stop using the gen name and the "+" to reference
> the newer platforms.
> And on this case specifically we can simplify the debug
> message even further.
Reviewed-by: Jani Nikula
>
> Cc: Jani Nikula
> Cc:
On Fri, 15 Oct 2021, Rodrigo Vivi wrote:
> There's no such thing as gen13. It is either display 13
> or graphics 13. Don't propagate the gen12 confusion
> further.
Reviewed-by: Jani Nikula
>
> Cc: Joonas Lahtinen
> Cc: Jani Nikula
> Signed-off-by: Rodrigo Vivi
ces: https://lore.kernel.org/r/20211015202648.25844...@canb.auug.org.au
Fixes: cd06ab2fd48f ("drm/locking: add backtrace for locking contended locks
without backoff")
Cc: Daniel Vetter
Signed-off-by: Stephen Rothwell
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_modeset_lock.c |
he line
above became unused and useless.
That's the actually helpful part. It's easy to see and verify that the
right fix is to just remove the line completely.
BR,
Jani.
> intel_fb_plane_dims(fb, i, &width, &height);
>
> ret = convert_plane_offset_to_xy(fb, i, width, &x, &y);
--
Jani Nikula, Intel Open Source Graphics Center
On Sat, 16 Oct 2021, Len Baker wrote:
> Hi Daniel and Jani,
>
> On Wed, Oct 13, 2021 at 01:51:30PM +0200, Daniel Vetter wrote:
>> On Wed, Oct 13, 2021 at 02:24:05PM +0300, Jani Nikula wrote:
>> > On Mon, 11 Oct 2021, Len Baker wrote:
>> > > Hi,
>> >
dp_init_connector(struct intel_digital_port
> *dig_port,
> }
>
> intel_dp_set_source_rates(intel_dp);
> + intel_dp_set_default_sink_rates(intel_dp);
> + intel_dp_set_common_rates(intel_dp);
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 19 Oct 2021, Imre Deak wrote:
> On Tue, Oct 19, 2021 at 10:27:18AM +0300, Jani Nikula wrote:
>> On Mon, 18 Oct 2021, Imre Deak wrote:
>> > Atm, there are no sink rate values set for DP (vs. eDP) sinks until the
>> > DPCD capabilities are successfully read from
k.
>> (Jani)
>> - Unexport struct intel_modifier_desc, separate its decl and init. (Jani)
>> - Remove enum pipe, plane_id forward decls from intel_fb.h, which are
>>not needed after v2.
>>
>> Cc: Ville Syrjälä
>> Cc: Juha-Pekka Heikkila
>> Cc:
odifier_display_ver_range(md, 12, 13)
==>
check_modifier_display_ver(md, 12) &&
check_modifier_display_ver(md, 13)
==>
12 >= md->display_ver.from &&
12 <= md->display_ver.until &&
13 >= md->display_ver.from &&
13 <= md->display_ver.until
==>
Always false.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Jani Nikula (2):
drm/dp: add helpers to read link training delays
drm/dp: reuse the 8b/10b link training delay helpers
drivers/gpu/drm/drm_dp_helper.c | 153 +++-
include/drm
_CHKN_LSHS_GB_MASKREG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB
> REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, 4)
>
> /* Display Stream Splitter Control */
> #define DSS_CTL1 _MMIO(0x67400)
--
Jani Nikula, Intel Open Source Graphics Center
L_ALDERLAKE_P),
> .require_force_probe = 1,
> .display.has_cdclk_crawl = 1,
> @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
> XE_HP_FEATURES,
> XE_HPM_FEATURES,
> XE_LPD_FEATURES,
> + DG2_TRANSCODERS,
> DGFX_FEATURES,
> .graphics_rel = 55,
> .media_rel = 55,
--
Jani Nikula, Intel Open Source Graphics Center
en11_dsi_gate_clocks(encoder);
So how does this relate to
991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
> }
>
> static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
--
Jani Nikula, Intel Open Source Graphics Center
POWER_DOMAIN_INIT)) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DSI)
Everywhere else POWER_DOMAIN_INIT is last in the list.
BR,
Jani.
>
> #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS
> BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
> #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS
> BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 19 Oct 2021, Ville Syrjälä wrote:
> On Tue, Oct 19, 2021 at 01:05:20PM +0300, Jani Nikula wrote:
>> On Mon, 18 Oct 2021, Vandita Kulkarni wrote:
>>
>> Commit message goes here.
>>
>> > Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA t
board.
References:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21255/bat-adlp-4/boot0.txt
Fixes: 05734ca2a8f7 ("drm/i915/bios: gracefully disable dual eDP for now")
Cc: José Roberto de Souza
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Swati Sharma
Signed-off-by: Jani Nikula
---
drive
\
>> > + [TRANSCODER_D] = PIPE_D_OFFSET,
>> \
>> >},
>> \
>> > - XE_LPD_CURSOR_OFFSETS
>> > + .trans_offsets = {
>> \
>> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
>> \
>> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
>> \
>> > + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
>> \
>> > + [TRANSCODER_D] = TRANSCODER_D_OFFSET,
>> \
>> > + }
>> \
>> >
>> > static const struct intel_device_info adl_p_info = {
>> >GEN12_FEATURES,
>> >XE_LPD_FEATURES,
>> > + ADLP_TRANSCODERS,
>> >PLATFORM(INTEL_ALDERLAKE_P),
>> >.require_force_probe = 1,
>> >.display.has_cdclk_crawl = 1,
>> > @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
>> >XE_HP_FEATURES,
>> >XE_HPM_FEATURES,
>> >XE_LPD_FEATURES,
>> > + DG2_TRANSCODERS,
>> >DGFX_FEATURES,
>> >.graphics_rel = 55,
>> >.media_rel = 55,
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
clocks after pll mapping")
>
> As per the latest bspec, this change doesn't seem to be valid anymore.
> It is marked with removed tag.
> When TGL got added this change came in.
>
> But now with ADL the whole thing is marked as removed.
> So, Do you suggest that I submit a revert for this change ?
No, just an explanation and maybe that commit reference in the commit
message.
BR,
Jani.
>
> Thanks,
> Vandita
>>
>> > }
>> >
>> > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
P_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
> #define DP_
On Mon, 18 Oct 2021, Jani Nikula wrote:
> From: Stephen Rothwell
>
> Commit cd06ab2fd48f ("drm/locking: add backtrace for locking contended
> locks without backoff") added functions named __stack_depot_* in drm
> which conflict with stack depot. Rename to __drm_stac
On Mon, 18 Oct 2021, Maxime Ripard wrote:
> Hi Jani,
>
> On Fri, Oct 15, 2021 at 06:21:35PM +0300, Jani Nikula wrote:
>> On Thu, 14 Oct 2021, Jani Nikula wrote:
>> > The link training delays are different and/or available in different
>> > DPCD offsets depending
On Tue, 19 Oct 2021, Maxime Ripard wrote:
> On Tue, Oct 19, 2021 at 12:59:57PM +0300, Jani Nikula wrote:
>>
>> Hi all -
>>
>> These are the drm dp helpers for figuring out link training delays, to
>> be pulled to both drm-misc-next and drm-intel-next.
>&
On Thu, 14 Oct 2021, Jani Nikula wrote:
> Use the new link training delay helpers, fixing the delays for
> 128b/132b.
>
> For existing 8b/10b functionality, this will cause additional 1-byte
> DPCD reads for LTTPR delays instead of using the cached values. It's
> just too
On Tue, 19 Oct 2021, Vandita Kulkarni wrote:
> v2: Fix the typo, move out the hardcoding from
> macro(Jani, Ville)
>
> Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup
> guardband")
> Signed-off-by: Vandita Kulkarni
Reviewed-by: Jan
On Tue, 19 Oct 2021, Vandita Kulkarni wrote:
> Update ADL_P device info to support DSI0, DSI1
>
> v2: Re-define cpu_transcoder_mask only (Jani)
>
> Signed-off-by: Vandita Kulkarni
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_pci.c | 11 +--
ff-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 21 +
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ada0a1ff262d..2c36fad88781 100644
--- a/drivers/gp
Drop the local intel_dp_phy_name() function, and replace with
drm_dp_phy_name(). This lets us drop a number of local buffers.
v2: Rebase
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä # v1
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_dp_link_training.c | 83 ---
1
/* YCBCR420 TMDS rate requirement is half the pixel clock */
> - if (intel_hdmi_is_ycbcr420(crtc_state))
> - clock /= 2;
> -
> bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
>
> - crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
> + crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
> +
> intel_hdmi_is_ycbcr420(crtc_state));
>
> /*
>* pipe_bpp could already be below 8bpc due to
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 19 Oct 2021, Imre Deak wrote:
> On Tue, Oct 19, 2021 at 10:39:08AM +0300, Imre Deak wrote:
>> On Tue, Oct 19, 2021 at 10:37:33AM +0300, Jani Nikula wrote:
>> > On Tue, 19 Oct 2021, Imre Deak wrote:
>> > > On Tue, Oct 19, 2021 at 10:27:18AM +0300, Jani Nikula
link rates between source and sink */
> - drm_WARN_ON(encoder->base.dev, common_len <= 0);
> -
> - limits.min_rate = intel_dp->common_rates[0];
> - limits.max_rate = intel_dp->common_rates[common_len - 1];
> + limits.min_rate = intel_dp_common_rate(intel_dp, 0);
> + limits.max_rate = intel_dp_max_link_rate(intel_dp);
>
> limits.min_lane_count = 1;
> limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
--
Jani Nikula, Intel Open Source Graphics Center
Syrjälä
Patches 1-5,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 35 ++-
> 1 file changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/di
int order;
>
> @@ -427,11 +424,11 @@ void i915_buddy_print(struct i915_buddy_mm *mm, struct
> drm_printer *p)
> mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20);
>
> for (order = mm->max_order; order >= 0; order--) {
> - struct i915_buddy_block *block;
> + struct drm_buddy_block *block;
> u64 count = 0, free;
>
> list_for_each_entry(block, &mm->free_list[order], link) {
> - GEM_BUG_ON(!i915_buddy_block_is_free(block));
> + BUG_ON(!drm_buddy_block_is_free(block));
> count++;
> }
>
> @@ -451,14 +448,14 @@ void i915_buddy_print(struct i915_buddy_mm *mm, struct
> drm_printer *p)
> #include "selftests/i915_buddy.c"
> #endif
>
> -void i915_buddy_module_exit(void)
> +void drm_buddy_module_exit(void)
> {
> kmem_cache_destroy(slab_blocks);
> }
>
> -int __init i915_buddy_module_init(void)
> +int __init drm_buddy_module_init(void)
> {
> - slab_blocks = KMEM_CACHE(i915_buddy_block, 0);
> + slab_blocks = KMEM_CACHE(drm_buddy_block, 0);
> if (!slab_blocks)
> return -ENOMEM;
>
> diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h
> index 521ed532d2b8..390b133fe342 100644
> --- a/include/drm/drm_buddy.h
> +++ b/include/drm/drm_buddy.h
> @@ -9,9 +9,19 @@
> #include
> #include
> #include
> +#include
>
> #include
>
> +#define range_overflows(start, size, max) ({ \
> + typeof(start) start__ = (start); \
> + typeof(size) size__ = (size); \
> + typeof(max) max__ = (max); \
> + (void)(&start__ == &size__); \
> + (void)(&start__ == &max__); \
> + start__ >= max__ || size__ > max__ - start__; \
> +})
> +
> struct drm_buddy_block {
> #define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
> #define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10)
--
Jani Nikula, Intel Open Source Graphics Center
changes the device info, and the copying all of that data over to
runtime info probably isn't worth it.
Should we just acknowledge that the runtime info is useless, and move
some of that data to intel_device_info and some of it elsewhere in i915?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
On Wed, 20 Oct 2021, Imre Deak wrote:
> On Tue, Oct 19, 2021 at 10:23:14PM +0300, Jani Nikula wrote:
>> On Mon, 18 Oct 2021, Imre Deak wrote:
>> > Add an assert that lookups from the intel_dp->common_rates[] array
>> > are always valid.
>>
>> The one t
x5
> -
> -#define DP_PHY_SQUARE_PATTERN0x249
> +#define DP_LINK_QUAL_PATTERN_SELECT 0x248
Please add a comment here referencing where the values are. There are
examples in the file.
> +
> +#define DP_PHY_SQUARE_PATTERN 0x249
>
> #define DP_TEST_HBR2_SCRAMBLER_RESET0x24A
> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250
--
Jani Nikula, Intel Open Source Graphics Center
| 16
> include/drm/drm_dp_helper.h | 13 +++--
> 7 files changed, 33 insertions(+), 40 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
cl and init. (Jani)
> - Remove enum pipe, plane_id forward decls from intel_fb.h, which are
> not needed after v2.
> v4:
> - Reuse IS_DISPLAY_VER() instead of open-coding it. (Jani)
> - Preserve the current modifier order exposed to user space. (Ville)
>
> Cc: Ville Syrjäl
ell.
> + */
> + if (linked) {
> + struct intel_plane_state *linked_new_plane_state =
> + intel_atomic_get_new_plane_state(state, linked);
> + struct drm_rect *linked_sel_fetch_area =
> + &
On Thu, 21 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> A bunch of function prototypes were left behind when the
> plane/crtc code got reshuffled to new files. Move the
> prototypes as well.
Reviewed-by: Jani Nikula
>
> Signed-off-by: Ville Syrjälä
> ---
),
> +
> + TP_fast_assign(
> +__entry->pipe = crtc->pipe;
> +__entry->frame = intel_crtc_get_vblank_counter(crtc);
> +__entry->scanline = intel_get_crtc_scanline(crtc);
> +),
> +
> + TP_printk("pipe %c, frame=%u, scanline=%u",
> + pipe_name(__entry->pipe), __entry->frame,
> +__entry->scanline)
> +);
> +
> +TRACE_EVENT(intel_crtc_vblank_work_end,
> + TP_PROTO(struct intel_crtc *crtc),
> + TP_ARGS(crtc),
> +
> + TP_STRUCT__entry(
> + __field(enum pipe, pipe)
> + __field(u32, frame)
> + __field(u32, scanline)
> + ),
> +
> + TP_fast_assign(
> +__entry->pipe = crtc->pipe;
> +__entry->frame = intel_crtc_get_vblank_counter(crtc);
> +__entry->scanline = intel_get_crtc_scanline(crtc);
> +),
> +
> + TP_printk("pipe %c, frame=%u, scanline=%u",
> + pipe_name(__entry->pipe), __entry->frame,
> +__entry->scanline)
> +);
> +
> TRACE_EVENT(intel_pipe_update_start,
> TP_PROTO(struct intel_crtc *crtc),
> TP_ARGS(crtc),
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 19 Oct 2021, "Souza, Jose" wrote:
> On Tue, 2021-10-19 at 14:43 +0300, Jani Nikula wrote:
>> This reverts commit 05734ca2a8f76c9eb3890b3c9dfc3467f03105c1.
>>
>> It's not graceful, instead it leads to boot time warning splats in the
>> case it is
On Thu, 21 Oct 2021, Ville Syrjälä wrote:
> On Thu, Oct 21, 2021 at 01:35:12PM +0300, Jani Nikula wrote:
>> On Thu, 21 Oct 2021, Ville Syrjala wrote:
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_displa
On Wed, 20 Oct 2021, "Souza, Jose" wrote:
> On Wed, 2021-10-20 at 12:47 +0300, Jani Nikula wrote:
>> On Tue, 19 Oct 2021, José Roberto de Souza wrote:
>> > The constant platform display version is not using this new struct but
>> > the runtime variant will de
Add the const that was accidentally left out from the vtables.
Fixes: 6b4cd9cba620 ("drm/i915: constify the cdclk vtable")
Cc: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 44 +++---
1 file changed, 22 insertions(+), 22
c5..722910d02b5f 100644
>>--- a/drivers/gpu/drm/i915/intel_uncore.c
>>+++ b/drivers/gpu/drm/i915/intel_uncore.c
>>@@ -22,11 +22,11 @@
>> */
>>
>> #include
>>-#include
>>
>> #include "gt/intel_lrc_reg.h" /* for shadow reg list */
>>
>> #include "i915_drv.h"
>>+#include "i915_iosf_mbi.h"
>> #include "i915_trace.h"
>> #include "i915_vgpu.h"
>> #include "intel_pm.h"
>>diff --git a/drivers/gpu/drm/i915/vlv_sideband.c
>>b/drivers/gpu/drm/i915/vlv_sideband.c
>>index 35380738a951..ed2ac5752ac4 100644
>>--- a/drivers/gpu/drm/i915/vlv_sideband.c
>>+++ b/drivers/gpu/drm/i915/vlv_sideband.c
>>@@ -3,9 +3,8 @@
>> * Copyright © 2013-2021 Intel Corporation
>> */
>>
>>-#include
>>-
>> #include "i915_drv.h"
>>+#include "i915_iosf_mbi.h"
>> #include "vlv_sideband.h"
>>
>> /*
>>--
>>2.33.0
>>
--
Jani Nikula, Intel Open Source Graphics Center
xa, id);
> + if (vm && !kref_get_unless_zero(&vm->ref))
> + vm = NULL;
> + rcu_read_unlock();
> +
> + return vm;
> +}
> +
> /* i915_gem_evict.c */
> int __must_check i915_gem_evict_something(struct i915_address_space *vm,
> u64 min_size, u64 alignment,
--
Jani Nikula, Intel Open Source Graphics Center
i915_drv.h is mostly not about i915_drv.c, so make the distinction clear
by renaming i915_drv.c to i915_driver.c and splitting out i915_driver.h
from i915_drv.h.
Jani Nikula (2):
drm/i915/driver: rename i915_drv.c to i915_driver.c
drm/i915/driver: rename driver to i915_drm_driver
drivers
This is more about trimming i915_drv.h than the renamed
i915_driver.[ch]. Split out i915_driver.[ch] out of i915_drv.h as a
feasible thing to do.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 2 +-
.../drm/i915/{i915_drv.c => i915_driver.c}|
As a name, "driver" is too generic and short to be easily located in a
file this size. Rename it to i915_drm_driver.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_driver.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_d
t refactoring
and not take one step further. Or, indeed, take this step *first*.
BR,
Jani.
Jani Nikula (4):
drm/i915/audio: group audio under anonymous struct in drm_i915_private
drm/i915/audio: name the audio sub-struct in drm_i915_private
drm/i915/audio: define the audio struct sepa
With an anonymous struct, this can be pure hierarchical organization
without code changes.
Cc: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 43 +
1 file changed, 22 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915
Add name to the audio sub-struct in drm_i915_private, and remove the
tautologies and other inconsistencies in the member names.
Cc: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c| 90 +--
.../gpu/drm/i915/display/intel_lpe_audio.c
Add a standalone definition of struct intel_audio_private, and note that
all of it is private to intel_audio.c.
Cc: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 45 ++---
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a
It's all internal to intel_audio.c.
Cc: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 9 +
drivers/gpu/drm/i915/i915_drv.h| 10 +-
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/di
On Fri, 22 Oct 2021, Ville Syrjälä wrote:
> On Fri, Oct 22, 2021 at 07:27:56PM +0300, Jani Nikula wrote:
>> Add name to the audio sub-struct in drm_i915_private, and remove the
>> tautologies and other inconsistencies in the member names.
>>
>> Cc: Dave Airlie
&g
On Fri, 22 Oct 2021, Ville Syrjälä wrote:
> On Fri, Oct 22, 2021 at 07:27:57PM +0300, Jani Nikula wrote:
>> Add a standalone definition of struct intel_audio_private, and note that
>> all of it is private to intel_audio.c.
>>
>> Cc: Dave Airlie
>> Signed-off-by
1bd3/0x2050 [i915]
> ...
>
> This has been tested on a Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC) tablet,
> with a 1536x2048 dual-link DSI panel.
>
> Note this fix was taken from icl_dsi.c which does the same in
> its get_config().
>
> Cc: Tsuchiya Yuto
> Signed-of
4, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
> +
> + /* Xiaomi Mi Pad 2 */
> + { 0x22b0, 0x1d72, 0x1502, quirk_no_vlv_disp_pw_dpio_cmn_bc_init },
> };
>
> void intel_init_quirks(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 005b1cec7007..b907b49b4f0e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -524,6 +524,7 @@ struct i915_drrs {
> #define QUIRK_INCREASE_T12_DELAY (1<<6)
> #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
> #define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
> +#define QUIRK_NO_VLV_DISP_PW_DPIO_CMN_BC_INIT (1<<9)
>
> struct intel_fbdev;
> struct intel_fbc_work;
--
Jani Nikula, Intel Open Source Graphics Center
On Fri, 22 Oct 2021, Lucas De Marchi wrote:
> On Thu, Oct 21, 2021 at 04:11:26PM +0300, Jani Nikula wrote:
>>On Wed, 20 Oct 2021, "Souza, Jose" wrote:
>>> On Wed, 2021-10-20 at 12:47 +0300, Jani Nikula wrote:
>>>> On Tue, 19 Oct 2021, José Roberto de So
oltage_sku(i915, phy))
> + if (intel_dp_is_edp(intel_dp))
> return 54;
>
> return 81;
> @@ -468,7 +442,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> max_rate = dg2_max_source_rate(intel_dp);
> else if (IS_ALDERLAKE_P(dev_p
tes")
Cc: Manasi Navare
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f5dc2126d140..9a0cd2e1ebea
ata rate calculation for UHBR
rates")
Cc: Manasi Navare
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/int
der_data_lookup(i915, port);
> +
> + return devdata && child_dev_is_dp_dual_mode(&devdata->child);
> + }
> +
> + if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
> + return false;
> +
> list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
> - if (child_dev_is_dp_dual_mode(&devdata->child, port))
> + if ((devdata->child.dvo_port == port_mapping[port].dp ||
> + devdata->child.dvo_port == port_mapping[port].hdmi) &&
> + child_dev_is_dp_dual_mode(&devdata->child))
> return true;
> }
--
Jani Nikula, Intel Open Source Graphics Center
) GS:99b1c7c8 ()
> knlGS:0
> 000
> [ 2.555130] CS: 0010 DS: ES: CRO: 000080050033
> [ 2.555133] CR2: 560e0c7395b8 CR3: 000100d02000 CR4:
> 06e0
> [ 2.555244] Console: switching to colour frame buffer device 210x65
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 26 Oct 2021, Ville Syrjälä wrote:
> On Tue, Oct 26, 2021 at 12:34:07PM +0300, Jani Nikula wrote:
>> The intermediate value 100 * 10 * 9671 overflows 32 bits, so force
>> promotion to a bigger type.
>>
>> >From the logs:
>>
>> [drm:in
fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING_X);
>
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> 0, plane_funcs,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 317108e009bba..45f0225ec59dd 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2095,9 +2095,12 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> else
> plane_type = DRM_PLANE_TYPE_OVERLAY;
>
> - plane_caps = PLANE_HAS_TILING;
> + plane_caps = PLANE_HAS_TILING_X | PLANE_HAS_TILING_Y;
> + if (IS_DISPLAY_VER(dev_priv, 9, 11))
> + plane_caps |= PLANE_HAS_TILING_Yf;
> +
> if (skl_plane_has_rc_ccs(dev_priv, pipe, plane_id))
> - plane_caps |= PLANE_HAS_CCS_RC;
> + plane_caps |= PLANE_HAS_CCS_RC | PLANE_HAS_CCS_RC_CC;
>
> if (gen12_plane_has_mc_ccs(dev_priv, plane_id))
> plane_caps |= PLANE_HAS_CCS_MC;
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 26 Oct 2021, Satadru Pramanik wrote:
> That appears to do the trick.
Thanks for confirming.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, 26 Oct 2021, Lucas De Marchi wrote:
> On Wed, Oct 13, 2021 at 03:12:55PM +0300, Jani Nikula wrote:
>>On Fri, 08 Oct 2021, Matt Roper wrote:
>>> On a multi-tile platform, each tile has its own registers + GGTT space,
>>> and BAR 0 is extended to cover all of t
On Wed, 27 Oct 2021, Imre Deak wrote:
> On Tue, Oct 26, 2021 at 08:52:12PM +0300, Jani Nikula wrote:
>> AFAICT there are no intel_plane_caps references anywhere after this, and
>> it no longer looks like an enum, so perhaps it just shouldn't be an enum
>> anymore? Just m
NAME ": Missing cache flush in %s\n", __func__)
>> +#endif
>> +
>> I915_SELFTEST_DECLARE(static bool force_different_devices;)
>>
>> static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf)
>> --
>> 2.26.3
>>
--
Jani Nikula, Intel Open Source Graphics Center
On Wed, 27 Oct 2021, Jani Nikula wrote:
> On Wed, 27 Oct 2021, Matthew Auld wrote:
>> On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>>>
>>> wbinvd_on_all_cpus() is only defined on x86 it seems, plus we need to
>>> include asm/smp.h here.
>>>
&
On Wed, 27 Oct 2021, Matthew Auld wrote:
> On Wed, 27 Oct 2021 at 09:58, Jani Nikula wrote:
>>
>> On Wed, 27 Oct 2021, Matthew Auld wrote:
>> > On Thu, 21 Oct 2021 at 13:54, Matthew Auld wrote:
>> >>
>> >> wbinvd_on_all_cpus() is only defined on
# i915 depends on ACPI_VIDEO when ACPI is enabled
> # but for select to work, need to select ACPI_VIDEO's dependencies, ick
The comment needs updating as well.
Other than that,
Acked-by: Jani Nikula
on the series.
> - select BACKLIGHT_CLASS_DEVICE if ACPI
> - select INPUT if ACPI
> - select ACPI_VIDEO if ACPI
> - select ACPI_BUTTON if ACPI
> select SYNC_FILE
> select IOSF_MBI
> select CRC32
--
Jani Nikula, Intel Open Source Graphics Center
The PPS, RC_RANGE_PARAM, and RC_BUF_THRESH logging are clearly for
debugging, and should not be info level messages.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu
On Wed, 27 Oct 2021, Ville Syrjälä wrote:
> On Tue, Oct 26, 2021 at 02:01:15PM +0300, Jani Nikula wrote:
>> On Mon, 25 Oct 2021, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Looks like we never updated intel_bios_is_port_dp_dual_mode() when
>>
gt; *intel_dp)
>> static bool
>> transcoder_has_psr2(struct drm_i915_private *dev_priv, enum
>> transcoder trans)
>> {
>> -if (DISPLAY_VER(dev_priv) >= 12)
>> +if (IS_ALDERLAKE_P(dev_priv))
>> +return trans <= TRANSCODER_
On Wed, 27 Oct 2021, "Tolakanahalli Pradeep, Madhumitha"
wrote:
> On Mon, 2021-07-05 at 13:28 +0300, Jani Nikula wrote:
>> On Tue, 29 Jun 2021, "Souza, Jose" wrote:
>> > On Mon, 2021-06-28 at 16:50 -0700, Madhumitha Tolakanahalli Pradeep
>>
an't actually fix it until such a merge
exists somewhere more permanent than an ephemeral integration branch.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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