[Intel-gfx] [PATCH 02/14] drm/i915: Add support for TEAR ON Sequence

For command mode panel, panel's fb enabling and tearing configuration is done as part of TEAR ON sequence. This patch parses and executes TEAR ON sequence for MIPI command mode. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- driver

[Intel-gfx] [PATCH 09/14] drm/i915: Changes for command mode preparation

Changes done in preparation of command mode- 1. Set DBI HS LS Switch bit for DBI packets to be tramitted in HS mode. 2. Set DBI FIFO watermark. 3. Timing regs need not be programmmed for command mode. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit

[Intel-gfx] [PATCH 04/14] drm/i915: Calculate bw timer for mipi DBI interface

This patch will calculate the bandwidth timer for MIPI DBI interface. If the BW timer value is available from VBT, then value from VBT will be used. Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 24

[Intel-gfx] [PATCH 01/14] drm/i915: allocate DMA region for mipi dbi cmd buffer

Allocate DMA region for MIPI DBI command buffer. This memory will be used when sending command via DBI interface. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu --- drivers/gpu/drm/i915/intel_dsi.c | 17 + drivers/gpu/drm/i915/intel_dsi.h |2 ++ 2

[Intel-gfx] [PATCH 03/14] drm/i915: Add functions for dcs memory write cmd

Add functions for DCS memory write command. The mem write command to send fb data to panel is sent using this function. Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915

[Intel-gfx] [PATCH 00/14] DSI Command mode(DBI mode) enabling on CHT

. Floating the command mode enabling patches separately to start with the review. These patches have been rebased on top of BXT MIPI, BXT dual link changes. Regards Gaurav Gaurav K Singh (14): drm/i915: allocate DMA region for mipi dbi cmd buffer drm/i915: Add support for TEAR ON Sequence drm/i915

[Intel-gfx] [PATCH 08/14] drm/i915: Disable Tearing effect trigger by GPIO pin

While disabling MIPI Port in command mode, disable TE trigger by GPIO pin. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c |8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a

[Intel-gfx] [RFC 04/14] drm/i915: Calculate bw timer for mipi DBI interface

This patch will calculate the bandwidth timer for MIPI DBI interface. If the BW timer value is available from VBT, then value from VBT will be used. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 24

[Intel-gfx] [RFC 00/14] DSI Command mode(DBI mode) enabling on CHT

command mode patches separately to start with the initial review. Regards Gaurav Gaurav K Singh (14): drm/i915: allocate gem memory for mipi dbi cmd buffer drm/i915: Add support for TEAR ON Sequence drm/i915: Add functions for dcs memory write cmd drm/i915: Calculate bw timer for mipi DBI

[Intel-gfx] [RFC 03/14] drm/i915: Add functions for dcs memory write cmd

Add functions for DCS memory write command. The mem write command to send fb data to panel is sent using this function. Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar Signed-off-by: Yogesh Mohan Marimuthu --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915

[Intel-gfx] [RFC 02/14] drm/i915: Add support for TEAR ON Sequence

For command mode panel, panel's fb enabling and tearing configuration is done as part of TEAR ON sequence. This patch parses and executes TEAR ON sequence for MIPI command mode. Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar Signed-off-by: Yogesh Mohan Marimuthu --- driver

[Intel-gfx] [RFC 01/14] drm/i915: allocate gem memory for mipi dbi cmd buffer

Allocate gem memory for MIPI DBI command buffer. This memory will be used when sending command via DBI interface. Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 31

[Intel-gfx] [RFC 08/14] drm/i915: Disable Tearing effect trigger by GPIO pin

While disabling MIPI Port in command mode, disable TE trigger by GPIO pin. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c |8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a

[Intel-gfx] [RFC 07/14] drm/i915: Disable MIPI display self refresh mode

During disable sequence for MIPI encoder in command mode, disable MIPI display self-refresh mode bit in Pipe Ctrl reg. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_display.c | 13 + 1 file changed

[Intel-gfx] [RFC 06/14] drm/i915: Disable vlank interrupt for disabling MIPI cmd mode

next enable sequence causing display blank out. Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/intel_dsi.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c

[Intel-gfx] [RFC 05/14] drm/i915: Use the bpp value wrt the pixel format

The bpp value which is used while calulating the txbyteclkhs values should be wrt the pixel format value. Currently bpp is coming from pipe config to calculate txbyteclkhs. Signed-off-by: Gaurav K Singh Signed-off-by: Deepak M Signed-off-by: Yogesh Mohan Marimuthu --- drivers/gpu/drm/i915

[Intel-gfx] [RFC 10/14] drm/i915: Enable Tearing effect trigger by GPIO pin

While enabling MIPI Port in command mode, enable tearing effect by GPIO pin. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a

[Intel-gfx] [RFC 13/14] drm/i915: Reset the display hw if vid mode to cmd mode

Reset the display hardware if video mode to command mode transition has to be done in MIPI display. otherwise command mode will not work. Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [RFC 09/14] drm/i915: Changes for command mode preparation

Changes done in preparation of command mode- 1. Set DBI HS LS Switch bit for DBI packets to be tramitted in HS mode. 2. Set DBI FIFO watermark. 3. Timing regs need not be programmmed for command mode. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit

[Intel-gfx] [RFC 11/14] drm/i915: Enable MIPI display self refresh mode

During enable sequence for MIPI encoder in command mode, enable MIPI display self-refresh mode bit in Pipe Ctrl reg. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_display.c | 15 +++ 1 file changed

[Intel-gfx] [RFC 14/14] drm/i915: send one frame after enabling mipi cmd mode

mode set and no frames are sent. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu --- drivers/gpu/drm/i915/intel_display.c | 46 ++ drivers/gpu/drm/i915/intel_drv.h |6 + 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm

[Intel-gfx] [RFC 12/14] drm/i915: Generalize DSI enable function

For command mode and video mode, panel prepare, wait for FIFO checks are required. Making these changes generic across command mode and video mode. Signed-off-by: Gaurav K Singh Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 11

[Intel-gfx] [PATCH] drm/i915: Support for higher DSI clk

For MIPI panels requiring higher DSI clk, values needs to be added in lfsr_converts table for getting the correct values of pll ctrl and dividor values which gets programmed in cck regs, otherwise DSI PLL does not get locked leading to no display on the MIPI panel. Signed-off-by: Gaurav K Singh

[Intel-gfx] [PATCH] drm/i915: Allow DSI dual link to be configured on any pipe

: Jani Nikula Date: Fri Jan 16 14:27:23 2015 +0200 drm/i915/dsi: add drm mipi dsi host support Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/intel_dsi.c |9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 6/9] drm/i915: Dsipll clk to be enabled for DSI1 in case of dual link configuration

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi_pll.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index fa7a6ca..2464089 100644

[Intel-gfx] [PATCH 7/9] drm/i915: MIPI Timings related changes for dual link Configuration

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 37 +++-- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 583c7fd

[Intel-gfx] [PATCH 0/9] BYT DSI Dual Link Support

Hi, These set of patches build on top of the existing DSI Video mode support to enable dual link MIPI panels with high resolutions. These patches have been tested on a 25x16 panel and works well. Regards Gaurav Gaurav K Singh (9): drm/i915: New functions added for enabling & disabling

[Intel-gfx] [PATCH 8/9] drm/i915: MIPI encoder disable related changes for dual link Configuration

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 74 -- 1 file changed, 48 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 6aac420

[Intel-gfx] [PATCH 4/9] drm/i915: Pixel Clock and pixel overlap related changes for dual link Configuration

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/i915_reg.h|4 drivers/gpu/drm/i915/intel_bios.h |3 ++- drivers/gpu/drm/i915/intel_dsi.c |8 drivers/gpu/drm/i915/intel_dsi.h |6

[Intel-gfx] [PATCH 2/9] drm/i915: MIPI Sequence to be sent to the DSI Controller based on the port no from VBT

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.h |1 + drivers/gpu/drm/i915/intel_dsi_cmd.c |9 +++-- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |3 +++ 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a

[Intel-gfx] [PATCH 5/9] drm/i915: SHUTDOWN & Turn ON packets to be sent for both MIPI Ports in case of dual link Configuration

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi_cmd.c | 35 ++ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c index

[Intel-gfx] [PATCH 9/9] drm/i915: MIPI Encoder enable related changes for dual link configuration

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 276 ++ 1 file changed, 161 insertions(+), 115 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 477b79d

[Intel-gfx] [PATCH 1/9] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg

This patch is in preparation for the dual link port enable and disable related changes. Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 43 -- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git

[Intel-gfx] [PATCH 3/9] drm/i915: MIPI Port Ctrl related changes for dual link configuration

Signed-off-by: Gaurav K Singh Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/i915_reg.h|1 + drivers/gpu/drm/i915/intel_dsi.c | 53 ++-- drivers/gpu/drm/i915/intel_dsi.h |1 + drivers/gpu/drm/i915/intel_dsi_panel_vbt.c

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