As an enhancement of dsb multi instance support added which can be
used by color framework for big lut programming in future.
Signed-off-by: Animesh Manna
Animesh Manna (3):
drm/i915/dsb: multi dsb instance support in prepare() and cleanup()
drm/i915/dsb: multi dsb instance support in dsb
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 40 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 8 ++---
drivers/gpu/drm/i915/display/intel_dsb.h | 4 +--
3 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 99 ++-
4 files changed, 65
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 74 +---
1 file changed, 39 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index c968c9785484..b3f1cc1652b8 100644
As an enhancement of dsb multi instance support added which can be
used by color framework for big lut programming in future.
Signed-off-by: Animesh Manna
Animesh Manna (3):
drm/i915/dsb: multi dsb instance support in prepare() and cleanup()
drm/i915/dsb: multi dsb instance support in dsb
To support multiple dsb instances per pipe dsb-id is passed
as argumnet in dsb-write() which will write into respective
dsb cmd-buffer.
v1: Initial version.
v2: Improved commit description.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 40
Command buffer allocation is done for all 3 dsb instances for every
pipe and cleanup code is modified accordingly.
v1: Initial version.
v2: Improved commit description.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 +-
drivers/gpu/drm/i915/display
To support multiple dsb instances per pipe dsb-id is passed
as argumnet in dsb-commit() and respective cmd-buffer will
be updated in actual hardware.
v1: Initial version.
v2: Improved commit description.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 74
due to unavailability of monitor
Animesh Manna (4):
drm/i915/panelreplay: HAS_PR() macro added for panel replay
drm/i915/panelreplay: Initializaton and compute config for panel
replay
drm/i915/panelreplay: enable/disable panel replay
drm/i915/panelreplay: Added state checker for panel
Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a HAS_PR() macro
to check for panel replay capability.
v1: Initial version.
v2: DISPLAY_VER macro used instead of has_pr flag. [Jose]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.
v1: RFC version.
v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 2
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 30
drivers/gpu/drm/i915/i915_reg.h | 1
has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu
due to unavailability of monitor
Animesh Manna (5):
drm/i915/panelreplay: dpcd register definition for panelreplay
drm/i915/panelreplay: HAS_PR() macro added for panel replay
drm/i915/panelreplay: Initializaton and compute config for panel
replay
drm/i915/panelreplay: enable/disable panel
DPCD register definition added to check and enable panel replay
capability of the sink.
Signed-off-by: Animesh Manna
---
include/drm/drm_dp_helper.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b52df4db3e8f
: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f..37313bf51a90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1693,6
]
- panel-repaplay init/compute functions moved inside respective psr
function. [Jani]
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 43 +
drivers/gpu/drm/i915/display/intel_psr.c | 48
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 30
drivers/gpu/drm/i915/i915_reg.h | 1
has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.
v1: RFC version.
v2: has_panel_replay flag updated as per hw readout. [Jani]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display
d-off-by: Jani Nikula
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 ++---
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 75d4ebc66941..4df56
): Up to HBR3 for higher Vccio.
Some condition added during max rate calculation in this patch series
based on above conditions.
Animesh Manna (2):
drm/i915/dp: fix EHL/JSL max source rates calculation
drm/i915/dp: fix for ADL_P/S and DG2 dp/edp max source rates
Jani Nikula (2):
drm/i915/dp
From: Jani Nikula
Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.
Bspec: 20584, 20598, 49180, 49201
Cc: Imre Deak
Signed-off-by: Jani Nikula
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c
Only higher voltage sku can support HBR3 so a condition
check added in max source rate calculation for ehl/jsl.
Bspec: 32247, 20598
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion
Added support for platforms having DISPLAY13 like DG2, ADL_P and ADL_S.
Bspec: 53597, 53720, 53657, 54034, 49185, 55409
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
From: Jani Nikula
Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP
can do 8.1 GHz on combo phy.
Bspec: 49182, 49205, 49202
Cc: Imre Deak
Signed-off-by: Jani Nikula
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +++-
1 file
): Up to HBR3 for higher Vccio.
Some condition added during max rate calculation in this patch series
based on above conditions.
Animesh Manna (2):
drm/i915/dp: fix EHL/JSL max source rates calculation
drm/i915/dp: fix for ADL_P/S dp/edp max source rates
Jani Nikula (2):
drm/i915/dp: fix TGL
d-off-by: Jani Nikula
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 ++---
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
ind
From: Jani Nikula
Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.
Bspec: 20584, 20598, 49180, 49201
Cc: Imre Deak
Signed-off-by: Jani Nikula
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm
From: Jani Nikula
Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP
can do 8.1 GHz on combo phy.
Bspec: 49182, 49205, 49202
Cc: Imre Deak
Signed-off-by: Jani Nikula
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 14
Only higher voltage sku can support HBR3 so a condition
check added in max source rate calculation for ehl/jsl.
Bspec: 32247, 20598
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 6
Added HBR3 support for ADL_P and ADL_S platform.
Bspec: 53597, 53720, 49185, 55409
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Animesh Manna
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
due to unavailability of monitor
Animesh Manna (5):
drm/i915/panelreplay: update plane selective fetch register definition
drm/i915/panelreplay: Feature flag added for panel replay
drm/i915/panelreplay: Initializaton and compute config for panel
replay
drm/i915/panelreplay: enable/disable
Panel replay can be enabled for all pipes driving DP 2.0 monitor,
so updated the plane selective fetch register difinition accordingly.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 8 +++---
drivers/gpu/drm/i915/i915_reg.h | 32
Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a feature flag
for panel replay.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915
As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 4 ++
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++
drivers/gpu
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 30
drivers/gpu/drm/i915/i915_reg.h | 1
has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can be derived through vma object. (Chris)
v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915
Thierry
Cc: Uma Shankar
Cc: Shashank Sharma
Cc: Swati Sharma
Cc: Lucas De Marchi
Signed-off-by: Animesh Manna
Animesh Manna (10):
drm/i915/dsb: feature flag added for display state buffer.
drm/i915/dsb: DSB context creation.
drm/i915/dsb: single register write function for DSB.
drm
code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display/intel_dsb.h | 1
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gpu/drm/i915
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index
)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 29
drivers/gpu/drm/i915/display/intel_dsb.h | 9
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers
comment. (Shashank)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 64
drivers/gpu/drm/i915/display/intel_dsb.h | 8 +++
2 files changed, 72 insertions(+)
diff --git a
-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 64 ++
drivers/gpu/drm/i915/i915_drv.h| 2 +
2 files changed, 43 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915
register. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm
Hi,
On 8/30/2019 7:05 PM, Jani Nikula wrote:
On Fri, 30 Aug 2019, Animesh Manna wrote:
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine
Hi,
On 9/3/2019 1:38 PM, Jani Nikula wrote:
On Fri, 30 Aug 2019, Jani Nikula wrote:
On Fri, 30 Aug 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio
Hi,
On 8/30/2019 7:02 PM, Jani Nikula wrote:
On Fri, 30 Aug 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
v1: Initial version
: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Imre Deak
Cc: Michel Thierry
Cc: Uma Shankar
Cc: Shashank Sharma
Cc: Swati Sharma
Cc: Lucas De Marchi
Signed-off-by: Animesh Manna
Animesh Manna (11):
drm/i915/dsb: feature flag added for display state buffer.
drm/i915/dsb: DSB context creation.
drm
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu
: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dsb.c | 70 +++
drivers/gpu/drm
comment. (Shashank)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 64
drivers/gpu/drm/i915/display/intel_dsb.h | 8 +++
2 files changed, 72 insertions(+)
diff --git a
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers
)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 30
drivers/gpu/drm/i915/display/intel_dsb.h | 9 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
The lifetime of command buffer can be controlled by the dsb user
throuh refcount. Added refcount mechanism is dsb get/put call
which create/destroy dsb context.
Cc: Jani Nikula
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 22
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm
code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 63 ++
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index
register. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 43 insertions(+)
diff --git
On 9/9/2019 6:26 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+if (!
On 9/9/2019 6:28 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the
On 9/9/2019 6:43 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed
On 9/9/2019 6:51 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
The lifetime of command buffer can be controlled by the dsb user
throuh refcount. Added refcount mechanism is dsb get/put call
which create/destroy dsb context.
Cc: Jani Nikula
Cc: Shashank Sharma
: Check DSB engine status.
On 9/9/2019 6:43 PM, Sharma, Shashank wrote:
On 9/7/2019 4:37 PM, Animesh Manna wrote:
+#define _DSBSL_INSTANCE_BASE0x70B00
+#define DSBSL_INSTANCE(pipe, id)(_DSBSL_INSTANCE_BASE + \
+ (pipe) * 0x1000 + (id) * 100)
Why is pipe in () ?
mmio
On 9/7/2019 10:44 PM, Anshuman Gupta wrote:
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Hi,
On 9/7/2019 10:44 PM, Anshuman Gupta wrote:
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers
code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display
dropping ref-count implementation. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 57 +-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Imre Deak
Cc: Michel Thierry
Cc: Uma Shankar
Cc: Shashank Sharma
Cc: Swati Sharma
Cc: Lucas De Marchi
Signed-off-by: Animesh Manna
Animesh Manna (10):
drm/i915/dsb: feature flag added for display state buffer
cmd_buf moved outside of mutex in dsb-put(). (Shashank)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu
comment. (Shashank)
v4: cosmetic changes done. (Shashank)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 65
drivers/gpu/drm/i915/display/intel_dsb.h | 8 +++
2 files
register. (Shashank)
v3: cosmetic changes done. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files
)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 30
drivers/gpu/drm/i915/display/intel_dsb.h | 9
On 9/12/2019 6:30 PM, Sharma, Shashank wrote:
On 9/12/2019 6:21 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, "Sharma, Shashank"
wrote:
On 9/12/2019 12:41 AM, Animesh Manna wrote:
DSB support single register write through opcode 0x1. Generic
api created which accumulate all singl
On 9/12/2019 6:37 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for
: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..6bfebab9a441 100644
--- a/drivers/gpu
. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a
On 9/17/2019 1:00 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, Animesh Manna wrote:
On 9/12/2019 6:37 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write
comment. (Shashank)
v4: cosmetic changes done. (Shashank)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 66
drivers/gpu/drm/i915/display
cmd_buf moved outside of mutex in dsb-put(). (Shashank)
v6:
- refcount machanism added.
- Used atomic_add_return and atomic_dec_and_test instead of
atomic_inc and atomic_dec. (Jani)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display
register. (Shashank)
v3: cosmetic changes done. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
drivers/gpu/drm/i915
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
v4: macro of indexed-write is moved. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h
.
v7: Addressed review commnets from Shashank and Jani.
Animesh Manna (10):
drm/i915/dsb: feature flag added for display state buffer.
drm/i915/dsb: DSB context creation.
drm/i915/dsb: single register write function for DSB.
drm/i915/dsb: Indexed register write function for DSB.
drm/i915
code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 42
drivers/gpu/drm/i915/display
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
dropping ref-count implementation. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 63 ++
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
comment. (Shashank)
v4: cosmetic changes done. (Shashank)
v5: reset ins_start_offset. (Jani)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 67
)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
v4: macro of indexed-write is moved. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display
.
v7: Addressed review commnets from Shashank and Jani.
v8: Addressed review commnets from Shashank and Jani.
Animesh Manna (10):
drm/i915/dsb: feature flag added for display state buffer.
drm/i915/dsb: DSB context creation.
drm/i915/dsb: single register write function for DSB.
drm/i915
1 - 100 of 679 matches
Mail list logo
