[Intel-gfx] [PATCH 4/5] drm/i915/dp: fix DG1 and RKL max source rates

[Animesh Manna]

From: Jani Nikula <jani.nik...@intel.com>

Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP
can do 8.1 GHz on combo phy.

Bspec: 49182, 49205, 49202

Cc: Imre Deak <imre.d...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Animesh Manna <animesh.ma...@intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5aabd8ec1015..3fe1158706d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -325,6 +325,18 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
        return 810000;
 }
 
+static int dg1_max_source_rate(struct intel_dp *intel_dp)
+{
+       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+       struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+       enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+       if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
+               return 540000;
+
+       return 810000;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -360,6 +372,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
                size = ARRAY_SIZE(icl_rates);
                if (IS_DG2(dev_priv))
                        max_rate = dg2_max_source_rate(intel_dp);
+               else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+                       max_rate = dg1_max_source_rate(intel_dp);
                else if (IS_JSL_EHL(dev_priv))
                        max_rate = ehl_max_source_rate(intel_dp);
                else
-- 
2.29.0