[Intel-gfx] [PATCH 2/5] drm/i915/dp: fix TGL and ICL max source rates

[Animesh Manna]

From: Jani Nikula <jani.nik...@intel.com>

Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.

Bspec: 20584, 20598, 49180, 49201

Cc: Imre Deak <imre.d...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Animesh Manna <animesh.ma...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4df56af36b3f..42b29948bc72 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -224,6 +224,15 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
                 encoder->port != PORT_A);
 }
 
+static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
+{
+       u32 voltage;
+
+       voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & 
VOLTAGE_INFO_MASK;
+
+       return voltage == VOLTAGE_INFO_0_85V;
+}
+
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -231,7 +240,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
        enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
        if (intel_phy_is_combo(dev_priv, phy) &&
-           !intel_dp_is_edp(intel_dp))
+           (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
                return 540000;
 
        return 810000;
-- 
2.29.0