On Mon, 27 Jan 2025, Gustavo Sousa wrote:
> Quoting Jani Nikula (2025-01-27 06:47:58-03:00)
>>On Fri, 17 Jan 2025, Gustavo Sousa wrote:
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>> b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>>> index 5488fbdf29b8..d11b0ab50b3c 100644
>>> -
On Mon, 27 Jan 2025, Jani Nikula wrote:
> On Fri, 17 Jan 2025, Gustavo Sousa wrote:
>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>> debugfs is not in use introduces a small but unnecessary pena
On Fri, 17 Jan 2025, Gustavo Sousa wrote:
> We use a spinlock to protect DMC wakelock debugfs data, since it is also
> accessed by the core DMC wakelock logic. Taking the spinlock when the
> debugfs is not in use introduces a small but unnecessary penalty.
>
> Since the debugfs functionality is on
Quoting Jani Nikula (2025-01-27 08:59:11-03:00)
>On Mon, 27 Jan 2025, Gustavo Sousa wrote:
>> Quoting Jani Nikula (2025-01-27 06:47:58-03:00)
>>>On Fri, 17 Jan 2025, Gustavo Sousa wrote:
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
b/drivers/gpu/drm/i915/display/intel_dmc_w
On Mon, 27 Jan 2025, Gustavo Sousa wrote:
> Quoting Jani Nikula (2025-01-27 10:35:57-03:00)
>>On Mon, 27 Jan 2025, Gustavo Sousa wrote:
>>> Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
On Fri, 17 Jan 2025, Gustavo Sousa wrote:
> We use a spinlock to protect DMC wakelock debugfs data,
Hi Zhanjun
There is a missing newline at drm-tip/drivers/gpu/drm/i915/gt/intel_rps.c:249
Overall, LGTM.
On Thu Jan 23, 2025 at 4:23 PM UTC, Zhanjun Dong wrote:
> The purpose of synchronize_irq is to wait for any pending IRQ handlers for the
> interrupt to complete, if synchronize_irq called befor
On Fri, 2025-01-24 at 14:49 +0200, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 12:41:11PM +, Hogander, Jouni wrote:
> > On Fri, 2025-01-24 at 14:37 +0200, Ville Syrjälä wrote:
> > > On Fri, Jan 24, 2025 at 11:57:10AM +, Hogander, Jouni wrote:
> > > > On Fri, 2025-01-24 at 13:39 +0200, Vi
On Mon, 27 Jan 2025, Joel Granados wrote:
> On Wed, Jan 22, 2025 at 01:41:35PM +0100, Ard Biesheuvel wrote:
>> On Wed, 22 Jan 2025 at 13:25, Joel Granados wrote:
>> >
>> > On Tue, Jan 21, 2025 at 02:40:16PM +0100, Alexander Gordeev wrote:
>> > > On Fri, Jan 10, 2025 at 03:16:08PM +0100, Joel Gran
On Wed, 22 Jan 2025 07:22:25 +0200
Raag Jadav wrote:
> On Tue, Jan 21, 2025 at 02:14:56AM +0100, Xaver Hugl wrote:
> > > +It is the responsibility of the consumer to make sure that the device or
> > > +its resources are not in use by any process before attempting recovery.
> > I'm not convinced
== Series Details ==
Series: PSR DSB support (rev7)
URL : https://patchwork.freedesktop.org/series/142520/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unr
Quoting Patchwork (2025-01-25 06:22:24-03:00)
>== Series Details ==
>
>Series: drm/i915/cmtg: Disable the CMTG (rev9)
>URL : https://patchwork.freedesktop.org/series/142947/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_16018_full -> Patchwork_142947v9_full
>==
== Series Details ==
Series: PSR DSB support (rev7)
URL : https://patchwork.freedesktop.org/series/142520/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16023 -> Patchwork_142520v7
Summary
---
**FAILURE**
Serious
Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
>On Fri, 17 Jan 2025, Gustavo Sousa wrote:
>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>> debugfs is not in use introduces a small but unnecessar
== Series Details ==
Series: drm/i915/selftests: avoid using uninitialized context
URL : https://patchwork.freedesktop.org/series/143990/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16023 -> Patchwork_143990v1
Summary
---
Quoting Patchwork (2025-01-24 18:22:41-03:00)
>== Series Details ==
>
>Series: drm/i915/dmc_wl: Do not check for DMC payload
>URL : https://patchwork.freedesktop.org/series/143951/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_16018 -> Patchwork_143951v1
>=
On Mon, 27 Jan 2025, Gustavo Sousa wrote:
> Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
>>On Fri, 17 Jan 2025, Gustavo Sousa wrote:
>>> We use a spinlock to protect DMC wakelock debugfs data, since it is also
>>> accessed by the core DMC wakelock logic. Taking the spinlock when the
>>> debugf
Quoting Jani Nikula (2025-01-27 06:47:58-03:00)
>On Fri, 17 Jan 2025, Gustavo Sousa wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>> index 5488fbdf29b8..d11b0ab50b3c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>
There is an error path in igt_ppgtt_alloc(), which leads to ww
object being passed down to i915_gem_ww_ctx_fini() without
initialization. Correct that by zeroing the struct.
Fixes: 480ae79537b2 ("drm/i915/selftests: Prepare gtt tests for obj->mm.lock
removal")
Signed-off-by: Krzysztof Karas
---
Hi Sebastian,
On 2025-01-23 at 14:38:40 GMT, Sebastian Brzezinka wrote:
> This reverts commit 835443da6f50d9516b58bba5a4fdf9e563d961c7.
>
> - turns out that logging with gt_err() causes CI to pick up an error
> even in intentional error injects,
> - the unintentional (real) errors are already r
Hi Sebastian,
> This reverts commit 835443da6f50d9516b58bba5a4fdf9e563d961c7.
>
> - turns out that logging with gt_err() causes CI to pick up an error
> even in intentional error injects,
> - the unintentional (real) errors are already reported correctly by CI,
> - a gt wedge is already being l
On Wed, Jan 22, 2025 at 01:41:35PM +0100, Ard Biesheuvel wrote:
> On Wed, 22 Jan 2025 at 13:25, Joel Granados wrote:
> >
> > On Tue, Jan 21, 2025 at 02:40:16PM +0100, Alexander Gordeev wrote:
> > > On Fri, Jan 10, 2025 at 03:16:08PM +0100, Joel Granados wrote:
> > >
> > > Hi Joel,
> > >
> > > > Ad
Quoting Jani Nikula (2025-01-27 10:35:57-03:00)
>On Mon, 27 Jan 2025, Gustavo Sousa wrote:
>> Quoting Jani Nikula (2025-01-27 09:01:39-03:00)
>>>On Fri, 17 Jan 2025, Gustavo Sousa wrote:
We use a spinlock to protect DMC wakelock debugfs data, since it is also
accessed by the core DMC wa
Hi CI-infra team,
below failure is unrelated to my patch.
Krzysztof
On 2025-01-27 at 13:22:27 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/selftests: avoid using uninitialized context
> URL : https://patchwork.freedesktop.org/series/143990/
> State : failure
>
> == Sum
Add utils and gt-c6 tests that utilize PMU counters.
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (2):
lib/igt_perf: Add utils to extract PMU event info
tests/xe/pmu: Add pmu tests
lib/igt_perf.c | 74 +
lib/igt_perf.h
Functions to parse event ID and GT bit shift for PMU events.
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
lib/igt_perf.c | 68 ++
lib/igt_perf.h | 2 ++
2 files changed, 70 insertions(+)
diff --g
Hi Vinay
On 1/27/2025 1:44 PM, Vinay Belgaumkar wrote:
Functions to parse event ID and GT bit shift for PMU events.
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
lib/igt_perf.c | 68 ++
lib/igt
This patch set is doing necessary modifications to support PSR update
using DSB on LunarLake onwards
It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP
sleep at the begin of commit This is left out from DSB commit. There
might be room for optimization for non-DSB as well because suc
We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.
It shouldn't be necessary to have SFF bit set if CFF bit is set in
PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not
reason t
In LunarLake we have SFF_CTL register which contains SFF bit ored with
respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead
of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This
helps us avoiding taking psr mutex when performing atomic commit.
We don't need t
PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
wake-up scanline counting starts from vblank_start - 1. We don't know if
wake-up is already ongoing when evasion starts. In worst case PIPEDSL could
start reading valid value right after checking the scanline. In this
scenario we
We may have commit which doesn't have any non-arming plane register
writes. In that case there aren't "Frame Change" event before DSB vblank
evasion which hangs as PIPEDSL register is reading as 0 when PSR state is
SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by ensuring "Frame Change"
event at th
Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do
not check intel_dp->psr.lock being held when using DSB. This assertion
doesn't make sense as in case of using DSB the actual write happens later
and we are not taking intel_dp->psr.lock mutex over dsb commit.
Signed-off-by: J
Add new function to trigger "Frame Change" event for ensuring we are waking
up before vblank evasion.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 22 ++
drivers/gpu/drm/i915/display/intel_psr.h | 3 +++
2 files changed, 25 insertions(+)
diff
Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use:
1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using
DSB.
2. Add PSR2_MAN_TRK_CTL writing into DSB commit in
intel_atomic_dsb_finish.
Taking PSR lock over DSB commit is not needed because PSR2_MAN_
We have different approach on how flip is considered being complete. We are
waiting for vblank on DSB and generate interrupt when it happens and this
interrupt is considered as indication of completion -> we definitely do not
want to skip vblank wait.
Also not skipping scanline wait shouldn't caus
This is a clean-up and a preparation for adding own SFF and CFF registers
for LunarLake onwards.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 88 +---
1 file changed, 31 insertions(+), 57 deletions(-)
diff --git a/d
Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
usage also when PSR is enabled for LunarLake onwards.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
dif
psr_force_hw_tracking_exit is misleading name as it is used for PSR1, PSR2
HW tracking and PSR2 selective fetch. Due to this rename it as
intel_psr_force_update.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
1 file changed, 4
Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
LNL_SFF_CTL and LNL_CFF_CTL.
v2: use _MMIO_TRANS instead of _MMIO_TRANS2
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++
1 file changed, 10 inser
Hi Vinay
On 1/27/2025 1:44 PM, Vinay Belgaumkar wrote:
Simple tests for validating the PMU implementation for GT C6
residencies.
These tests validate the kernel series which is currently in review
here - https://patchwork.freedesktop.org/series/139121/
v2: Rename rc6-residency-* to gt-c6-resid
On Fri, 17 Jan 2025, Gustavo Sousa wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> index 5488fbdf29b8..d11b0ab50b3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h
>
On Wed, 22 Jan 2025, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we don't account for the VT-d alignment w/a in
> plane->min_alignment() which means that panning inside a larger
> framebuffer can still cause the plane SURF to be misaligned.
> Fix the issue by moving the VT-d alignmen
Simple tests for validating the PMU implementation for GT C6
residencies.
These tests validate the kernel series which is currently in review
here - https://patchwork.freedesktop.org/series/139121/
v2: Rename rc6-residency-* to gt-c6-residency and remove freq tests.
v3: Keep just gt-c6 tests, add
Hi Zhanjun,
On Thu, Jan 23, 2025 at 08:23:51AM -0800, Zhanjun Dong wrote:
> The purpose of synchronize_irq is to wait for any pending IRQ handlers for the
> interrupt to complete, if synchronize_irq called before interrupt disabled, an
> tiny timing window created, where no more pending IRQ, but i
On Mon, Jan 27, 2025 at 04:55:58PM +0200, Jani Nikula wrote:
> You could have static const within functions too. You get the rodata
> protection and function local scope, best of both worlds?
timer_active is on the stack, so it can't be static const.
Does this really need to be cc'd to such a wid
On 1/23/2025 8:23 AM, Zhanjun Dong wrote:
The purpose of synchronize_irq is to wait for any pending IRQ handlers for the
interrupt to complete, if synchronize_irq called before interrupt disabled, an
tiny timing window created, where no more pending IRQ, but interrupt not
disabled yet. Meanwh
From: Ville Syrjälä
Pull the code linking the UV and Y planes together into a
sensible function instead of having the code plastered inside
the higher level loop.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 83 +++-
1 file changed, 47 inserti
From: Ville Syrjälä
All the this generic 'plane' vs 'linked' stuff is hard to
follow. Rename the variables to use the y_plane vs. uv_plane
terminology to make it clear which is which.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 107 ++-
1 fil
From: Ville Syrjälä
Try to keep all the low level skl+ universal plane register
details inside skl_universal_plane.c instead of having them
sprinkled all over the place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 30 -
.../drm/i915/display/
From: Ville Syrjälä
The current code tries to handle joiner vs. Y planes completely
independently. That does not really work since each pipe selects
its Y planes completely independently, and any plane pulled into
the state by one of the secondary pipes needs to have the plane
on the primary pipe
From: Ville Syrjälä
Bspec talks about Y planes, not planar slaves. Switch to using the
same erminology to make life a bit less confusing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display.c| 8 +++
From: Ville Syrjälä
I wanted to reorganize the Y plane code, but then I
realized it still has real issued, espectially when it comes
to joiner usage. So fix the bugs first, then do the code
reorganization.
Ville Syrjälä (11):
drm/i915: Make sure all planes in use by the joiner have their crtc
From: Ville Syrjälä
This reverts commit 1d5b09f8daf859247a1ea65b0d732a24d88980d8.
Now that the root cause the missing crtc state has been fixed
we can get rid of the duct tape.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
1 file changed, 1 inserti
From: Ville Syrjälä
Any active plane needs to have its crtc included in the atomic
state. For planes enabled via uapi that is all handler in the core.
But when we use a plane for joiner the uapi code things the plane
is disabled and therefore doesn't have a crtc. So we need to pull
those in by ha
From: Ville Syrjälä
Use the standard [PLANE:%d:%s] stuff for the Y plane debugs,
and more clearly spell out which plane is UV plane and which
is Y plane when linking them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 +---
1 file changed, 5 inserti
From: Ville Syrjälä
Pull the details of the nv12 plane unlinking to a small
funciton to make the higher level code less messy.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git
From: Ville Syrjälä
visible can't be true when is_y_plane is true. Replace the
bogus check with an WARN_ON(). Flatten the function while
at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-
From: Ville Syrjälä
Move all the intel_atomic_check_planes() machinery into
intel_atomic_plane.c in order to declutter intel_display.c.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 293 ++
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +
On Mon, Jan 27, 2025 at 1:47 PM Ville Syrjälä
wrote:
>
> On Thu, Jan 16, 2025 at 10:53:40AM -0500, Brian Geffon wrote:
> > When converting to folios the cleanup path of shmem_get_pages() was
> > missed. When a DMA remap fails and the max segment size is greater than
> > PAGE_SIZE it will attempt t
When converting to folios the cleanup path of shmem_get_pages() was
missed. When a DMA remap fails and the max segment size is greater than
PAGE_SIZE it will attempt to retry the remap with a PAGE_SIZEd segment
size. The cleanup code isn't properly using the folio apis and as a
result isn't handlin
From: Ville Syrjälä
Currently we just define the display tracpoints with
TRACE_SYSTEM i915. However the code gets included separately
in i915 and xe, and now both modules are competing for the
same tracpoints. Apparently whichever module is loaded first
gets the tracepoints and the other guy is l
-Original Message-
From: Intel-gfx On Behalf Of Brian
Geffon
Sent: Monday, January 27, 2025 12:44 PM
To: intel-gfx@lists.freedesktop.org
Cc: Wilson, Chris P ; Saarinen, Jani
; Mistat, Tomasz ; Srinivas,
Vidya ; ville.syrj...@linux.intel.com;
jani.nik...@linux.intel.com; linux-ker...@vg
-Original Message-
From: Intel-xe On Behalf Of Ville
Syrjala
Sent: Monday, January 27, 2025 1:31 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel...@lists.freedesktop.org
Subject: [PATCH] drm/i915: Give i915 and xe each their own display tracepoints
>
> From: Ville Syrjälä
>
> Currentl
On Mon, Jan 27, 2025 at 11:50:34AM +0200, Jani Nikula wrote:
> On Wed, 22 Jan 2025, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we don't account for the VT-d alignment w/a in
> > plane->min_alignment() which means that panning inside a larger
> > framebuffer can still cause the
Hi Krzysztof,
On Mon Jan 27, 2025 at 11:46 AM UTC, Krzysztof Karas wrote:
> There is an error path in igt_ppgtt_alloc(), which leads to ww
> object being passed down to i915_gem_ww_ctx_fini() without
> initialization. Correct that by zeroing the struct.
>
> Fixes: 480ae79537b2 ("drm/i915/selftests
On Mon, Jan 27, 2025 at 06:44:21PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 27, 2025 at 11:50:34AM +0200, Jani Nikula wrote:
> > On Wed, 22 Jan 2025, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Currently we don't account for the VT-d alignment w/a in
> > > plane->min_alignment() w
On Thu, Jan 16, 2025 at 10:53:40AM -0500, Brian Geffon wrote:
> When converting to folios the cleanup path of shmem_get_pages() was
> missed. When a DMA remap fails and the max segment size is greater than
> PAGE_SIZE it will attempt to retry the remap with a PAGE_SIZEd segment
> size. The cleanup
On Sat, Jan 25, 2025 at 12:38:46AM +, li...@treblig.org wrote:
> From: "Dr. David Alan Gilbert"
>
> The last use of live_context_for_engine() was removed in 2021 by
> commit 99919be74aa3 ("drm/i915/gem: Zap the i915_gem_object_blt code")
>
> Remove it.
>
Reviewed-by: Rodrigo Vivi
> Signe
== Series Details ==
Series: drm/i915: replace in_atomic() with manually set flag (rev2)
URL : https://patchwork.freedesktop.org/series/143402/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Mon, Jan 27, 2025 at 07:25:31AM +, Borah, Chaitanya Kumar wrote:
> Hello Ville,
>
> > -Original Message-
> > From: Intel-xe On Behalf Of Murthy,
> > Arun R
> > Sent: Saturday, January 25, 2025 12:25 PM
> > To: Ville Syrjälä
> > Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.
== Series Details ==
Series: drm/i915: replace in_atomic() with manually set flag (rev2)
URL : https://patchwork.freedesktop.org/series/143402/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16026 -> Patchwork_143402v2
Summa
On Thu, Jan 23, 2025 at 10:16:07PM -0500, Rodrigo Vivi wrote:
> On Wed, Jan 22, 2025 at 01:15:31PM +0200, Giedrius Statkevičius wrote:
> > Hello,
> >
> > On Mon, 4 Nov 2024 at 23:28, Rodrigo Vivi wrote:
> > >
> > > On Mon, Nov 04, 2024 at 02:09:46PM +0200, Giedrius Statkevičius wrote:
> > > > Hel
== Series Details ==
Series: drm/i915: joiner and Y plane fixes and reorganization
URL : https://patchwork.freedesktop.org/series/144001/
State : warning
== Summary ==
Error: dim checkpatch failed
1419823e1d5f drm/i915: Make sure all planes in use by the joiner have their
crtc included
-:62:
Functions to parse event ID and GT bit shift for PMU events.
v2: Review comments (Riana)
Cc: Riana Tauro
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
lib/igt_perf.c | 70 ++
lib/igt_perf.h | 2 +
Simple tests for validating the PMU implementation for GT C6
residencies.
v2: Rename rc6-residency-* to gt-c6-residency and remove freq tests.
v3: Keep just gt-c6 tests, add frequency tests later.
Cc: Lucas De Marchi
Cc: Riana Tauro
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
tests/
Add utils and gt-c6 tests that utilize PMU counters.
Cc: Riana Tauro
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (2):
lib/igt_perf: Add utils to extract PMU event info
tests/xe/pmu: Add pmu tests
lib/igt_perf.c | 70
lib/
== Series Details ==
Series: drm/i915: joiner and Y plane fixes and reorganization
URL : https://patchwork.freedesktop.org/series/144001/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/a
== Series Details ==
Series: drm/i915: joiner and Y plane fixes and reorganization
URL : https://patchwork.freedesktop.org/series/144001/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16029 -> Patchwork_144001v1
Summary
---
Add utils and gt-c6 tests that utilize PMU counters.
Cc: Riana Tauro
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (2):
lib/igt_perf: Add utils to extract PMU event info
tests/xe/pmu: Add pmu tests
lib/igt_perf.c | 70 +
lib
Simple tests for validating the PMU implementation for GT C6
residencies.
v2: Rename rc6-residency-* to gt-c6-residency and remove freq tests.
v3: Keep just gt-c6 tests, add frequency tests later.
v4: Review comments (Riana)
Cc: Lucas De Marchi
Cc: Riana Tauro
Cc: Rodrigo Vivi
Signed-off-by: V
Functions to parse event ID and GT bit shift for PMU events.
v2: Review comments (Riana)
Cc: Riana Tauro
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
lib/igt_perf.c | 70 ++
lib/igt_perf.h | 2 +
On Mon, Jan 27, 2025 at 11:30:55PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Currently we just define the display tracpoints with
TRACE_SYSTEM i915. However the code gets included separately
in i915 and xe, and now both modules are competing for the
same tracpoints. Apparently whichever m
== Series Details ==
Series: drm/i915: Fix page cleanup on DMA remap failure (rev4)
URL : https://patchwork.freedesktop.org/series/143614/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16030 -> Patchwork_143614v4
Summary
--
== Series Details ==
Series: drm/i915/guc: Debug print LRC state entries only if the context is
pinned (rev4)
URL : https://patchwork.freedesktop.org/series/143361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16030 -> Patchwork_143361v4
=
> -Original Message-
> From: Cavitt, Jonathan
> Sent: 28 January 2025 02:45
> To: Brian Geffon ; intel-gfx@lists.freedesktop.org
> Cc: Wilson, Chris P ; Saarinen, Jani
> ; Mistat, Tomasz ;
> Srinivas, Vidya ; ville.syrj...@linux.intel.com;
> jani.nik...@linux.intel.com; linux-ker...@vger
On Sat, Jan 25, 2025 at 10:32:11AM -0600, Lucas De Marchi wrote:
On Fri, Jan 24, 2025 at 04:46:21PM -0800, Umesh Nerlige Ramappa wrote:
Hi Lucas,
Mostly a bunch of questions since I think I am missing something.
On Tue, Jan 21, 2025 at 10:59:08AM -0600, Lucas De Marchi wrote:
On Tue, Jan 21,
== Series Details ==
Series: drm/i915/dmc_wl: Do not check for DMC payload
URL : https://patchwork.freedesktop.org/series/143951/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16018 -> Patchwork_143951v1
Summary
---
Hi,
https://patchwork.freedesktop.org/series/143951/ - Re-reported.
i915.CI.BAT - Re-reported.
Thanks,
Ravali.
-Original Message-
From: I915-ci-infra On Behalf Of
Gustavo Sousa
Sent: 27 January 2025 19:01
To: i915-ci-in...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: i
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, January 28, 2025 12:44 AM
> To: Borah, Chaitanya Kumar
> Cc: Murthy, Arun R ; dri-
> de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org
> Subject: Re: [PATCH v3 2/5] drm/plane: Ex
== Series Details ==
Series: drm/i915: Give i915 and xe each their own display tracepoints
URL : https://patchwork.freedesktop.org/series/144005/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16030 -> Patchwork_144005v1
Sum
On Mon, Jan 27, 2025 at 02:33:01PM -0800, Vinay Belgaumkar wrote:
Simple tests for validating the PMU implementation for GT C6
residencies.
v2: Rename rc6-residency-* to gt-c6-residency and remove freq tests.
v3: Keep just gt-c6 tests, add frequency tests later.
v4: Review comments (Riana)
Cc:
== Series Details ==
Series: drm/i915: Fix page cleanup on DMA remap failure (rev4)
URL : https://patchwork.freedesktop.org/series/143614/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Mon, Jan 27, 2025 at 02:33:00PM -0800, Vinay Belgaumkar wrote:
Functions to parse event ID and GT bit shift for PMU events.
v2: Review comments (Riana)
Cc: Riana Tauro
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
lib/igt_perf.c | 70 ++
> -Original Message-
> From: Intel-xe On Behalf Of Ville
> Syrjala
> Sent: Friday, January 24, 2025 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org
> Subject: [PATCH 11/11] drm/i915: Pimp plane debugs
>
> From: Ville Syrjälä
>
> Include the standard
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