== Series Details ==
Series: drm/edid: filter DisplayID v2.0 CTA block in audio detection
URL : https://patchwork.freedesktop.org/series/101565/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11386_full -> Patchwork_22622_full
===
== Series Details ==
Series: drm: add a check to verify the size alignment
URL : https://patchwork.freedesktop.org/series/101569/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11387 -> Patchwork_22623
Summary
---
**S
WRT below, i believe this failure is unrelated due to the following reasons:
1. GuC submission wasn't enabled on below IGT (see bootlog:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22607/shard-iclb2/boot11.txt)
2. The failure was coming from a KMD plane scaling IGT and based on the dmesgs
Hi Lakshmi,
here would be again false positive on glk, glk doesn't use dpt which is
changed on my patch.
/Juha-Pekka
On 17.3.2022 4.31, Patchwork wrote:
*Patch Details*
*Series:* drm/i915/display: Add smem fallback allocation for dpt
*URL:* https://patchwork.freedesktop.org/series/1014
On Sun, 2022-03-20 at 02:12 +0530, Ramalingam C wrote:
> XY_FAST_COLOR_BLT cmd is faster than the older XY_COLOR_BLT. Hence
> for
> clearing (Zero out) the pages of the newly allocated object, faster
> cmd
> is used.
NIT: Imperative wording
>
> Signed-off-by: Ramalingam C
> Signed-off-by: Chris
On Mon, 21 Mar 2022, Cooper Chiou wrote:
> In DisplayID v2.0 CTS data block 0x81 case, there is no any audio
> information definition, but drm_detect_monitor_audio didn't filter
> it so that it caused eDP dummy audio card be detected improperly.
>
> We observed this issue on some AUO/BOE eDP panel
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/dp/drm_dp.c| 25 +
include/drm/dp/drm_dp_he
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/dp/drm_dp.c | 25
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Add DSC checks to intel_dp_mst_mode_valid_ctx, similar
to ones we have in intel_dp_mode_valid(Manasi Navare)
v3: Removed redundant edp condition logic
== Series Details ==
Series: drm: add a check to verify the size alignment
URL : https://patchwork.freedesktop.org/series/101569/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11387_full -> Patchwork_22623_full
Summary
== Series Details ==
Series: Add DP MST DSC support to i915 (rev2)
URL : https://patchwork.freedesktop.org/series/101492/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9b8bc9218f7e drm: Add missing DP DSC extended capability definitions.
-:45: CHECK:LINE_SPACING: Please don't u
== Series Details ==
Series: Add DP MST DSC support to i915 (rev2)
URL : https://patchwork.freedesktop.org/series/101492/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/am
== Series Details ==
Series: Add DP MST DSC support to i915 (rev2)
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11387 -> Patchwork_22624
Summary
---
**SUCCESS**
On Sat, 19 Mar 2022 at 02:06, Patchwork
wrote:
>
> Patch Details
> Series:Introduce multitile support
> URL:https://patchwork.freedesktop.org/series/101551/
> State:failure
> Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index.html
>
> CI Bug Log - changes from CI_DRM_11384_full
looks good to me overall but I would get others r-b.
Patches 1-3 Reviewed-by: Nirmoy Das
Patches 4-7 Acked-by: Nirmoy Das
On 03/03/2022 19:00, Balasubramani Vivekanandan wrote:
drm_memcpy_from_wc() performs fast copy from WC memory type using
non-temporal instructions. Now there are two simi
In the previous version I replied only to the mailing list email so
probably my email slipped through.
Reviewed-by: Nirmoy Das for patch 6-7
On 3/19/2022 9:42 PM, Ramalingam C wrote:
Add a parameter called "extra_pages" for ttm_tt_init, to indicate that
driver needs extra pages in ttm_tt.
v2
On 19/03/2022 19:42, Michael Cheng wrote:
To align with the discussion in [1][2], this patch series drops all usage of
wbvind_on_all_cpus within i915 by either replacing the call with certain
drm clflush helpers, or reverting to a previous logic.
AFAIU, complaint from [1] was that it is wrong
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everything at once to avoid paranoia.
And now we know, or we know it is not a concern?
To make i915 mor
On Sun, 2022-03-20 at 02:12 +0530, Ramalingam C wrote:
> While clearing the Flat-CCS capable lmem object, we need to clear the
> CCS
> meta data corresponding to the memory.
>
> As part of live_migrate_clear add check for the ccs meta data clear
> for
> the Flat-CCS capable lmem object.
>
> Signe
We are currently getting FIFO underruns, in particular
when PSR2 is enabled. There seem to be no existing workaround
or patches, which can fix that issue(were expecting some recent
selective fetch update and DBuf bw/SAGV fixes to help,
which unfortunately didn't).
Current idea is that it looks like
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/dp/drm_dp.c | 25
drivers/gpu/drm/i915/display/intel_dp.c | 75 +-
drivers
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/dp/drm_dp.c| 25 +
include/drm/dp/drm_dp_he
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
Signed-off-by
Hi, Tvrtko.
On 3/21/22 11:27, Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
To align with the discussion in [1][2], this patch series drops all
usage of
wbvind_on_all_cpus within i915 by either replacing the call with certain
drm clflush helpers, or reverting to a previous l
Thanks for the contribution, Colin. Queued.
On 3/15/22 8:24 PM, Colin Ian King wrote:
> There is a spelling mistake in a gvt_vgpu_err error message. Fix it.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On 3/21/22 11:30, Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everything at once to avoid paranoia.
And now we know, or we k
== Series Details ==
Series: drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used (rev2)
URL : https://patchwork.freedesktop.org/series/101533/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f2d79bd4ca6 drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used
-:32: CHECK:LINE_SPA
On Tue, Mar 15, 2022 at 03:27:30PM +0530, Ankit Nautiyal wrote:
> Add debug print for Procmon Ref values, to help get the
> voltage configurations of combo PHYs.
>
> v2: Used drm_dbg_kms for logs. (Jani)
> Added names for different voltage levels. (Imre)
>
> v3: Used const char * for names. (Jani
== Series Details ==
Series: drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used (rev2)
URL : https://patchwork.freedesktop.org/series/101533/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11389 -> Patchwork_22625
Summary
== Series Details ==
Series: Add DP MST DSC support to i915 (rev2)
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11387_full -> Patchwork_22624_full
Summary
---
*
ATM the drm privacy-screen code is not using connector names to lookup
drm privacy-screen providers, drm_privacy_screen_get() does support this,
but before this change the con_id is set to NULL everywhere which is
treated as a wildcard.
There are some worries that we may see devices with 2 display
On 21/03/2022 11:03, Thomas Hellström wrote:
Hi, Tvrtko.
On 3/21/22 11:27, Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
To align with the discussion in [1][2], this patch series drops all
usage of
wbvind_on_all_cpus within i915 by either replacing the call with certain
d
Change functions that always return '0' to be void type.
Signed-off-by: Andi Shyti
Reviewed-by: Maciej Patelczyk
---
Hi,
just resending it once more time. Matt, can you please commit
this refactoring if you are OK with it?
Andi
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 7 ---
driv
On Fri, 18 Mar 2022 at 09:22, Juha-Pekka Heikkila
wrote:
>
> On 17.3.2022 13.55, Matthew Auld wrote:
> > On Wed, 16 Mar 2022 at 22:23, Juha-Pekka Heikkila
> > wrote:
> >>
> >> Add fallback smem allocation for dpt if stolen memory
> >> allocation failed.
> >>
> >> Signed-off-by: Juha-Pekka Heikkil
On Mon, 2022-03-21 at 12:22 +, Tvrtko Ursulin wrote:
>
> On 21/03/2022 11:03, Thomas Hellström wrote:
> > Hi, Tvrtko.
> >
> > On 3/21/22 11:27, Tvrtko Ursulin wrote:
> > >
> > > On 19/03/2022 19:42, Michael Cheng wrote:
> > > > To align with the discussion in [1][2], this patch series drops
On 21/03/2022 00:54, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these 2 FBs where only one
is mappable/fenceable creates latencies
On Mon, 21 Mar 2022, Stanislav Lisovskiy wrote:
> Adding DP DSC register definitions, we might need for further
> DSC implementation, supporting MST and DP branch pass-through mode.
>
> v2: - Fixed checkpatch comment warning
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/dp/drm_d
On Fri, 18 Mar 2022, José Roberto de Souza wrote:
> From: Caz Yokoyama
>
> B credits set by IFWI do not match with specification default, so here
> programming the right value.
>
> Also while at it, taking the oportunity to do a read-modify-write to
> all other bit in this register that specifica
On Thu, 17 Mar 2022, Alan Previn wrote:
> Add device specific tables and register lists to cover different engines
> class types for GuC error state capture for XE_LP products.
>
> Signed-off-by: Alan Previn
> Reviewed-by: Umesh Nerlige Ramappa
Some random drive-by comments inline.
> ---
> ..
On 21/03/2022 12:33, Thomas Hellström wrote:
On Mon, 2022-03-21 at 12:22 +, Tvrtko Ursulin wrote:
On 21/03/2022 11:03, Thomas Hellström wrote:
Hi, Tvrtko.
On 3/21/22 11:27, Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
To align with the discussion in [1][2], this pa
Hi Nanley, JP,
On Tue, Feb 15, 2022 at 09:34:22PM +0200, Juha-Pekka Heikkila wrote:
> [...]
> > > > > > > > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > > > > > > > b/include/uapi/drm/drm_fourcc.h index
> > > > > > > > > b8fb7b44c03c..697614ea4b84 100644
> > > > > > > > > --- a/include/uapi
Hi,
On Mon, 2022-03-21 at 13:12 +, Tvrtko Ursulin wrote:
>
> On 21/03/2022 12:33, Thomas Hellström wrote:
> > On Mon, 2022-03-21 at 12:22 +, Tvrtko Ursulin wrote:
> > >
> > > On 21/03/2022 11:03, Thomas Hellström wrote:
> > > > Hi, Tvrtko.
> > > >
> > > > On 3/21/22 11:27, Tvrtko Ursuli
On 18/03/2022 18:08, fei.y...@intel.com wrote:
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalid
On Thu, 17 Mar 2022, Ville Syrjälä wrote:
> On Thu, Mar 17, 2022 at 07:33:55PM +0200, Jani Nikula wrote:
>> The kernel preference is to use the __packed macro instead of the direct
>> __attribute__.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Ville Syrjälä
Pushed, thanks.
BR,
Jani.
>
>
v2 of https://patchwork.freedesktop.org/series/101499/
Jani Nikula (7):
drm/i915/dmc: simplify intel_dmc_load_program() conditions
drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
drm/i915/dmc: move dmc debugfs to intel_dmc.c
drm/i915/dmc: fix i915_reg_t usage
drm/i915/dmc: abstract
intel_dmc_load_program() is only ever called when
intel_dmc_has_payload() is true. Move the condition within
intel_dmc_load_program() to let it be called directly.
Also note that intel_dmc_has_payload() will always return false when
HAS_DMC() is false. Remove the redundant check.
Signed-off-by: J
Start localizing DMC register and data access to intel_dmc.c.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12
drivers/gpu/drm/i915/display/intel_dmc.c | 11 +++
drivers/gpu/drm/i915/display/intel
Continue localizing DMC register and data access to intel_dmc.c.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_debugfs.c | 75 +
drivers/gpu/drm/i915/display/intel_dmc.c | 83 +++
drivers/gpu/drm/i915/display
i915_reg_t is supposed to be a somewhat opaque data type, not to be
looked inside.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.
Only intel_dmc.c should be accessing dmc details directly.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++
drivers/gpu/drm/i915/display/intel_dmc.h | 3 +++
drivers/gpu/drm/i915/i915_gpu_error.c| 10 +-
3 fi
The macros are now only needed within intel_dmc.c, so move them there.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4
drivers/gpu/drm/i915/display/intel_dmc.h | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a
Clean up the massive i915_reg.h a bit with this isolated set of
registers.
v2: Remove stale comment (Lucas)
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 1 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 30 +++
The initialization is there only to silence the compiler, but use the
correct initializer for i915_reg_t.
Cc: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/g
On Mon, Mar 21, 2022 at 02:44:20PM +0200, Jani Nikula wrote:
> On Mon, 21 Mar 2022, Stanislav Lisovskiy
> wrote:
> > Adding DP DSC register definitions, we might need for further
> > DSC implementation, supporting MST and DP branch pass-through mode.
> >
> > v2: - Fixed checkpatch comment warning
On Mon, Mar 21, 2022 at 03:59:55PM +0200, Jani Nikula wrote:
The initialization is there only to silence the compiler, but use the
correct initializer for i915_reg_t.
Cc: Lucas De Marchi
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/gt/
== Series Details ==
Series: drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used (rev2)
URL : https://patchwork.freedesktop.org/series/101533/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11389_full -> Patchwork_22625_full
===
On 21/03/2022 13:40, Thomas Hellström wrote:
Hi,
On Mon, 2022-03-21 at 13:12 +, Tvrtko Ursulin wrote:
On 21/03/2022 12:33, Thomas Hellström wrote:
On Mon, 2022-03-21 at 12:22 +, Tvrtko Ursulin wrote:
On 21/03/2022 11:03, Thomas Hellström wrote:
Hi, Tvrtko.
On 3/21/22 11:27, Tvrt
From: Jordan Justen
Also, document DRM_I915_QUERY_HWCONFIG_BLOB with this struct.
v3:
* Add various changes suggested by Tvrtko
v5:
* Fix documenation formatting and verified with `make htmldocs` as
suggested by Daniel
Cc: Daniel Vetter
Signed-off-by: Jordan Justen
Acked-by: Jon Bloomfi
On Mon, 2022-03-21 at 14:43 +, Tvrtko Ursulin wrote:
>
> On 21/03/2022 13:40, Thomas Hellström wrote:
> > Hi,
> >
> > On Mon, 2022-03-21 at 13:12 +, Tvrtko Ursulin wrote:
> > >
> > > On 21/03/2022 12:33, Thomas Hellström wrote:
> > > > On Mon, 2022-03-21 at 12:22 +, Tvrtko Ursulin wr
== Series Details ==
Series: drm/i915/display: Add smem fallback allocation for dpt
URL : https://patchwork.freedesktop.org/series/101443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11372_full -> Patchwork_22588_full
Sum
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
Summary
---
**SUCCESS**
On 2022-03-21 3:30 a.m., Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everything at once to avoid paranoia.
And now we know, o
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Then, populate GuC ADS with the lists of registers we want
GuC to report back to host on engine reset events. This list
should include global, engine-class and engine-instance
registers for e
This series:
1. Enables support of GuC to report error-state-capture
using a list of MMIO registers the driver registers
and GuC will dump, log and notify right before a GuC
triggered engine-reset event.
2. Updates the ADS blob creation to register said lists
of global, engi
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 insertions(+), 2
GuC log buffer regions for debug-log-events, crash-dumps and
error-state-capture are all part of a single bo allocation that
also includes the guc_log_buffer_state structures. Now that we
support it, increase the size allocation for error-capture.
Since the error-capture region is accessed at non-
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
.../gpu/drm/i91
Add a flags parameter through all of the coredump creation
functions. Add a bitmask flag to indicate if the top
level gpu_coredump event is triggered in response to
a GuC context reset notification.
Using that flag, ensure all coredump functions that
read or print mmio-register values related to w
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 47 ++
In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset_prepare's call
to flush_work(&guc->ct.requests.worker) can cau
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 112 ++
drivers/gpu/drm/i915/gt/
- Upon the G2H Notify-Err-Capture event, parse through the
GuC Log Buffer (error-capture-subregion) and generate one or
more capture-nodes. A single node represents a single "engine-
instance-capture-dump" and contains at least 3 register lists:
global, engine-class and engine-instance. An
Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.
Since GuC could have reported multiple engine register dumps
in a single notification event, parse t
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
Summary
---
**SUCCESS**
Issue is related to
https://gitlab.freedesktop.org/drm/intel/-/issues/1373
Few tests - incomplete - Kernel panic - not syncing: EXT4-fs (device
nvme0n1p2): panic forced after error|Kernel panic - not syncing: EXT4-fs panic
from previous error
Lakshmi.
-Original Message-
From: Matthew Au
Below one looks like a new issue
https://gitlab.freedesktop.org/drm/intel/-/issues/5386
igt@perf@stress-open-close - dmesg-fail - general protection fault, probably
for non-canonical address 0x6b6b6b6b6b6b6bcb, RIP: 0010:i915_oa_init_reg_state
Thanks,
Lakshmi.
-Original Message-
From: Juh
On Mon, 2022-03-21 at 12:49 +0200, Stanislav Lisovskiy wrote:
> We are currently getting FIFO underruns, in particular
> when PSR2 is enabled. There seem to be no existing workaround
> or patches, which can fix that issue(were expecting some recent
> selective fetch update and DBuf bw/SAGV fixes to
On Mon, 2022-03-21 at 12:49 +0200, Stanislav Lisovskiy wrote:
> We are currently getting FIFO underruns, in particular
> when PSR2 is enabled. There seem to be no existing workaround
> or patches, which can fix that issue(were expecting some recent
> selective fetch update and DBuf bw/SAGV fixes to
== Series Details ==
Series: drm/i915/display: Add smem fallback allocation for dpt
URL : https://patchwork.freedesktop.org/series/101443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11372_full -> Patchwork_22588_full
Sum
On 21/03/2022 16:31, Michael Cheng wrote:
On 2022-03-21 3:30 a.m., Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everything at
On 2022-03-21 10:28 a.m., Tvrtko Ursulin wrote:
On 21/03/2022 16:31, Michael Cheng wrote:
On 2022-03-21 3:30 a.m., Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the
On 2022-03-21 10:28 a.m., Tvrtko Ursulin wrote:
On 21/03/2022 16:31, Michael Cheng wrote:
On 2022-03-21 3:30 a.m., Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the
Freq caps (i.e. RP0, RP1 and RPn frequencies) are read from HW. However the
formats (bit positions, widths, registers and units) of these vary for
different generations with even more variations arriving in the future. In
order not to have to do identical computation for these caps in multiple
plac
On Mon, Mar 21, 2022 at 10:56:04AM -0700, Ashutosh Dixit wrote:
diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h
b/drivers/gpu/drm/i915/gt/intel_rps_types.h
index 3941d8551f52..5990df35b393 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps_types
On 21.3.2022 14.29, Matthew Auld wrote:
On Fri, 18 Mar 2022 at 09:22, Juha-Pekka Heikkila
wrote:
On 17.3.2022 13.55, Matthew Auld wrote:
On Wed, 16 Mar 2022 at 22:23, Juha-Pekka Heikkila
wrote:
Add fallback smem allocation for dpt if stolen memory
allocation failed.
Signed-off-by: Juha-Pe
== Series Details ==
Series: Add DP MST DSC support to i915 (rev3)
URL : https://patchwork.freedesktop.org/series/101492/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5e516f0e4e89 drm: Add missing DP DSC extended capability definitions.
-:45: CHECK:LINE_SPACING: Please don't u
== Series Details ==
Series: Add DP MST DSC support to i915 (rev3)
URL : https://patchwork.freedesktop.org/series/101492/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/am
On 2022-03-21 4:07 a.m., Thomas Hellström wrote:
On 3/21/22 11:30, Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everything at
On Wed, Mar 16, 2022 at 10:00:06AM +0200, Jani Nikula wrote:
> On Fri, 18 Feb 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Initialize on-stack modes with drm_mode_init() to guarantee
> > no stack garbage in the list head, or that we aren't copying
> > over another mode's list head.
== Series Details ==
Series: Add DP MST DSC support to i915 (rev3)
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11393 -> Patchwork_22626
Summary
---
**SUCCESS**
On Mon, 21 Mar 2022 11:17:46 -0700, Lucas De Marchi wrote:
>
> On Mon, Mar 21, 2022 at 10:56:04AM -0700, Ashutosh Dixit wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h
> > b/drivers/gpu/drm/i915/gt/intel_rps_types.h
> > index 3941d8551f52..5990df35b393 100644
> > --- a/drivers/gp
On Thu, Mar 03, 2022 at 11:30:08PM +0530, Balasubramani Vivekanandan wrote:
Fast copy using non-temporal instructions for x86 currently exists at two
locations. One is implemented in i915 driver at i915/i915_memcpy.c and
another copy at drm_cache.c. The plan is to remove the duplicate
implementat
== Series Details ==
Series: drm/privacy-screen: Use connector name in lookup
URL : https://patchwork.freedesktop.org/series/101582/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11393 -> Patchwork_22627
Summary
---
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next v5.17 next-20220321]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
From: Ville Syrjälä
Clean up a few random things that caught my eye.
Ville Syrjälä (3):
drm/i915: Program i830 DPLL FP register later
drm/i915: Use drm_connector_attach_hdr_output_metadata_property()
drm/i915: Remove dead members from dev_priv
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Follow the new i9xx DPLL FP register programming sequence
introduced in commit 62d66b218386 ("drm/i915: Fold
i9xx_set_pll_dividers() into i9xx_enable_pll()") in the
i830 "power well" code as well. Just for consistency.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/d
From: Ville Syrjälä
Stop hand rolling drm_connector_attach_hdr_output_metadata_property().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu
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