== Series Details ==
Series: i915/display: split and constify vtable
URL : https://patchwork.freedesktop.org/series/94459/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10560_full -> Patchwork_20985_full
Summary
---
== Series Details ==
Series: Enable GuC submission by default on DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/93325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10560_full -> Patchwork_20986_full
Summary
Hi, Matt,
Thanks for reviewing.
On 9/7/21 7:37 PM, Matthew Auld wrote:
+ i915_gem_ww_unlock_single(backup);
+ i915_gem_object_put(backup);
I assume we need to set ttm.backup = NULL somewhere here on the
failure path, or don't drop the ref? Or at least it looks like
potential uaf lat
On 07/09/2021 12:13, Eero Tamminen wrote:
Hi,
For completeness sake, it might be worth mentioning specifically what
(synthetic) test-cases regress with THP patch.
* Skylake GT4e:
20-25% SynMark TexMem*
(whereas all MemBW GPU tests either improve or are not affected)
* Broxton J4205:
On Tue, 07 Sep 2021, Lucas De Marchi wrote:
> Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
> gt aware debugfs") says it was moving debug files to gt/, the
> i915_frequency_info file was left behind and its implementation copied
> into drivers/gpu/drm/i915/gt/debugfs_gt_pm
On Wed, Sep 8, 2021 at 5:14 AM Masahiro Yamada wrote:
>
> On Mon, Sep 6, 2021 at 4:34 PM Daniel Vetter wrote:
> >
> > On Mon, Sep 6, 2021 at 12:49 AM Stephen Rothwell
> > wrote:
> > > Hi all,
> > >
> > > On Thu, 2 Sep 2021 07:50:38 +1000 Stephen Rothwell
> > > wrote:
> > > >
> > > > On Fri, 2
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This reworks the uncore function vtable so that it's constant.
There's a bug in there, see comment inline, with that fixed,
Reviewed-by: Jani Nikula
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/i915/intel_uncore.c |
On 08/09/2021 00:27, Vinay Belgaumkar wrote:
Seeing these errors when GT is likely in suspend state-
"RPM wakelock ref not held during HW access"
Ensure GT is awake before trying to access HW registers. Avoid
reading the register if that is not the case.
Signed-off-by: Vinay Belgaumkar
Fix
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> constify it while here. drop the put function since it was never
> overloaded and always has done the same thing, no point in
> indirecting it for show.
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 6
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> A vague goal is to have the vfunc table be the api between
> wm and display, not having direction function calls cross
> the boundary.
>
> This aligns the legacy update_wm with the newer vfuncs.
>
> The comment probably needs to live
Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.
These patches are basic enablement patches and reused psr
framework to add panel replay related new changes which
may need further fine tuning to fill the gap if there is any.
Note: The patches are not tested due
Panel replay can be enabled for all pipes driving DP 2.0 monitor,
so updated the plane selective fetch register difinition accordingly.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 8 +++---
drivers/gpu/drm/i915/i915_reg.h | 32 +---
2
Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a feature flag
for panel replay.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_inf
As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 4 ++
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++
drivers/gpu/
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 30
drivers/gpu/drm/i915/i915_reg.h | 1 +
i
has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> These are the watermark api between display and pm.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 54 ++--
> drivers/gpu/drm/i915/i915_drv.h | 24 ++---
> drivers/gpu/drm/i915/intel_pm.c
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> These are only used internally in the color module
I think this patch is a testament to my comment on wrappers for calling
vfuncs. It's all intel_color.c implementation details.
Reviewed-by: Jani Nikula
I might nitpick on the cho
On 07/09/2021 18:19, Matt Roper wrote:
Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).
To begin with, define the compute class/engine common functions, based
on the existing render ones.
Bspec: 46167, 45544
Original-patc
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> These are only used internally in the audio code
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 24 +++---
> drivers/gpu/drm/i915/i915_drv.h| 19 +++--
> 2 files changed, 25 insertions(+
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
Commit message.
>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c| 148 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> .../drm/i915/display/intel_display_power.c| 2 +-
> drivers/gpu/drm/i9
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This provide a service from irq to display, so make it separate
> ---
> drivers/gpu/drm/i915/display/intel_hotplug.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 9 -
> drivers/gpu/drm/i915/i915_irq.c
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> It may make sense to merge this with display again later,
> however the fdi use of the vtable is limited to only a
> few generations.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel
On 07/09/2021 18:19, Matt Roper wrote:
The reset domain is shared between render and all compute engines,
so resetting one will affect the others.
Note: Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impac
On 07/09/2021 18:19, Matt Roper wrote:
Add execlists and GuC interrupts for compute CS into existing IRQ handlers.
All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.
CCS0
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> this could be merged later but for now it's simple to split it out.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_dpll.c| 16
> drivers/gpu/drm/i915/i915_
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> Avoid having writeable function pointers.
Would benefit from the call wrapper and naming.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 1
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> Use a macro to avoid mistakes, this type of macro is only used
> in a couple of places.
> ---
> drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i9
On 07/09/2021 18:19, Matt Roper wrote:
The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.
The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the c
== Series Details ==
Series: i915/uncore: constify the uncore vtables. (rev2)
URL : https://patchwork.freedesktop.org/series/94465/
State : failure
== Summary ==
Applying: drm/i915/uncore: split the fw get function into separate vfunc
Applying: drm/i915/uncore: constify the register vtables.
e
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
The commit message could contain some words about how ugly this used to
be and how beautiful it is now. Awesome.
One bug, comment inline.
>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 138 ++---
> drivers/gpu
== Series Details ==
Series: Panel replay phase1 implementation
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c7704eae2ab0 drm/i915/panelreplay: update plane selective fetch register
definition
-:8: WARNING:TYPO_SPELLING: '
On Tue, Sep 07, 2021 at 03:20:44PM +0200, Maarten Lankhorst wrote:
> i915 will soon gain an eviction path that trylock a whole lot of locks
> for eviction, getting dmesg failures like below:
>
> BUG: MAX_LOCK_DEPTH too low!
> turning off the locking correctness validator.
> depth: 48 max: 48!
> 4
== Series Details ==
Series: Panel replay phase1 implementation
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 43 ++
> drivers/gpu/drm/i915/i915_drv.h| 2 +-
> 2 files changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a/d
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
Reviewed-by: Jani Nikula
>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +--
> drivers/gpu/drm/i915/display/intel_dpll.c| 49
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 3 files ch
On 06/09/2021 17:55, Thomas Hellström wrote:
Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.
Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose
== Series Details ==
Series: Panel replay phase1 implementation
URL : https://patchwork.freedesktop.org/series/94470/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10562 -> Patchwork_20989
Summary
---
**SUCCESS**
On 06/09/2021 17:55, Thomas Hellström wrote:
Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.
Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose
On Thu, 02 Sep 2021, Lee Shawn C wrote:
> So far, DCS backlight driver hardcode (0xFF) for max brightness level.
> MIPI DCS spec allow max 0x for set_display_brightness (51h) command.
> And VBT brightness precision bits can support 8 ~ 16 bits.
>
> We should set correct precision bits in VBT t
On Thu, 02 Sep 2021, Lee Shawn C wrote:
> VDSC engine can process only 1 pixel per Cd clock. In case
> VDSC is used and max slice count == 1, max supported pixel
> clock should be 100% of CD clock. Then do min_cdclk and
> pixel clock comparison to get proper min cdclk.
>
> v2:
> - Check for dsc en
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> The i845_update_wm code was always calling the i845 variant,
> and the i9xx_update_wm had only a choice between i830 and i9xx
> paths, hardly worth the vfunc overhead.
>
> Signed-off-by: Dave Airlie
Reviewed-by: Jani Nikula
> ---
On Wed, 08 Sep 2021, David Airlie wrote:
> On Wed, Sep 8, 2021 at 10:39 AM Dave Airlie wrote:
>>
>> From: Dave Airlie
>>
>> The crtc was never being used here.
>
> /me realises I've noobed up the Sob on these,
>
> I've added them to my tree locally and in the branch I posted to the
> other threa
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> The crtc was never being used here.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This function is only used inside intel_pm.c
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9 ++-
> drivers/gpu/drm/i915/intel_pm.c | 48 -
> 2 files changed, 32 insertions(+), 25 deletions(-)
>
> di
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> There was some excess comments and an unused vtbl ptr.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu
v2: Get data length of brightness value more easily while driver try to
read/write MIPI_DCS_DISPLAY_BRIGHTNESS command.
v3: fix checkpatch warning.
Signed-off-by: Lee Shawn C
Lee Shawn C (5):
drm/i915/dsi: wait for header and payload credit available
drm/i915/dsi: refine send MIPI DCS co
Driver should wait for free header or payload buffer in FIFO.
It would be good to wait a while for HW to release credit before
give it up to write to HW. Without sending initailize command
sets completely. It would caused MIPI display can't light up properly.
Cc: Ville Syrjala
Cc: Jani Nikula
Cc
VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confir
According to chapter "Sending Commands to the Panel" in bspec #29738
and #49188. If driver try to send DCS long pakcet, we have to program
TX payload register at first. And configure TX header HW register later.
DSC long packet would not be sent properly if we don't follow this
sequence.
Cc: Ville
So far, DCS backlight driver hardcode (0xFF) for max brightness level.
MIPI DCS spec allow max 0x for set_display_brightness (51h) command.
And VBT brightness precision bits can support 8 ~ 16 bits.
We should set correct precision bits in VBT that meet panel's request.
Driver can refer to this
Driver has to swap the endian before send brightness level value
to tcon.
v2: Use __be16 instead of u16 to fix sparse warning.
v3: Send one or two bytes brightness value depend on the precision.
v4: get data length of brightness value more easily.
Reported-by: kernel test robot
Cc: Ville Syrjala
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This is a bit of a twisty one since each platform is slightly
> different, so might take some more review care.
Yes, it was a PITA to review. But the end result is good.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/dis
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
Reviewed-by: Jani Nikula
>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 81
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 2 files changed, 52 insertions(+), 31 deletions(-)
>
> diff --git a
On Mon, Sep 6, 2021 at 4:34 PM Daniel Vetter wrote:
>
> On Mon, Sep 6, 2021 at 12:49 AM Stephen Rothwell
> wrote:
> > Hi all,
> >
> > On Thu, 2 Sep 2021 07:50:38 +1000 Stephen Rothwell
> > wrote:
> > >
> > > On Fri, 20 Aug 2021 15:23:34 +0900 Masahiro Yamada
> > > wrote:
> > > >
> > > > On F
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> I used a macro to avoid making any really silly mistakes here.
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 77 +++--
> 2 files changed, 54 insertions(+), 25 deleti
On Wed, 08 Sep 2021, Jani Nikula wrote:
> On Wed, 08 Sep 2021, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> I used a macro to avoid making any really silly mistakes here.
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_pm.c | 77 +++-
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> Avoid having writeable function pointers.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 18 +++---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>
On Wed, 08 Sep 2021, Patchwork wrote:
> == Series Details ==
>
> Series: i915/display: split and constify vtable
> URL : https://patchwork.freedesktop.org/series/94459/
> State : warning
>
> == Summary ==
>
> $ make htmldocs 2>&1 > /dev/null | grep i915
> ./drivers/gpu/drm/i915/display/intel_dis
== Series Details ==
Series: DSI driver improvement (rev4)
URL : https://patchwork.freedesktop.org/series/94237/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_eng
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This adds some extra checks for the table pointer being
> valid due to some paths not setting it due to failing
> CxSR.
Can we just add a
static const struct drm_i915_wm_disp_funcs nop_wm_funcs = {
};
and point dev_priv->wm_disp a
On Wed, 08 Sep 2021, Dave Airlie wrote:
> This is orthogonal to my display ptr refactoring and should probably
> be applied first.
Yeah, overall nice cleanups, and a much easier bandwagon to jump onto
than the other one. ;)
Nothing too bad, a few bugs had crept in, and I had some nitpicks.
> Th
On Wed, 08 Sep 2021, Lee Shawn C wrote:
> v2: Get data length of brightness value more easily while driver try to
> read/write MIPI_DCS_DISPLAY_BRIGHTNESS command.
> v3: fix checkpatch warning.
The series is v4, what's new here?
BR,
Jani.
>
> Signed-off-by: Lee Shawn C
>
> Lee Shawn C (5)
On Wed, 2021-09-08 at 12:07 +0100, Matthew Auld wrote:
> On 06/09/2021 17:55, Thomas Hellström wrote:
> > Pinned context images are now reset during resume. Don't back them
> > up,
> > and assuming that rings can be assumed empty at suspend, don't back
> > them
> > up either.
> >
> > Introduce a n
== Series Details ==
Series: DSI driver improvement (rev4)
URL : https://patchwork.freedesktop.org/series/94237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10562 -> Patchwork_20990
Summary
---
**SUCCESS**
No re
On Wed, 08 Sep 2021, Jani Nikula wrote:
>On Wed, 08 Sep 2021, Lee Shawn C wrote:
>> v2: Get data length of brightness value more easily while driver try to
>> read/write MIPI_DCS_DISPLAY_BRIGHTNESS command.
>> v3: fix checkpatch warning.
>
>The series is v4, what's new here?
>
>BR,
>Jani.
>
On 08/09/2021 13:26, Thomas Hellström wrote:
On Wed, 2021-09-08 at 12:07 +0100, Matthew Auld wrote:
On 06/09/2021 17:55, Thomas Hellström wrote:
Pinned context images are now reset during resume. Don't back them
up,
and assuming that rings can be assumed empty at suspend, don't back
them
up eit
These errors did not relate to this patch series. Thanks!
Best regards,
Shawn
From: Patchwork
Sent: Friday, September 3, 2021 3:21 AM
To: Lee, Shawn C
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for DSI driver improvement (rev3)
Patch Details
Series:
DSI driver improveme
On 08/09/2021 11:13, Tvrtko Ursulin wrote:
On 07/09/2021 18:19, Matt Roper wrote:
The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.
The CCS context state (lrc) is also similar to
On 07/09/2021 18:19, Matt Roper wrote:
In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.
The context priority i
On 07/09/2021 18:19, Matt Roper wrote:
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
Bspec: 46034
Original-patch-by: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Ara
On Wed, Sep 08, 2021 at 11:54:40AM +0300, Jani Nikula wrote:
On Tue, 07 Sep 2021, Lucas De Marchi wrote:
Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
gt aware debugfs") says it was moving debug files to gt/, the
i915_frequency_info file was left behind and its implemen
> -Original Message-
> From: Lee, Shawn C
> Sent: Wednesday, September 8, 2021 6:42 PM
> To: Nikula, Jani ; intel-gfx@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Kulkarni, Vandita
> ; Chiou, Cooper ;
> Tseng, William
> Subject: RE: [v4 0/5] DSI driver improvement
>
> On We
On 07/09/2021 18:19, Matt Roper wrote:
From: John Harrison
Now that OpenCL workloads can run on the compute engine, we need to set
preempt_timeout_ms = 0 on the CCS engines too.
Signed-off-by: John Harrison
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +
== Series Details ==
Series: Panel replay phase1 implementation
URL : https://patchwork.freedesktop.org/series/94470/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10562_full -> Patchwork_20989_full
Summary
---
**FAI
Quoting Siddiqui, Ayaz A (2021-09-07 08:43:52)
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Talla
> > Raviteja Goud
> > Sent: Friday, September 3, 2021 11:51 PM
> > To: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> > ; Meena, Mahesh
> > ; Pandey, H
On Wed, Sep 08, 2021 at 07:14:00AM -0700, Lucas De Marchi wrote:
On Wed, Sep 08, 2021 at 11:54:40AM +0300, Jani Nikula wrote:
On Tue, 07 Sep 2021, Lucas De Marchi wrote:
Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
gt aware debugfs") says it was moving debug files to
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
URL : https://patchwork.freedesktop.org/series/94278/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6374ded0c677 drm/i915/ttm: Implement a function to copy the contents of two
TTM-base
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
URL : https://patchwork.freedesktop.org/series/94278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10563 -> Patchwork_20991
Summar
== Series Details ==
Series: DSI driver improvement (rev4)
URL : https://patchwork.freedesktop.org/series/94237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10562_full -> Patchwork_20990_full
Summary
---
**SUCCESS*
On Tue, Sep 07, 2021 at 10:19:09AM -0700, Matt Roper wrote:
> Introduce a Compute Command Streamer (CCS), which has access to
> the media and GPGPU pipelines (but not the 3D pipeline).
>
> To begin with, define the compute class/engine common functions, based
> on the existing render ones.
>
> Bs
On Tue, Sep 07, 2021 at 10:19:10AM -0700, Matt Roper wrote:
> The reset domain is shared between render and all compute engines,
> so resetting one will affect the others.
>
> Note: Before performing a reset on an RCS or CCS engine, the GuC will
> attempt to preempt-to-idle the other non-hung RCS
On Thu, Sep 02, 2021 at 04:01:40PM +0100, Tvrtko Ursulin wrote:
>
> On 02/09/2021 15:33, Daniel Vetter wrote:
> > On Tue, Aug 31, 2021 at 02:18:15PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 31/08/2021 13:43, Daniel Vetter wrote:
> > > > On Tue, Aug 31, 2021 at 10:15:03AM +0100, Tvrtko Ursulin
On Thu, Sep 02, 2021 at 10:57:37PM +0100, Colin King wrote:
> From: Colin Ian King
>
> There is a statement that is indented one character too deeply,
> clean this up.
>
> Signed-off-by: Colin Ian King
Queued to drm-intel-gt-next, thanks for patch.
-Daniel
> ---
> drivers/gpu/drm/i915/gt/int
On Fri, Sep 03, 2021 at 12:24:05PM +0100, Matthew Auld wrote:
> Currently we blow up in trace_dma_fence_init, when calling into
> get_driver_name or get_timeline_name, since both the engine and context
> might be NULL(or contain some garbage address) in the case of newly
> allocated slab objects vi
Hi Dave and Daniel,
here's this week's PR for drm-misc-fixes. One patch is a potential deadlock
in TTM, the other enables an additional plane in kmb. I'm slightly unhappy
that the latter one ended up in -fixes as it's not a bugfix AFAICT.
Best regards
Thomas
drm-misc-fixes-2021-09-08:
Short summ
On Wed, Sep 08, 2021 at 12:14:23PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 07, 2021 at 03:20:44PM +0200, Maarten Lankhorst wrote:
> > i915 will soon gain an eviction path that trylock a whole lot of locks
> > for eviction, getting dmesg failures like below:
> >
> > BUG: MAX_LOCK_DEPTH too low!
execlists_dequeue() is invoked from a function which uses
local_irq_disable() to disable interrupts so the spin_lock() behaves
like spin_lock_irq().
This breaks PREEMPT_RT because local_irq_disable() + spin_lock() is not
the same as spin_lock_irq().
execlists_dequeue_irq() and execlists_dequeue()
Clark Williams reported two issues with the i915 driver running on
PREEMPT_RT. While #1 looks simple I have no idea about #2 thus the RFC.
Sebastian
Disabling interrupts and invoking the irq_work function directly breaks
on PREEMPT_RT.
PREEMPT_RT does not invoke all irq_work from hardirq context because
some of the user have spinlock_t locking in the callback function.
These locks are then turned into a sleeping locks which can not be
acquired
== Series Details ==
Series: drm/i915/gt: Locking splats PREEMPT_RT
URL : https://patchwork.freedesktop.org/series/94480/
State : failure
== Summary ==
Applying: drm/i915/gt: Queue and wait for the irq_work item.
Applying: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() +
spin
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Panel replay can be enabled for all pipes driving DP 2.0 monitor,
> so updated the plane selective fetch register difinition accordingly.
It should mention that this changes are to accommodate differences in DG2.
Anyways, DG2 had PSR2 supp
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a feature flag
> for panel replay.
As all display 13 and newer platforms supports it would be better to have
#define HAS_PR(i915) (DISPLAY_V
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> Signed-off-by: Animesh Manna
> ---
> .../drm/i915/display/intel_display_types.h| 4 ++
> drivers/gpu/dr
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, September 9, 2021 12:57 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong ; Nikula, Jani
> ; Kahola, Mika ; Navare,
> Manasi D
> Subject: Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
URL : https://patchwork.freedesktop.org/series/94278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10563_full -> Patchwork_20991_full
==
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from source
> and sink is enabled through panel replay dpcd configuration address.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 30
On Mon, Aug 30, 2021 at 02:09:57PM +0200, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_eng
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, September 9, 2021 1:02 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong ; Nikula, Jani
> ; Kahola, Mika ; Navare,
> Manasi D
> Subject: Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initiali
On Thu, 2021-09-09 at 01:20 +0530, Manna, Animesh wrote:
>
> > -Original Message-
> > From: Souza, Jose
> > Sent: Thursday, September 9, 2021 1:02 AM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org
> > Cc: Mun, Gwan-gyeong ; Nikula, Jani
> > ; Kahola, Mika ; Navare,
> > Man
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