On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Panel replay can be enabled for all pipes driving DP 2.0 monitor,
> so updated the plane selective fetch register difinition accordingly.
It should mention that this changes are to accommodate differences in DG2.
Anyways, DG2 had PSR2 support dropped so we don't need this whole patch.
>
> Signed-off-by: Animesh Manna <animesh.ma...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8 +++---
> drivers/gpu/drm/i915/i915_reg.h | 32 +++++++++++++-----------
> 2 files changed, 22 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3f6fb7d67f84..5fa76b148f6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> intel_plane *plane,
>
> val = plane_state ? plane_state->ctl : 0;
> val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe,
> plane->id), val);
> if (!val || plane->id == PLANE_CURSOR)
> return;
>
> @@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct
> intel_plane *plane,
>
> val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> val |= plane_state->uapi.dst.x1;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe,
> plane->id), val);
>
> /* TODO: consider auxiliary surfaces */
> x = plane_state->uapi.src.x1 >> 16;
> y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
> val = y << 16 | x;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe,
> plane->id),
> val);
>
> /* Sizes are 0 based */
> val = (drm_rect_height(clip) - 1) << 16;
> val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe,
> plane->id), val);
> }
>
> void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..5bc8f22fa9a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7471,6 +7471,7 @@ enum {
> #define _SEL_FETCH_PLANE_BASE_7_A 0x70960
> #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
> #define _SEL_FETCH_PLANE_BASE_1_B 0x70990
> +#define _DG2_SEL_FETCH_PLANE_BASE_1_B 0x71890
>
> #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
> _SEL_FETCH_PLANE_BASE_1_A, \
> @@ -7481,31 +7482,34 @@ enum {
> _SEL_FETCH_PLANE_BASE_6_A, \
> _SEL_FETCH_PLANE_BASE_7_A, \
> _SEL_FETCH_PLANE_BASE_CUR_A)
> -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A,
> _SEL_FETCH_PLANE_BASE_1_B)
> -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> - _SEL_FETCH_PLANE_BASE_1_A + \
> - _SEL_FETCH_PLANE_BASE_A(plane))
> +#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A, \
> + DISPLAY_VER(dev_priv) >
> 12 ? \
> +
> _DG2_SEL_FETCH_PLANE_BASE_1_B : \
> + _SEL_FETCH_PLANE_BASE_1_B)
> +#define _SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane)
> (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
> + _SEL_FETCH_PLANE_BASE_1_A
> + \
> +
> _SEL_FETCH_PLANE_BASE_A(plane))
>
> #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
> -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe,
> plane) + \
> +#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> _SEL_FETCH_PLANE_CTL_1_A - \
> _SEL_FETCH_PLANE_BASE_1_A)
> #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
>
> #define _SEL_FETCH_PLANE_POS_1_A 0x70894
> -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe,
> plane) + \
> - _SEL_FETCH_PLANE_POS_1_A - \
> - _SEL_FETCH_PLANE_BASE_1_A)
> +#define PLANE_SEL_FETCH_POS(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> +
> _SEL_FETCH_PLANE_POS_1_A - \
> +
> _SEL_FETCH_PLANE_BASE_1_A)
>
> #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
> -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe,
> plane) + \
> - _SEL_FETCH_PLANE_SIZE_1_A - \
> - _SEL_FETCH_PLANE_BASE_1_A)
> +#define PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> +
> _SEL_FETCH_PLANE_SIZE_1_A - \
> +
> _SEL_FETCH_PLANE_BASE_1_A)
>
> #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
> -#define PLANE_SEL_FETCH_OFFSET(pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> - _SEL_FETCH_PLANE_OFFSET_1_A -
> \
> - _SEL_FETCH_PLANE_BASE_1_A)
> +#define PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> +
> _SEL_FETCH_PLANE_OFFSET_1_A - \
> +
> _SEL_FETCH_PLANE_BASE_1_A)
>
> /* SKL new cursor registers */
> #define _CUR_BUF_CFG_A 0x7017c
